An 8-b Cascaded Folding A/D Converter

with a New Fully Differential Source Follower

Inkyung Hwang*, Daehyuk Kim*, Ji-Hyun Roh**, Mun-Kyo Lee**, Sun-Phil Nah***
and Minkyu Song*
*Dept. of Semiconductor Science, Dongguk University, Seoul, KOREA
** Samsung Thales. Co.Ltd, Yongin, KOREA
*** Agency for Defense Development, Daejeon, KOREA
mksong@dongguk.edu

Abstract— Conventionally, source followers have been used problems, accurate voltage transfer can be obtained by using
at the block of track-and-hold amplifiers (THA) for high- a low output impedance voltage follower configured from
speed medium-bit analog-to-digital converters (ADCs). Even an operational amplifier. To avoid instabilities, however, the
though the input signals of an ADC are fully differential, two voltage follower with an op-amp only operates at low
single-ended source followers should be normally used. This is frequencies [6]. The other solution is a conventional source
because differential source followers have some drawbacks. In
follower as shown in Fig.1. Although the source follower
this study, a wideband fully differential source follower is
presented to obtain maximum efficiency of a fully differential operates at high frequencies, it has a problem of high output
THA. Because a cross coupling technique at the differential impedance [7].
nodes is adopted, the performance of the proposed source In this paper, a wideband fully differential source
follower is superior to the performance of conventional follower is presented. Using the principle of interference
followers. The result of Spurious Free Dynamic Range(SFDR) between differential nodes, we can reduce the output
is -66.92dBc for Fin=Fs/2 at FS=500MHz. The SFDR of the impedance of the proposed source follower compared to the
proposed source follower is better by about 8.6dB than the output impedance of conventional followers at the same
SFDR of a conventional source follower under the same power dissipation and area. In addition, a fully differential
experimental conditions. To verify them, an 8-b cascaded structure can reduce noises and mismatching problems.
folding ADC which includes the proposed source follower is This paper is organized as follows. The principles of
fabricated with a 0.13um CMOS technology. conventional and proposed source followers are discussed
in Section II. Frequency characteristics and fast Fourier
I. INTRODUCTION transform (FFT) simulations are presented in Section III.
Finally, our conclusions are given in Section IV.
In recent years, many systems such as software defined
radios (SDR), high quality video signal digitizers, and
digital radar receivers (DRR) have included a built-in high
performance analog-to-digital converter (ADC) for an
analog Intellectual Property(IP). These ADCs need
specifications such as a resolution of 8-10 bits, a clock
sampling beyond 500MHz, a wide input bandwidth, low
power consumption of a few hundred milliwatts [1], and so
on. A THA, which is required at the front end of most
ADCs, plays a significant role [2]. A THA is generally
composed of a metal-oxide semiconductor (MOS) switch, a
holding capacitor, and a voltage follower. A voltage
follower is often used in many high speed or high
frequency applications [3]. While a closed-loop voltage
follower based on an op-amp is used for high resolution
ADCs above 10 bits, an open-loop voltage follower based
on a source follower circuit is normally used for medium
resolution ADCs below 8 bits. In the case of a closed-loop
Fig. 1. Circuit diagram of open-loop THA with the conventional single-
voltage follower, a fully differential type can be supported ended source follower for high-speed and medium-bit ADC
because a fully differential op-amp can be designed. For an
open-loop voltage follower, however, a fully differential
type cannot be supported in a conventional source follower. II. SCHEME OF SOURCE FOLLOWERS
Normally, a voltage follower needs low output
impedance to satisfy a wide bandwidth input signal. A. Conventional single-ended source followers
Furthermore, some applications such as source degeneration Many kinds of source followers have been published for
trans-conductors [4] and triode operating trans-conductors analog output buffers [8]-[17]. Among them, a basic source
[5] require a low output impedance node to ensure a unity follower shown in Fig.2(a) is widely used [8] because of
gain or to suppress voltage variations. To solve these the circuit simplicity. However, the circuit has several
disadvantages[6]. First, due to the variation of dc bias of the proposed source follower is determined not only by
current, the VGS of input MOS is highly signal-dependant. M1, M3, M5, and M7, but also by M6. Further, M7 and M8
Thus, serious distortions could be produced in the output are connected to the opposite side with cross coupling.
node. Second, although the output impedance of the source Therefore, the proposed fully differential source follower
follower should be very low to obtain a unity gain, it is not can reduce the output impedance drastically and improves
low. Normally, the output impedance of a basic source the input bandwidth widely. Further, the noises and
follower is 1/gm1 with a value of several kΩ. Since the mismatching problems can be reduced.
desired value of output impedance is generally 10 to 50 Ω,
the output impedance must be reduced. The only way to
decrease the output impedance is to increase the trans-
conductance gain, which means a large bias current and
large W/L dimensions. Therefore, power consumption and
chip area are increased.
To overcome the drawbacks of a basic source follower,
the flipped voltage follower shown in Fig.2(b) has been
designed [9]. The flipped voltage follower has two
advantages. The first advantage is that the current through
input MOS is constant and independent of the input voltage,
because a current source is placed at the drain of input
MOS. The second advantage is that the output impedance
is much lower than that of the basic source follower [9].
However, the flipped voltage follower has a disadvantage.
Although the minimum supply voltage of this topology is
VGS+VDsat, the output voltage swing of the flipped voltage (a) (b) (c)
follower is decreased to VGS - 2VDsat which seriously
reduces the output swing performance in the deep sub- Fig. 2. Circuit diagrams of conventional source followers, (a) basic source
follower, (b) flipped voltage follower, and (c) super source follower
micron CMOS process [6]. Since the voltage swing is
especially important for analog circuits with the reduction
trend of supply voltage, the output swing of the flipped
voltage follower is too small.
Fig. 2(c) shows a super source follower with a wide
output swing and low distortion [14], [15]. The source and
drain of M1 is connected to the Vout node and Vx node,
respectively. The gate and source of M4 is connected to the
Vout node and Vx node, respectively. Since the super source
follower generates a feedback loop, the fixed Ron resistance
of M1 and the linearity of the voltage follower are
improved. Among conventional source followers, the super
source follower has the best performance. Nevertheless, the
super source follower is a single-ended type. Since we
cannot design a fully differential super source follower,
only the single-ended THA shown in Fig. 1 is still available.
B. A proposed differential source follower
Since conventional source followers are single-ended Fig. 3. THA with a fully differential source follower.
types, they are not appropriate schemes for a THA that has
a fully differential input signal. A fully differential THA is
shown in Fig. 3. If the input signal is fully differential, we
need a fully differential source follower rather than a
conventional single-ended source follower.
Fig.4 shows the circuit diagram of a conventional fully
differential source follower [16]. This is composed of four
pMOSs. Since the gates of M3 and M4 are cross-coupled
connection to the sources of M1 and M2, we obtain a fully
differential type. However, it needs a large chip area and
high power consumption in order to satisfy a middle bit
resolution and wide bandwidth beyond 500MHz. Thus, we
need low power dissipation and small area fully differential
source follower. Fig. 5 shows the circuit diagram of the
proposed fully differential source follower. This is
composed of two pMOS M1 and M2, two nMOS M7 and
M8. The Vx and Vy nodes form a cross-coupled connection Fig. 4. Circuit diagram of conventional differential source follower.
to the sources of M7 and M8. The output impedance of the
super source follower shown in Fig. 2 is determined by the
impedance of M1 to M4. However, the output impedance
 (a)

Fig. 5. Circuit diagram of the proposed wideband fully differential source

follower.

III. EXPERIMENTAL RESULTS

Bode plots based on HSPICE simulations are shown in
Fig. 6 for the super source follower and the proposed
follower. The two source followers had the same conditions
such as MOSFET size, reference currents, load capacitance,
and etc. From Fig. 6 (a), the bandwidth of the proposed (b)
follower is much wider than that of the conventional Fig. 6. (a) Bode plots for the super source follower and the proposed fully
follower, even though the direct current (DC) voltage gain differential source follower and (b) FFT verification results for THA from H-
is lower. Therefore, the frequency characteristics of the SPICE.
proposed source follower show better performance than the
conventional follower. FFT simulation results for THA
with the conventional and proposed source followers are
shown in Fig. 6 (b). The 1024-point FFT simulated SNDR
result for the super source follower is about 58.13 dB at a
500 MHz sampling frequency. The result for the proposed
source follower is about 65.51 dB. Thus, the SNDR was
improved by 7.38 dB with the proposed fully differential
source follower. The SFDR characteristic of the super
source follower was about 58.21 dBc at a 500 MHz
sampling frequency. The SFDR of the proposed source
follower was about 66.92 dBc. Thus, for the same
experimental conditions, the proposed source follower had
a better performance.
An 8-bit cascaded folding-interpolation ADC[18] is
fabricated with a 0.13um Samsung 1-poly 6-metal CMOS
technology to verify the performance of the proposed Fig. 7. Die photo of the prototype 8-bit ADC with proposed source fully
source follower. Fig.7 shows the die photo of the ADC. It is differential source follower.
composed of a THA at the left top side, an analog block, a
digital block, and etc. Fig. 8 shows the measured results of
IV. CONCLUSIONS
the prototype ADC. Fig. 8(a) shows the integral
nonlinearity (INL) and differential nonlinearity (DNL) at We presented a fully differential source follower. The
500MS/s. The measured INL and DNL are +0.8/-0.5LSB results of the conventional and the proposed source
and +0.4/-0.3LSB, respectively. The measured SNDR is followers are summarized in Table 1. Since the output
over 46 dB and the SFDR is 61.8 dBc at 145MHz input impedance of the proposed source follower was smaller
frequency. As a result, the performance of the prototype than that of the conventional follower, the bandwidth was
ADC is better than the same ADC with the conventional improved by about 50%. However, DC voltage gain was
source follower[19]. A typical output FFT spectrum is decreased by about 9%. The SNDR and SFDR of the
shown in Fig. 8 (b). proposed follower were improved by 11.3% and 11.5%,
respectively, compared to those of the conventional
follower. In order to verify the performance, a prototype 8-
bit folding-interpolation ADC was fabricated.
 [6] Y. Kong et al., “An Ultra Low Output Resistance and Wide Swing
Voltage Follower,” in Proc. IEEE ICCCAS, Jul. 2007, pp. 1007-
1010.
[7] H. Barthelemy and E. Kussener, “High Speed Voltage Follower for
Standard BiCMOS Technology,” IEEE Trans. Circuits Syst. II, vol.
48, no. 7, pp. 727-732, Jul. 2001.
[8] K. Hadidi et al., “A Novel Highly Linear CMOS Buffer,” in Proc.
IEEE ICECS, vol 3, Sep. 1998, pp.369-371.
[9] R. G. Carvajal et al., “The Flipped Voltage Follower: A Useful Cell
for Low-Voltage Low-Power Circuit Design,” IEEE Trans. Circuits
Syst. I, vol. 52, no. 7, pp. 1276-1291, Jul. 2005.
[10] P. R. Gray, P. J. Hurst, S. H. levis and R. G. Meyer, “Analysis and
Design of Analog Integrated Circuits,” NewYork : John
Willey&Sons.
[11] B.-W. Chen et al., “A 6-bit, 1.2-GS/s ADC with Wideband THA in
(a) 0.13-um CMOS,” in Proc. IEEE A-SSCC, Nov. 2008, pp. 381-384.
[12] H. Rapakko and J. Kostamovaara, “On the Performance and Use of
an Improved Source-Follower Buffer,” IEEE Trans. Circuits Syst. I,
vol. 54, no. 3, pp. 504-517, Mar. 2007.
[13] K. Hadidi and A. Khoei, “A Highly Linear Cascode-Driver CMOS
Source-Follower Buffer,” in Proc. IEEE ICECS, vol. 2, Oct. 1996,
pp. 1243-1246.
[14] C. Fiocchi and U. Gatti, “A Very Flexible BiCMOS Low-Voltage
High-Performance Source Follower,” in Proc. IEEE ISCAS, vol. 2,
Jul. 1999, pp. 212-215.
[15] M. Koutani et al., “A Highly Linear CMOS Buffer Circuit with an
Adjustable Output Impedance,” in Proc. IEEE CICC, Sep. 2003, pp.
(b) 685-688.
Fig. 8. Prototype ADC measured results, (a) Nonlinearity (INL & DNL), and [16] Anthony R. Bonaccio, “Differential Source Follower with Body
Effect Compensation,” U.S. Patent 5,874,840, Feb. 23, 1999.
(b) 16K-point FFT spectrum at 500MS/s for 145MHz input frequency.
[17] V. V. Ivanov and I. M. Filanovsky, “Operational Amplifier Speed
and Accuracy Improvement,” Boston, MA:Kluwer, 2004
[18] Robert C. Taft, et al., "A 1.8-V 1.6-GSample/s 8-b Self-Calibrating
TABLE I. Performance Summary of the Proposed ADC folding ADC With 7.26 ENOB at Nyquist Frequency," IEEE J.
Solid-State Circuits, vol. 39, no. 12, pp. 2107-2115, Dec. 2004.
Resolution 8-bit [19] Dongjin Lee et al., "Design of a 1.8V 8-bit 500MSPS Folding-
Interpolation CMOS A/D Converter with a Folder Averaging
Sampling Freq. 500MHz Technique," in Proc. IEEE ECCTD, pp. 356-359, Aug. 2007
Power Supply 1.2V (Analog & Digital)
Input Range Diff. 0.6Vpp
INL / DNL ±0.8LSB / ±0.4LSB
SNDR 46.04dB
Power diss. 200mW
Core Area 980um × 870um (0.85mm2 )
Process 0.13um 1 poly 6 metal N-well CMOS

ACKNOWLEDGMENT
This research was supported by a grant-in-aid of Samsung
Thales Co.Ltd., and Agency for Defense Development,
Korea.
REFERENCES
[1] S. M. Louwsma et al., “A 1.35GS/s, 10b, 175mW Time-Interleaved
AD Converter in 0.13um CMOS,” IEEE J. Solid-State Circuits, vol
43, no. 4, pp. 778-786, Apr. 2008.
[2] H.-G. Wei et al., “A Rapid Power-Switchable Track-and-Hold
Amplifier in 90-nm CMOS,” IEEE Trans. Circuits Syst. II, vol. 57,
no. 1, pp. 16-20, Jan. 2010.
[3] X. Fan and P. K. Chan, “Analysis and Design of Low-Distortion
CMOS Source Followers,” IEEE Trans. Circuits Syst. I, vol. 52, no.
8, pp. 1489- 1501, Aug. 2005.
[4] A. Leuciue and Y. Zhang, “A Highly Linear Low-Voltage MOS
Transconductor,” in Proc. IEEE ISCAS, vol. 3, Jul. 2002, pp. 735-
738.
[5] U. Yodprasit and C. C. Enz, “A 1.5-V 75-dB Dynamic Range Third-
Order Gm-C Filter Integrated in a 0.18-um Standard Digital CMOS
Process,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1189-1197,
Jul. 2003.