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CHAPTER ONE

1.1 Historical Background

The invention of transistors in the year 1947 marked a great era in the field of
electronics. This gradually replaced vacuum tubes. Vacuum tubes were bulky, very
unreliable and consumed a lot of power.

The commercial availability of transistors led to the fabrication of several transistors

on a single chip (Integrated Circuit - I.C) in the year 1959.

Moore’s Law

In 1965, Gordon Moore an article “Cramming more components onto integrated

circuit” predicted that component density would double every year.

Moore revisited his prediction in 1975 to say that “component density would double
every 18 months”

Figure 1.1: A graph of Moore’s Prediction

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Microprocessor

A microprocessor incorporates all the functions of central processing unit (CPU) that
has been integrated on a single integrated circuit. Literally, a microprocessor is a
“CPU on a chip”. It is a semiconductor device consisting of electronic logic circuits
manufactured by using a LSI or VLSI technique.

At the heart of all personal computers and most workstations sits a microprocessor.
Microprocessors also control the logic of almost all digital devices, from clock radios
to fuel-injection systems for automobiles.

The key features of a microprocessor are Arithmetic Logic Unit (ALU), Registers and
Control Unit (CU). There is usually an interface provided to link the processor to
memory and I/O devices through a strip of wires called a bus. There are three types
of busses:

1. Address Bus: The address bus is used to identify the memory location or I/O
device the processor intends to communicate with.
2. Data Bus: Data bus is used by the CPU to get data from / to send data to the
memory or the I/O devices. The width of a microprocessor is used to classify
the microprocessor.
3. Control Bus: may be used to indicate when a valid address is on the address
bus, which direction data are to be transferred over the data bus (in/out),
when external devices can read/write data on the data bus and when valid
read/write data are on the data bus.

The ALU is responsible for all the calculations and logic operations that take place in
the processor while the registers serve as temporary memory locations. The timing
and control unit coordinates all the activities in the processor.

The first microprocessor was 4004 and was developed by Intel in 1971 to be used for
a calculator.

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Figure 1.2: A block diagram of a Microprocessor interfaced with memory and I/O
devices

1.2 Evolution of Intel Microprocessors

Since the development of the first microprocessor Intel 4004, Motorola, Texas
Instrument, and a host of other companies joined microprocessor manufacturing
race.

Table 1.1: Generation of Intel microprocessors

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Some important terminologies

Bits

All the information entering or leaving a microprocessor is in the form of a binary

signal, a voltage switching between the two bit levels 0 and 1.

Nibble

A group of four bits handled as a single lump. Examples are 1110, 0010, and 1001

Byte

A byte is simply a collection of 8 bits. Whether they are ones or zeros. Examples are
00000000, 10000101, and 11111111

Word

A number of bits can be collected together to form a ‘word’. Unlike a byte, a word
does not have a fixed number of bits in it. The length of the word or the number of
bits in the word depends on the microprocessor being used. If the microprocessor
accepts binary data in groups of 32 at a time then the word in this context would
include 32 bits. If a different microprocessor uses data in smaller handfuls, say 16 at
a time, then the word would have a value of 16 bits. The most likely values are 8, 16,
32 and 64 bits but no value is excluded.

Long word

In some microprocessors where a word is taken to mean say 16 bits, a long word
would mean a group of twice the normal length, in this case 32 bits.

Kilobyte (Kb or KB or kbyte)

A kilobyte is 1024 or 210 bytes.

Megabyte (MB or Mb)

This is 220 or 1 048 576 bytes.

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Gigabyte (Gb)

This is 1024 megabytes which is 230 or 1 073 741 824 bytes.

Terabyte (TB or Tb)

Terabyte is 240 or 1 099 511 600 000 bytes.

Instruction set: The set of instructions that the microprocessor can execute.

Bandwidth: The number of bits processed in a single instruction.

Clock speed: Given in megahertz (MHz), the clock speed determines how many
instructions per second the processor can execute.

1.3 Classification of Microprocessors

There are various ways by which microprocessors may be classified. The commonly
used classification schemes are by: semiconductor technology of their design, the
width of the data format they can process, and their instruction set.

Classification by semiconductor technology used in design

The technologies used may be transistor-transistor logic (TTL) which is widely used;
complementary-metal-oxide semiconductor (CMOS) which is a choice for portable
computers and other battery-powered devices because of its low power
consumption; and emitter-coupled logic (ECL) which is used in situations where the
need for its greater speed offsets the fact that it consumes the most power.

Classification by width of data format

This is based on the width of data a particular processor can process. The commonly
used formats are 4-bit, 8-bit, 16-bit, 32-bit, or 64-bit. Four-bit processors are
inexpensive and are only good for simple control applications. The wider the data
format, the faster the device.

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Classification based on instruction set

Microprocessors could be classified as complex-instruction-set computer (CISC) or

reduced-instruction-set computer (RISC).

Examples of CISC processors: Motorola 68000 family, and AMD and Intel x86 CPUs.

Examples of RISC processors: ARM, AVR, MIPS, PA-RISC, PIC, Power Architecture, and
SPARC.

CISC Characteristics

The CISC architecture is characterized by its complex micro-coded instructions which

take many clock cycles to execute. The architecture often has a large and variable
code size and offers many powerful instructions and addressing modes. In
comparison to RISC, CISC takes longer to execute its instructions, but the instruction
set is more powerful.

1. Can handle large number of instructions – typically from 100 to 250

instructions.
2. It has some instructions that perform specialized tasks.
3. It has large variety of addressing modes – typically 5 to 20 different modes.
4. It can handle variable-length instruction formats
5. There are instructions that manipulate operands in memory.

RISC Characteristics

The RISC architecture has simple, hard-wired instructions which often take only one
or a few clock cycles to execute. RISC machines feature a small and fixed code size
with comparatively few instructions and few addressing modes. As a result,
execution of instructions is very fast, but the instruction set is rather simple.

1. It can handle relatively few instructions.

2. It has relatively few addressing modes.
3. Memory access is limited to load and store instructions.

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4. All operations are done within the registers of the CPU.

5. It has fixed-length and easily-decoded instruction format.
6. It has single cycle instruction execution.

Micro-coded and hard-coded processors

A computer is a complex sequential digital circuit with both combinational and

sequential circuit components.

In a micro-coded processor, each instruction is realized by a number of steps that are

implemented using small subroutines. These subroutines are called micro-codes
stored within the instruction decode unit. Hence, a micro-coded processor can be
called a processor within a processor.

In a hard coded processor, each instruction is realized by combinational and/or

sequential digital circuits. The design is complex and hard to debug. However, the
program execution is faster.

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CHAPTER TWO

2.1 Organization of the Intel 8086 Microprocessors

Some Features of the 8086 Processor

 It is a 16-bit microprocessor
 It has a 20-bit address bus and therefore can access up to 1,048,576 memory
locations (220 bytes).
 Address ranges from 00000H to FFFFFH
 Its word size is 16 bits and double word size is 4 bytes.
 It is a 40 pin dual in line package
 It has a multiplexed address and data bus AD0 – AD15 and A16 – A19
 It is designed to operate in two modes, Minimum and Maximum
 It fetches up to 6 instruction bytes from memory and queues them in order
to speed up instruction execution (pipelining).

Pin diagram of 8086 Microprocessor

Figure 2.1 8086 µP Pin diagram

Description of some of the Intel 8086 Pins

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AD15±AD0 - ADDRESS DATA BUS: These lines constitute the time multiplexed
memory/IO address and data bus.
ALE - Address Latch Enable. A HIGH on this line causes the lower order 16-bit address
bus to be latched that stores the addresses and then, the lower order 16bit of the
address bus can be used as data bus.
READY: READY is the acknowledgement from the addressed memory or I/O device
that it will complete the data transfer.

INTR -INTERRUPT REQUEST: is a level triggered input which is sampled during the
last clock cycle of each instruction to determine if the processor should enter into an
interrupt acknowledge operation. A subroutine is vectored to via an interrupt vector
lookup table located in system memory. It can be internally masked by software
resetting the interrupt enable bit. INTR is internally synchronized. This signal is active
HIGH.
INTA -Interrupt Acknowledge from the MP
NMI -NON-MASKABLE INTERRUPT: an edge triggered input which causes an interrupt
request to the MP. A subroutine is vectored to via an interrupt vector lookup table
located in system memory. NMI is not maskable internally by software.
RESET: causes the processor to immediately terminate its present activity. The signal
must be active HIGH for at least four clock cycles. It restarts execution
MN/MX: MINIMUM/MAXIMUM: indicates what mode the processor is to operate in.
The two modes are discussed in the following sections.
M/IO: Differentiates between the Memory and I/O operation. A LOW on this pin
indicated I/O operation and a HIGH indicated a Memory Operation
HOLD: The 8086 has a pin called HOLD. This pin is used by external devices to gain
control of the busses.
HLDA: When the HOLD signal is activated by an external device, the 8086 stops
executing instructions and stops using the busses. This would allow external devices
to control the information on the 8086 MINIMUM AND MAXIMUM MODES of
operation

MN/MX

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 Minimum mode
The 8086 processor works in a single processor environment known as Minimum
mode. All control signals for memory and I/O are generated by the microprocessor.
 Maximum mode
This mode is desirable when a coprocessor exists in the system, that is,
multiprocessor environment. Control signals for memory and I/O are generated by
an external BUS Controller.

Figure 2.2: Internal organization of Intel 8086 Microprocessor

The Intel 8086 and 8088 microprocessors are the basis of most modern
microprocessors. The 8086 processor consists of two internal units: the Bus Interface
Unit (BIU) and the Execution Unit (EU).

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Bus Interface Unit – BIU

The BIU generates the 20-bit physical memory address and facilitates
communication between the EU and the memory or Input/output circuits. To speed
up execution, 6-bytes of instruction are fetched in advance and kept in a 6-byte
Queue while other instructions are being executed in the EU. Therefore after
execution, the next instruction is directly fetched from the instruction queue in First-
In-First-Out (FIFO) without having to wait for the external memory to send the
instructions. When there is a jump instruction, the microprocessor must flush out
the queue. When a jump instruction is executed BIU again fetches information from
the new location in the memory. In this situation EU must wait until the BIU starts to
fetch the new instruction. This is known as branch penalty.

This unit is responsible for performing all external bus operations.

1. It gives address of memory or I/O.

2. It fetches “opcode” from memory.

3. It read data from memory or I/O port.

4. It writes data into memory or I/O port.

5. It supports instruction queuing.

Execution Unit – EU

The execution unit contains the arithmetic and logic unit (ALU) that performs
arithmetic and logical operations. The EU has eight registers – AX, BX, CX, DX, SP, BP,
SI, and DI for storing data during program execution. A decoder in the EU translates
instructions fetched from memory into a series of actions to be carried out by the
EU. There is also a 16-bit flag register of which nine are active. During execution, the
EU may test the status and control flags and update these flags based on results of
execution.

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In general EU is responsible for

1. Informing B.I.U (bus interface unit) from where to fetch instruction of data
and where to store the data.
2. Decodes the op-codes which is fetched from queue register and then execute
that instruction.

2.2 Registers
Registers are located inside the CPU therefore they are much faster than memory.
Registers are a collection of flip-flops. Accessing a memory location requires the use
of a system bus which takes much longer than accessing data in a register.

General Purpose Registers

The general purpose registers are AX, BX, CX, and DX. These four are made of two
separate 8-bit registers, for example if AX= 0011000000111001B, then
AH=00110000B and AL=00111001B. The most significant byte is represented by “H”
and the least significant byte is represented by “L”. The same applies to all the other
3 registers.

Figure 2.3: General purpose registers

AX - Accumulator Register is favoured by the CPU for arithmetic operations such as

division and multiplication.

BX - Base Register usually contains a data pointer used for based, based indexed or
register indirect addressing.

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CX - Count Register acts as a counter for repeating or looping instructions. CL is used

to hold the count value while executing the shift/rotate instruction. The count value
indicates the number of times the same code has to be executed when the loop
instruction is used.

DX - Data Register is used to hold a part of result during a multiplication operation

and a part of dividend before division operation. It is also used to hold the I/O device
address while executing an I/O instruction.

Pointers and Index Registers

SP – Stack Pointer is used to hold the offset address of the data stored at the top of
the stack segment. SP is used along with the SS register to decide the address at
which data is to be pushed or popped during the PUSH and POP instructions.

A stack is a section of memory set aside to store addresses and data while
subprogram executes. The Stack Segment Register is used to hold the upper 16 bits
of the starting address for the program stack. Items are added and removed from
one end of the structure that is it is processed in Last in First out (LIFO) manner. The
most recent addition to the stack is called the top of the stack. Stack is used by CALL
instruction to keep return address for procedure, RET instruction gets value from the
stack and returns the offset. RET instruction can also be used to return to the
operating system.
PUSH stores 16 bit value in the stack and POP gets 16 bit value from the stack.

BP – Base Pointer is used to hold the offset address of the data to be read from or
written into the stack

SI – Source Index is used to hold the offset address of the source data segment while
executing string instructions.

DI – Destination Index is used to hold the offset address of the destination data in
extra segment, while executing the string instructions.

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IP – Instruction Pointer is a 16-bit register that points to the next instruction to be

executed within the current code segment.

Segment Registers

The four segment registers in 8086 processor are Code Segment (CS), Data Segment
(DS), Stack Segment (SS), and Extra Segment (ES). These are generally used to hold
the upper 16 bits of the starting address of four memory segments that the 8086 is
working with at a particular time.

1. CS Register: This register contains the initial address of the code segment.
This address plus the offset value contained in the instruction pointer (IP)
indicates the address of an instruction to be fetched for execution.
2. SS Register: The stack segment register contains the initial address of the
stack segment. The address plus the value contained in the stack pointer (SP)
is used for stack operations.
3. DS Register: The data segment register contains the initial address of the
current data segment. This address together with the offset value in
instruction causes a reference to specific location in the data segment. By
default, the processor assumes that all data referenced by the general
registers (AX, BX, CX, DX) and index registers (SI, DI) are located in the data
segment.
4. ES Register: Extra segment is used by some string operations. The extra
segment register contains the initial address of the extra segment string
instructions always use the ES and DI registers to calculate the physical
address for the destination. The processor also assumes by default, that the
DI register references the ES segment in string manipulation instructions.

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There are special combinations of segment registers and general registers that point
to important addresses:

 CS: IP - points to the address where the processor will fetch the next byte of
code.
 SS:SP – points to the address top of the stack ( the most recently pushed
byte)
 DS: SI – is often used to point to string data that is about to be copied to
ES:DI.
 ES: DI – is typically used to point to the destination for a string copy.

The table below however offers other possible combinations of segment and offset
registers.

Segment Register CS DS ES SS
Offset register(s) IP SI,DI,BX SI, DI, BX SP, BP
Table 2.1: Segment and offset registers combination

Flag Register

A flag is a flip-flop that indicates some condition produced by the execution of an

instruction or controls certain operations of the Execution Unit (EU). It is a 16-bit
register of which 7 are unused. The flag register can be divided into two: (a)
Conditional or Status Flags and (b) Control Flags.

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Figure 2.3: Flag register

Conditional or Status Flags

These flags are set or reset by the EU on the basis of the results of some arithmetic
operations. The six conditional flags are Carry Flag (CF), Parity Flag (PF), Auxiliary Flag
(AF), Zero Flag (ZF), Sign Flag (SF), and the Overflow Flag (OF).

Carry Flag

The carry flag will be set to 1 if the addition of two 16-bit binary numbers produces a
carry out of the MSB position. If no carryout of MSB is produced by the addition,
then the carry flag will be zero.

Example: Consider the binary addition below.

1000011101001110

1001100100001001

0010000001010111

A carry is generated at the Most Significant Bit (MSB) so the carry flag will set, that is
CF=1.

Parity Flag

PF=1 if the low byte of a result has an even number of 1’s (Even parity)

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Example: Consider the binary addition below.

1000011101001110

1001100100001001

0010000001110111

The lower 8 bits of the result (01110111) has 6 1’s (Even parity) as such PF = 1.

Auxiliary Carry Flag

It is set (AF=1) if a carry is transferred from lower nibble to higher nibble or if a

subtraction of the least significant nibble requires a borrow.

Example: Consider the binary addition below.

1000011101001110

1001100100001001

0010000001110111

A carry is generated at bit position 3 so AF will set (AF = 1).

Zero Flag

ZF = 1 if the total result of an arithmetic operation or logical operation is zero.

Example: Consider the binary addition below.

1000000000000000

1000000000000000

0000000000000000

The total output is zero, therefore ZF=1.

Sign Flag

After the execution of arithmetic or logical operation, if the most significant bit
(MSB) result is 1, then the sign flag will be set otherwise it will be reset.

If the value of MSB is 1, then it indicates a negative number. If the value of MSB is 0,
it means the number is positive.

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For a negative number, the magnitude will be in 2’s complement form.

Control Flags

The control flags are Trap Flag (TF), Interrupt Flag (IF) and Direction Flag (DF). These
flags are used to enable or disable certain operations of the processor.

Trap Flag

It is used to debug a program using a single step technique. If it is set, the

microprocessor gets interrupted after the execution of each instruction in the
program. If TF is reset, the trapping or debugging feature is disabled.

Interrupt Flag

If the Interrupt Flag is zero (IF = 0) then INTR pin is disabled. If the Interrupt Flag, IF
=1, then INTR pin is enabled.

Direction Flag

If DF is set, then string manipulation instructions will auto-decrement index registers.

If it is cleared, then the index registers will be auto-incremented.

2.3 Memory Segmentation

The total physical memory in an 8086 based system is divided into a number of
logical segments in a process known as segmentation. A segment is just an area in
memory. Each segment is 64K bytes in size and is addressed by one of the four
segment registers. The 16-bit contents of the segment register point to the starting
location of a particular segment. To address a specific memory location within a
segment, an offset address is needed. The offset address is equally 16-bit long as
such the maximum offset value can be FFFF H. The complete I MB memory can be
divided into 16 segments.
Therefore the 8086 processor can support 1Mbyte of external memory that has
been organized as individual bytes of data stored at consecutive addresses over the

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address range 0000016 to FFFFF16. The 8086 can access any two consecutive bytes as
a word of data. The lower-addressed byte is the least significant byte of the word,
and the higher- addressed byte is its most significant byte. The starting and end
address of each segment is given in the table 2.1 below:
Segment Starting address End Address
1st Segment 00000 H 0FFFF H
2nd Segment 10000 H 1FFFF H
3rd Segment 20000 H 2FFFF H
4th Segment 30000 H 3FFFF H
---------- -------- ---------
---------- -------- ---------
16th Segment F0000 H FFFFF H
Table 2.1: Starting and ending address of segments.

Memory segments can overlap or two or more segments could even coincide. This is
indicated in the figure 2.4 below:

Figure 2.4: Memory segmentation

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2.4 Generating Memory Address

A physical memory address may be represented logically as shown below:
Logical Address: segment: Offset

Example 1
CS:IP
438B:2467

To derive the 20-bit Physical Address of memory from a given logical address,
1. Multiply Segment register by 10H ( or shift it to left by four bit)
2. Add it to the offset
Example 2
If CS = 002AH, and IP = 0023H, write the logical address that they represent, then
map it to Physical address.

Solution: Logical address = CS:IP

002A : 0023

Physical address = ( CS X 10H ) + IP = 002A0 +0023 = 002C3

Example 3
Ex: If CS=24F6H and IP=634AH, determine:
a) The logical address
b) The offset address
c) The physical address
d) The lower range of the code segment
e) The upper range of the code segment

Solution
a) The logical address is; 24F6:634A
b) The offset address is; 634A
c) The Physical address is; 24F60+634A= 2B2AA

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d) The lower range of the code segment: 24F6:0000 => 24F60+0000 =24F60
e) The upper range of the code segment: 24F6:FFFF => 24F60+FFFF=34F5F

Exercise
With reference to the contents of the following registers:
CS = 1111 H, DS = 3333 H, SS = 2526 H, IP = 1232 H, SP = 1100 H, DI = 0020 H

Calculate the corresponding physical addresses (effective addresses) for the address
bytes in CS, DS and SS. In each case, state the corresponding logical address.

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CHAPTER THREE

3.1 Microprocessor Programming

Programming language
Programming language is a set of rules that tells the computer what operations to
perform. This set of rules may differ from microprocessor to microprocessor or may
be interpreted differently by different microprocessors.

A computer program: it is a list of instructions that the processor must follow in

order to process data into information.

Processor (computer) Instruction

Instruction can be divided into two parts namely: operation code (opcode) and
operands.
Operation Code (Opcode): This part instructs a computer about the operation to be
performed.
Operand: This part instructs the computer about the location of the data on which
the operation specified by opcode is to be performed.

Machine language – first generation language

This is the basic language of the computer or processor and data and instructions are
represented as 1’s and 0’s. Machine language is processor dependent.

Assembly Language – second generation language

Assembly language is a low-level programming language that allows a programmer
to write instructions to be executed by the processor using alphanumeric symbols
instead of 0’s and 1’s. A translation program is needed to convert assembly language
code into machine language code. This translation program is called an assembler.

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High-level language – third generation language

High level language resembles human language such as English and therefore it is
much easier to program as compared with machine and assembly languages.
Depending on the particular language being used, a translator such as an interpreter
or a compiler may be used to convert the code to machine code. In most cases high-
level languages such as C or C++ are used to program microprocessors.

3.2 Micro-operations
A micro-operation is an elementary operation performed on the information stored
in one or more registers. The result of the operation may replace the previous binary
information of a register or may be transferred to another register.
There are four main types of micro-operations and these are:
 Arithmetic Micro-operations: these involve operations such as addition,
subtraction, increment, decrement, add with carry, subtract with borrow,
and so on.

Figure 3.1: Summary of arithmetic operations

 Logic Micro-operations: these can be used to manipulate individual bits or

portions of a word in a register. The commonly used logical operations are
AND, OR, XOR, and Complement/NOT.

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Figure 3.2: Summary of logical operations

 Shift Micro-operations: these involve logical shift (right shift/ left shift),
circular shift (right circular shift/left circular shift), and arithmetic shift
operations (right arithmetic shift/left arithmetic shift).
 Register transfer micro-operations: The data transfer instructions are used to
move data between internal registers or between internal register and the
memory. The content of the source remains the same after the execution of
data transfer instructions. Flags are not affected by any of the instruction in
the group.

3.3 Addressing modes

The different modes used to access data are called addressing modes. The 8086
addressing modes are categorized into three types: Register addressing mode,
immediate addressing mode, and Memory addressing mode.

3.3.1 Register addressing mode:

With register addressing mode, the operand to be accessed is specified as residing in
an internal register. Since memory is not accessed, it is faster.
Source and destination registers must match in size.
Example:
MOV AX, BX ; copies the content of register BX into register AX
MOV BX, DX

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MOV ES, AX
ADD AL, BH
MOV AL, CX ; not possible due varying register sizes.

3.3.2 Immediate addressing mode:

Source operand is a constant
Immediate addressing is possible in all registers except segment and flag registers.
Example:
MOV BX, 1234H ; move 1234H into BX
MOV CX, 625 ; load the decimal value 625 into CX
ADD AL, 40H ; AL=AL+33H
MOV DS, 1234H ; illegal (data cannot be transferred directly into a segment
register)

3.3.3 Memory addressing mode

Memory addressing mode defines how a microprocessor references an operand in

memory. The 8086 must calculate the physical address of the operand and then
initiate a read or write operation of this storage location. This mode includes:
 Direct addressing: The address of the data in memory comes immediately
after the instruction operand is a constant. The address is the offset address
and this is put in a rectangular bracket.
Example:
MOV DL,[2400] ; move contents of DS:2400H into DL

Exercise: Find the physical address of the memory location and its content
after the execution of the following operation. Assume DS=1512H
MOV AL, 99H
MOV [3518], AL
Physical address of DS: 3518 => 15120+3518=18638H
The memory location 18638H will contain the value 99H
 Register indirect addressing: this mode is similar to the direct addressing but
the offset is specified in a base register (BX), base pointer (BP) or an index
register (SI or DI) within the 8086. The offset is usually combined with DS to
generate the 20-bit physical address.

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Examples:
MOV AL, [BX] ; moves into AL the contents of the memory location
pointed to by DS:BX
MOV CL, [SI] ; move contents of DS:SI into CL
MOV [DI], AH ; move the contents of AH into DS:DI
 Based addressing: In this mode, the effective address is obtained by adding a
direct or indirect displacement to the contents of either the base register BX
or Base pointer BP. The default segments used for the calculation of physical
address are DS for BX, or SS for BP
Examples:
MOV CX, [BX]+10 ; move DS:BX+10 and DS:BX+11 into CX
; PA = DS (shifted left) +BX+10
• Note that, the content of the low address will go into CL and the
high address contents will go into CH.
• There are alternative coding: MOV CX,[BX+10], MOV CX,10[BX]
• BX+10 is effective address
MOV AL,[BP]+5 ; PA = SS (shifted left) +BP+5
 Indexed addressing: this mode work in similar manner to that of the based
addressing mode but the effective address is obtained by adding the
displacement to the value in an index register (SI or DI). SI and DI hold the
offset address.

Examples:
MOV DX, [SI]+5 ;PA=DS(shifted left)+SI+5
MOV CL, [DI]+20 ;PA=DS(shifted left)+DI+20
MOV AL, [SI]+1234H

 Based-Indexed addressing: this mode combines the based addressing mode

and indexed addressing mode. One base register and one index register are
used.
Examples:

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MOV CL, [BX][DI]+8 ;PA=DS(shifted left)+BX+DI+8

MOV CH, [BX][SI]+20 ;PA=DS(shifted left)+BX+SI+20
MOV AH, [BP][DI]+12 ;PA=SS(shifted left)+BP+DI+12
MOV AL, [BP][SI]+29 ;PA=SS(shifted left)+BP+SI+29

Alternative coding:
MOV CL,[BX+DI+8]
MOV CL,[DI+BX+8]

3.4 Microprocessor Instruction Set

The operations of a microprocessor correspond to its instructions. These instructions
can be classified as Data transfer instructions, Arithmetic instructions, Bit
manipulation instructions, String instructions, Program execution transfer
instructions, and Processor control instruction.

3.5 Data transfer instructions

GENERAL PURPOSE
MOV Copies a byte or word from a source to a destination
PUSH Copies a word onto stack
POP Copies a word from the stack to the specified location
PUSHA Pushes registers onto stack
POPA Copies registers off stack
XCHG Exchanges byte or word
XLAT Transforms a byte in AL using a table in the memory
INPUT/OUTPUT
IN Copies a byte or word from the specified I/O port to the accumulator
OUT Copies a byte or word from the accumulator to the specified I/O port
ADDDRESS OBJECT AND STACK FRAME
LEA Loads effective address of an operation in the specified register
LDS Loads register DS and other specified registers from the memory
LES Loads register ES and other specified registers from the memory

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ENTER Build stack frame

LEAVE Tear down stack frame
FLAG TRANSFER
LAHF Loads AH with the least significant byte of the flags register
SAHF Stores AH register in the least significant byte of the flags register
PUSHF Copies the flags register onto the stack
POPF Copies a word from the stack to the flags register

Arithmetic instructions
ADDITION
ADD Sums the specified byte/word to a byte/word
ADC Sums considering also the value of the carry flag
INC Increments the specified byte or word by 1
AAA Adjusting ASCII after addition
DAA Adjusting decimal after an addition
SUBTRACTION
SUB Subtracts the specified byte or word
SBB Subtracts considering also the value of the carry flag
DEC Decrements the specified byte or word by 1
NEG Calculates the complement to 2 (Negate byte or word)
CMP Compare two bytes or words
ASS Adjusting ASCII after subtraction
DAS Adjusting decimal after subtraction
MULTIPLICATION
MUL Multiplies bytes or words without sign
IMUL Multiplies bytes or words with sign
AAM Adjusting ASCII after the multiplication
DIV Divides a word without sign by a byte, or double word without sign by a
word
IDIV Divides a word with sign by a byte, or double word with sign by a word
AAD Adjusting ASCII before the division
CBW Convert byte to word

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CWD Convert word to double word

Bit manipulation
LOGICALS
NOT Inverts each bit of a byte or word
AND AND byte or word
OR ‘Inclusive or’ byte or word
XOR ‘Exclusive or’ byte or word
TEST Follows the same operations of an AND, but doesn’t change the value of the
operands
SHIFTS
SHL/ Shifts logical/arithmetic to the left the bit of a word or of a byte
SAL
SHR Shifts to the right the bit of a word or of a byte
SAR Shifts arithmetic right the bit of a word or of a byte
ROTATES
ROL Rotates to the left the bit of a word or of a byte, puts MSB in LSF and CF
ROR Rotates to the right the bit of a word or of a byte, LSB in MSB and CF
RCL Rotates to the left the bit of a word or of a byte, MSB in CF and CF in LSB
RCR Rotates to the right the bit of a word or of a byte, LSB in CF and CF in MSB

String instructions
A string is a series of bytes or words in sequential locations of the memory. It is
normally formed from ASCII characters.

REP Instruction prefix. Repeat the following instruction until CX=0

REPE/REPZ Instruction prefix. Repeat the instruction until CX=0 or ZF≠0
REPNE/REPNZ Instruction prefix. Repeat the instruction until CX=0 or ZF=0
MOVSB/MOVSW/MOVS Move byte or word from a string to another
COMPS/COMPSB/COMPSW Compares two byte strings or two word strings
INS/INSB/INSW Input byte or word from a port

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OUTS/OUTSB/OUTSW Output byte or word from a port

SCAS/SCASB/SCASW Scanning of a string. Compares a string of byte with a byte in
AL, or a string of words with a word in AX
LODS/LODSB/LODSW Loads a byte or word string in AL to a word of string in AX
STOS/STOSB/STOSW Stores a byte from AL or a word from AX in a string

Program execution transfer instructions

CALL Calls a subprogram, saves the return address on the stack
RET Returns from a subprogram to the calling program
JMP Jumps all specified address to follow the next instruction
JA/JNBE Jumps if above/ jumps if not below or equal
JAE/JNB Jumps if above or equal/ jumps if not under
JBE/JNA Jumps is below or equal/ jumps if not below
JC Jumps if Carry Flag CF=1
JE/JZ Jumps if equal/ jumps if Zero Flag ZF= 1
JG/JNLE Jumps if more than/ jumps if not less or equal
JGE/JNL Jumps if more than or equal /jumps if not less
JL/JNGE Jumps if less/ jumps if not more than or equal
JLE/JNG Jumps if less or equal /jumps if not more than
JNC Jumps if no Carry (CF=0)
JNE/JNZ Jumps if not equal /jumps if not zero (ZF≠1)
JNO Jumps if no overflow, OF=0
JO Jumps if overflow, OF=1
JP/JPE Jumps if parity/ jumps if parity is even (PF=1)
JS Jumps if sign (SF=1)
ITERATION CONTROL
LOOP Follows a sequence of instructions until CX=0
LOOPE/LOOPZ Follows a sequence of instructions while ZF=1, CX≠0
LOOPNE/LOOPNZ Follows a sequence of instructions while ZF=0, CX≠0
JCXZ Jumps to the specified address if CX=0
INTERRUPTS

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INT Interrupts the execution of the program and calls a service

procedure
INTO Interrupts the execution of the program if OF =1
IRET Returns from an interruption service

Processor control instructions

FLAG OPERATIONS
STC Set carry flag
CLC Clear carry flag
CMC Complements the state of the carry flag
STD Sets the direction flag DF=1
CLD Resets the direction flag DF=0
STI Sets the enabling flag of the interrupts at 1
CLI Resets the enabling flag of the interrupts
EXTERNAL SYNCHRONIZATION
HLT Stops the processor until the arrival of an interrupt
WAIT Waits until the signal on pin TEST becomes low
ESC Escapes from the external coprocessor (8087 or 8089)
LOCK Instruction prefix. Blocks eventual external processors
NO OPERATION
NOP No operation

3.6 Instruction Format

An instruction format defines the layout of the bits of an instruction, in terms of its
constituent parts .The assembly instruction format includes: Label which defines the
program line, Opcode or mnemonic which describes the required operation,
Operand which defines the data to be operated upon, and Comment. The label and
comment may be omitted during programming.

A line of instruction may be written as follows:

Label: Opcode Operand1, Operand2 ;Comment

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MOV Instruction
MOV destination, source ; copy source operand to destination
Types of instruction format
Instructions come as three address instructions, two address instructions, one
address instructions or zero address instructions.
 Three address instructions: Computers that use this type of instruction
format use three address fields to specify either a processor register or a
memory operand.
For example: ADD R1, A, B ; R1 M[A] + M[B]

It is clear from the example that 3 addresses are specified: one register
address, and two memory addresses. Example of computer using this type of
instruction is Cyber 170.
 Two address instructions: two addresses are specified in this type of
instruction format.
Example: ADD R1, A ; R1 M[A] + M[B]
It can be observed that one register as well as one memory operand are
specified. Register R1 is both the source and the destination. Most
commercial computers use this type of instruction.
 One address instructions: one register, usually the Accumulator register is
used for all data manipulation.
Example: ADD B ; AC C + M[B]
All operations are done between the Accumulator and a memory operand.
Commercially available computers also use this type of instruction format.
 Zero address instructions: a stack organized computer does not require an
address field for computational instructions. Due to the absence of the
address field it is known as zero address instructions.
Example: PUSH A ; STACK A
PUSH B ; STACK B
ADD ; STACK (A+B)

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Mnemonic operands
Example: (8-bit)
MOV CL,55H ;move 55H into register CL
MOV DL,CL ;move/copy the contents of CL into DL (now DL=CL=55H)
MOV BH,DL ;move/copy the contents of DL into BH (now DL=BH=55H)
MOV AH,BH ;move/copy the contents of BH into AH (now AH=BH=55H)

Example: (16-bit)
MOV CX,468FH ;move 468FH into CX (now CH =46 , CL=8F)
MOV AX,CX ;move/copy the contents of CX into AX (now AX=CX=468FH)
MOV BX,AX ;now BX=AX=468FH
MOV DX,BX ;now DX=BX=468FH
MOV DI,AX ;now DI=AX=468FH
MOV SI,DI ;now SI=DI=468FH
MOV DS,SI ;now DS=SI=468FH
MOV BP,DS ;now BP=DS=468FH

Basic Rules for MOV instruction

 Data can be moved among all registers except the flag register. There are
other ways to load the flag registers.
 Source and destination registers have to match in size.
 Data can be moved among all registers (except flag reg.) but data can be
moved directly into non-segment registers only. You cannot move data into
the segment registers directly (CS, DS, SS and ES).
Examples:
MOV BX,14AFH ;move 14AFH into BX (legal)
MOV SI,2345H ;move 2345H into SI (legal)
MOV DI,2233H ;move 2233H into DI (legal)
MOV CS,2A3FH ;move 2A3FH into CS (illegal)
MOV DS,CS ;move the content of CS into DS (legal)
MOV FR,BX ;move the content of BX into FR (illegal)

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MOV DS,14AFH ;move 14AFH into DS (illegal)

MOV AX,1234H ; load 1234H into AX
MOV SS,AX ;load the value in AX into SS
MOV BX,2H ; BX=0002H, BL:02H, BH:00H
MOV AL,123H ; illegal (larger than 1 byte)
MOV AX,3AFF21H ; illegal (larger than 2 bytes)

XOR
XOR destination, source
Example: MOV DH,54H
XOR DH,78H
Interpretation: 54H 01010100
78H 01111000
2CH 00101100 SF=0, ZF=0, PF=0, CF=OF=0
SHIFT
SHR destination, source ;shift right

The operand is shifted right bit by bit, and for every shift the LSB will go to the CF and
MSB is filled with a zero.
Example: MOV AL,9AH
MOV CL,3 ;set number of times to shift
SHR AL,CL
Interpretation: 9AH 10011010
01001101 CF=0 (shifted once)
00100110 CF=1 (shifted twice)
00010011 CF=0 (shifted three times)
After three times of shifting AL=13H and CF=0
Note: The destination operand can be in a register or memory. Immediate
addressing mode is not possible. If the destination operand is to be shifted once only
1 can be used instead of CL.

SHL

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The operand is shifted left bit by bit, and for every shift the LSB is filled with a zero
(0) and the MSB goes into CF.
Example: MOV DH,6
MOV CL,4 ;set number of times to shift
SHL DH,CL
Interpretation: 00000110
CF=0 00001100 (shifted left once)
CF=0 00011000
CF=0 00110000
CF=0 01100000 (shifted left 4 times)
Note: The destination operand can be in a register or memory. Immediate
addressing mode is not possible. If the destination operand is to be shifted once only
1 can be used instead of CL.

ROTATE INSTRUCTIONS
• ROR rotate right
Note: LSB is moved to MSB and is copied to CF. CL holds the number of rotations. If
to be rotated once, 1 is used.

Example: MOV AL,36H ;AL=0011 0110

ROR AL,1 ;AL=0001 1011 CF=0
ROR AL,1 ;AL=1000 1101 CF=1
ROR AL,1 ;AL=1100 0110 CF=1
or:
MOV AL,36H ;AL=0011 0110
MSB LSB CF
MOV CL,3 ;CL=3 number of times to rotate
ROR AL,CL ;AL=1100 0110 CF=1
• ROL rotate left
Notice: MSB is moved to LSB and is copied to CF. CL holds the number of rotations. If
to be rotated once, 1 is used.
Example: MOV AL,47H ;AL=0100 0111

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ROL AL,1 ;AL=1000 1110 CF=0

ROL AL,1 ;AL=0001 1101 CF=1
ROL AL,1 ;AL=0011 1010 CF=0
ROL AL,1 ;AL=0111 0100 CF=0
or:
MOV AL,47H ;AL=0100 0111
MOV CL,4 ;CL=4 number of times to rotate
ROR AL,CL ;BH=0111 0100 CF=0

COMPARING UNSIGNED NUMBERS

CMP destination, source ; compare destination and source.

Note: The operands themselves remain unchanged. The destination operand can be
in register or memory. The source operand can be in register, memory or an
immediate number. Only the CF and ZF are affected.

How the flags are set

Compare operands CF ZF
Destination >source 0 0
Destination = source 0 1
Destination < source 1 0

Example: DATA1 DW 235FH

…
MOV AX,CCCCH
CMP AX,DATA1 ;compare CCCC with 235F
JNC OVER ;jump if CF=0
SUB AX,AX
OVER: INC DATA1

SUBTRACTION OF UNSIGNED NUMBERS

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SUB destination, source ; dest = dest - source

Note: In subtraction 2’s complement method is used.

Steps
1. Take the 2’s complement of the subtrahend (source operand)
2. Add it to the minuend (destination operand)
3. Invert the carry

Example: MOV AL,3FH ; load AL=3FH

MOV BH,23H ; load BH=23H
SUB AL,BH ; subtract BH from AL. Place result in AL

Execution steps:
AL 3F 0011 1111 0011 1111
– BH – 23 – 0010 0011 + 1100 0001 (2’s complement)
1C 0001 1100 1 0001 1100

UNSIGNED MULTIPLICATION AND DIVISION

Multiplication of unsigned numbers
byte x byte :
 One of the operands must be in AL. The other operand can be either in a
register or in memory.
 After the multiplication the result is in AX.
Example: RESULT DW ? ; result is defined in data
segment
…..
MOV AL,25H ; a byte is moved to AL
MOV BL,65H ; immediate data must be in a register
MUL BL ; AL= AL x BL = 25 x 65
MOV RESULT,AX ; result is saved
Example:

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; from the data segment:

DATA1 DB 25H
DATA2 DB 65H
RESULT DW ?
; from the code segment:
MOV AL,DATA1
MOV BL,DATA2
MUL BL ;register addressing mode
MOV RESULT,AX
or
MOV AL,DATA1
MUL DATA2 ;direct addressing mode
MOV RESULT,AX
word x word :
 One of the operands must be in AX . The other operand can be either in a
register or in memory.
 After the multiplication the lower word is in AX and the higher word is in DX.

Unsigned Multiplication summary

Multiplication Operand 1 Operand 2 Result
byte x byte AL register or memory AX
word x word AX register or memory DX AX
word x byte AL=byte, AH=0 register or memory DX AX

Division of unsigned numbers

1. Byte / byte
 Numerator must be in AL and AH must be set to zero
 Denominator cannot be immediate but can be in memory or in a register.
 After the division AL will have the quotient and AH will have the remainder

Example: DATA7 DB 95
DATA8 DB 10
QUOT1 DB ?

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REMAIN1 DB ?
; using direct mode
MOV AL,DATA7 ;AL holds numerator
SUB AH,AH ;AH must be cleared
DIV DATA8 ;divide AX by DATA8
MOV QUOT1,AL ;quotient = AL = 09
MOV REMAIN1,AH ;remainder = AH = 05
; using register addressing mode
MOV AL,DATA7 ;AL holds numerator
SUB AH,AH ;AH must be cleared
MOV BH,DATA8 ;move denominator to a register
DIV BH ;divide AX by BH
MOV QUOT1,AL ;quotient = AL = 09
MOV REMAIN1,AH ;remainder = AH = 05
; using the immediate addressing mode will give an error
MOV AL,DATA7
SUB AH,AH
DIV 10 ; immediate mode is not allowed
2. word / word
 Numerator must be in AX and DX must be cleared
 Denominator can be in memory or in a register.
 After the division AX will have the quotient and DX will have the remainder
Example:
MOV AX,10050 ;AX holds numerator
SUB DX,DX ;DX must be cleared
MOV BX,100 ;BX is used for denominator
DIV BX ;divide AX by BX
MOV QUOT2,AX ;quotient = AX = 64H (100 )
MOV REMAIN2,DX ;remainder = DX = 32H (50)

3. word / byte

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 Numerator must be in AX
 Denominator can be in memory or in a register.
 After the division AL will have the quotient and AH will have the remainder
Example:
MOV AX,2055 ;AX holds numerator
MOV CL,100 ;BX is used for denominator
DIV CL ;divide AX by CL
MOV QUO,AL ;AL holds the quotient = AL = 14H (20)
MOV REMI,AH ;AH holds the remainder = AH = 37H (55)

Little endian convention

Given 8-bit (1-byte) data, bytes are stored one after the other in the memory.
However given16-bit (2-bytes) of data how are date stored?

Ex: MOV AX,35F3H ;load 35F3H into AX

MOV [1500],AX ;copy contents of AX to offset 1500H
In such a case the low byte goes to the low memory location and high byte goes to
the high memory location.
DS:1500 = F3 DS:1501 = 35
This convention is called little endian convention: This convention is used by Intel.
The big endian convention is the opposite, where the high byte goes to the low
address and low byte goes to the high address. Motorolla microprocessor uses this
convention.

CHAPTER FOUR

4.1 Memories
Memories are circuits or systems that store digital information temporally or
permanently. Semiconductor memories are mostly fabricated using the VLSI

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technology. Storing data in a memory location is referred to as write operation while

looking up the contents of a memory location is referred to as memory read
operation.

Memory organization

Computer memory device may be viewed as consisting of a number of equally sized

segments or registers that share common set of inputs and a common set of outputs
as shown in figure 4.1 below:

Figure 4.1: Memory organization

If the number of segments is 2n then n-lines will be required to select the segment to
be written into. The address inputs are decoded by the address decoder to select
only one of the memory segments for either reading or writing.

For a memory device with n-bit address a memory device with n-bit address lines
and word size of m-bits, the memory has 2n words (2n x m).

Example: if n=10 and m=8, the memory is a 1024x8 bit memory or 1K bytes.

Memory Hierarchy

The entire memory capacity of a computer can be visualized as being a hierarchy of

components. The memory hierarchy system consists of all storage devices employed

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in a computer system from the slow but high-capacity auxiliary memory to a

relatively faster main memory, to an even smaller and faster cache memory
accessible to the high-speed processing logic. Figure 4.2 illustrates the components
in a typical memory hierarchy. At the bottom of the hierarchy are the relatively slow
magnetic tapes used to store removable files. Next are the magnetic disks used as
backup storage. The main memory occupies a central position by being able to
communicate directly with the CPU and with auxiliary memory devices through an
I/O processor. When programs not residing in main memory are needed by the CPU,
they are brought in from auxiliary memory. Programs not currently needed in main
memory are transferred into auxiliary memory to provide space for currently used
programs and data. The auxiliary memory provides backup storage.

Figure 4.2 Memory hierarchy

Cache Memory

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When a program loop is executed, the CPU repeatedly refers to the set of
instructions in memory that constitute the loop. Every time a given subroutine is
called, its set of instructions are fetched from memory. Thus loops and subroutines
tend to localize the references to memory for fetching instructions. To a lesser
degree, memory references to data also tend to be localized. Table-lookup
procedures repeatedly refer to that portion in memory where the table is stored.
Iterative procedures refer to common memory locations and array of numbers are
confined within a local portion of memory. The result of all these observations is the
locality of reference property, which states that over a short interval of time, the
addresses generated by a typical program refer to a few localized areas of memory
repeatedly, while the remainder of memory is accessed relatively infrequently.

If the active portions of the program and data are placed in a fast small memory, the
average memory access time can be reduced, thus reducing the total execution time
of the program. Such a fast small memory is referred to as a cache memory. It is
placed between the CPU and main memory in the memory hierarchy. The cache is
the fastest component in the memory hierarchy and approaches the speed of CPU
components.

The fundamental idea of cache organization is that by keeping the most frequently
accessed instructions and data in the fast cache memory, the average memory
access time of a computer system can be improved considerably by use of cache.

When the CPU refers to memory and finds the word in cache, it is said to produce a
hit. If the word is not found in cache, it is in main memory and it counts as a miss.

The performance of cache memory is frequently measured in terms of a quantity

called hit ratio. This is the ratio of the number of hits divided by the total CPU
references to memory (hits plus misses) is the hit ratio.

Hit ratio = hit / (hit + miss)

The basic characteristic of cache memory is its fast access time. Therefore, very little
or no time must be wasted when searching for words in the cache. The

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transformation of data from main memory to cache memory is referred to as a

mapping process.

Figure 4.3: Cache memory organization

Three types of mapping procedures are of practical interest when considering the
organization of cache memory.

1. Associative mapping

The fastest and most flexible cache organization uses an associative memory. This
organization is illustrated in Figure 4.4. The associative memory stores both the
address and content (data) of the memory word. This permits any location in cache
to store any word from main memory. The diagram shows three words presently
stored in the cache. The address value of 15 bits is shown as a five-digit octal number
and its corresponding 12-bit word is shown as a four-digit octal number. A CPU
address of 15 bits is placed in the argument register and the associative memory is
searched for a matching address. If the address is found, the corresponding 12-bit
data is read and sent to the CPU. If no match occurs, the main memory is accessed
for the word. The address data pair is then transferred to the associative cache
memory. If the cache is full, an address – data pair must be displaced to make room
for a pair that is needed and not presently in the cache. The decision as to what pair
is replaced is determined from the replacement algorithm that the designer chooses
for the cache. A simple procedure is to replace cells of the cache in round-robin
order whenever a new word is requested from main memory. This constitutes a first-
in first-out (FIFO) replacement policy.

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Figure 4.4 Associative mapping (all numbers in octal)

2. Direct mapping

Associative memories are expensive compared to random-access memories because

of the added logic associated with each cell. The possibility of using a random-access
memory for the cache is illustrated in Figure 4.5 below. The CPU address of 15 bits is
divided into two fields. The nine least significant bits constitute the index field and
the remaining six bits form the tag bits. The number of bits in the index field is equal
to the number of address bits required to access the cache memory.

Figure 4.5: Addressing relationships between main and cache memories.

In the general case, there are 2k words in cache memory and 2n words in main
memory. The n-bit memory address is divided into two fields: k bits for the index

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field and n − k bits for the tag field. The direct mapping cache organization uses the
n-bit address to access the main memory and the k-bit index to access the cache.
The internal organization of the words in the cache memory is as shown in Figure
4.6(b). Each word in cache consists of the data word and its associated tag. When a
new word is first brought into the cache, the tag bits are stored alongside the data
bits. When the CPU generates a memory request, the index field is used for the
address to access the cache.

Figure 4.6: Addressing relationships between main and cache memories.

The tag field of the CPU address is compared with the tag in the word read from the
cache. If the two tags match, there is a hit and the desired data word is in cache. If
the two tags match, there is a hit and the desired data word is in cache. If there is no
match, there is a miss and the required word is read from main memory. It is then
stored in the cache together with the new tag, replacing the previous value. The
disadvantage of direct mapping is that the hit ratio can drop considerably if two or
more words whose addresses have the same index but different tags are accessed
repeatedly. However, this possibility is minimized by the fact that such words are
relatively far apart in the address range (multiples of 512 locations in this example).

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3. Set-associative mapping.

As mentioned earlier one disadvantage of direct mapping is that two words with the
same index in their address but with different tag values cannot reside in cache
memory at the same time. Set-associative mapping is an improvement over the
direct-mapping organization in that each word of cache can store two or more words
of memory under the same index address. Each data word is stored together with its
tag and the number of tag-data items in one word of cache is said to form a set. An
example of a set-associative cache organization for a set size of two is shown in
Figure 4.7. Each index address refers to two data words and their associated tags.
Each tag requires six bits and each data word has 12 bits, so the word length is

2(6 + 12) = 36 bits.

Figure 4.7: Two-way set-associative mapping cache

An index address of nine bits can accommodate 512 words. Thus the size of cache
memory is 512 × 36. It can accommodate 1024 words of main memory since each
word of cache contains two data words. In general, a set-associative cache of set size
k will accommodate k words of main memory in each word of cache.

The octal numbers listed in Figure 4.7 are with reference to the main memory
content illustrated in Figure 4.6. The words stored at addresses 01000 and 02000 of
main memory are stored in cache memory at index address 000. Similarly, the words

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at addresses 02777 and 00777 are stored in cache at index address 777. When the
CPU generates a memory request, the index value of the address is used to access
the cache. The tag field of the CPU address is then compared with both tags in the
cache to determine if a catch occurs. The comparison logic is done by an associative
search of the tags in the set similar to an associative memory search: thus the name
“set-associative”. The hit ratio will improve as the set size increases because more
words with the same index but different tags can reside in cache. However, an
increase in the set size increases the number of bit s in words of cache and requires
more complex comparison logic.

When a miss occurs in a set-associative cache and the set is full, it is necessary to
replace one of the tag-data items with a new value. The most common replacement
algorithms used are: random replacement, first-in, first out (FIFO), and least recently
used (LRU). With the random replacement policy the control chooses one tag-data
item for replacement at random. The FIFO procedure selects for replacement the
item that has been in the set the longest. The LRU algorithm selects for replacement
the item that has been least recently used by the CPU. Both FIFO and LRU can be
implemented by adding a few extra bits in each word of cache.

Main Memories

There are two types of primary or main memories: volatile and non-volatile. Volatile
memory is the type of memory that will lose data when the power supply to the
memory goes off. An example of volatile memory is Random Access Memory (RAM).
Non-volatile memory keeps the data in the memory even it is not powered up (e.g.
ROM).

RAM

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The two most common types of RAMs are the static RAM (SRAM) and the dynamic
RAM (DRAM). Static RAMs hold the stored value in flip-flop circuits as long as the
power is on. SRAMs tend to be high-speed memories with clock cycles in the range
of 5 to 50 ns.

Figure 4.8: Static RAM structure

Static RAM Operation

 Transistor arrangement gives stable logic state

 State 1: C1 high, C2 low; T1 T4 off, T2 T3 on
 State 0: C2 high, C1 low; T2 T3 off, T1 T4 on
 Address line transistors T5 T6 form a switch
 Write – apply value to B & complement to B
 Read – value is on line B

Dynamic RAMs store values on capacitors. They are prone to noise and leakage
problems, and are cheaper and slower than SRAMs, clocking at 50 ns to 200 ns.
However, DRAMs are much denser than SRAMs—up to four times denser in a given
generation of technology.

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Figure 4.9: Dynamic RAM structure

DRAM Operation

 Address line active when bit read or written: — Transistor switch closed
(current flows)
 Write: — Voltage is applied to bit line (High for 1 low for 0) then address line
is activated. Transistor allows current to flow; transfers charge to capacitor
 Read: — Address line is activated – Transistor allows current to flow;
transfers charge from capacitor to bit line — Bit line fed to sense amplifier –
Compares with reference value to determine 0 or 1 — Capacitor charge must
be restored to complete the read operation

ROM

All ROMs are non-volatile, but they vary in the method used to enter (write) stored
data.

Masked-ROM: it is the simplest form of ROM and it is programmed during the

manufacturing by formation of physical patterns on the chip; subsequent changes of
stored data are impossible.

Programmable Read-Only Memories (PROMs): have a data path present between

every row and column when manufactured, corresponding to a stored 1 in every
data position. Storage cells are selectively switched to the 0 state once after
manufacture by applying appropriate electrical pulses to selectively open (blow out)

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row-column data paths. Once programmed, or blown, a 0 cannot be changed back to

a 1.

Erasable Programmable Read-Only Memories (EPROMs): also have all bits initially
in one binary state. They are programmed electrically (similar to the PROM), but all
bits may be erased (returned to the initial state) by exposure to ultraviolet (UV) light.
The packages for these components have transparent windows over the chip to
permit the UV irradiation. Electrically Erasable Programmable Read-Only Memories
(EEPROMs, E2PROM, or E-squared PROMs): may be written and erased by electrical
means. These are the most advanced and most expensive form of PROM. Unlike
EPROMs, which must be totally erased and rewritten to change even a single bit,
E2PROMs may be selectively erased. Writing and erasing operations for all PROMs
require times ranging from microseconds to milliseconds.

A recent form of EPROM and E2PROM is termed Flash memory, a name derived from
the fact that blocks of memory may be erased simultaneously. Flash memory of the
EPROM form is written using the hot-electron effect2 whereas E2PROM Flash is
written using Fowler-Nordheim (FN) tunnelling. Both types are erased using FN
tunnelling. Their large storage capacity has made this an emerging mass storage
medium. In addition, these types of memories are beginning to replace the role of
ROMs on many chips, although additional processing is required to manufacture
Flash memories in a standard CMOS technology.

Memories based on ferroelectric materials called FRAMs or FeRAMs, can also be

designed to retain stored information when power is off.

Auxiliary Memory

The most common auxiliary memory devices used in computer systems are magnetic
disks and tapes. Other components used, but not as frequently, are magnetic drums,
magnetic bubble memory, and optical disks. Although the physical properties of
these storage devices can be quite complex, their logical properties can be
characterized and compared by a few parameters. The important characteristics of
any device are its access mode, access time, transfer rate, capacity, and cost.

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The average time required to reach a storage location in memory and obtain its
contents is called the access time. In electromechanical devices with moving parts
such as disks and tapes, the access time consists of a seek time required to position
the read-write head to a location and a transfer time required to transfer data to or
from the device. Because the seek time is usually much longer than the transfer
time, auxiliary storage is organized in records or blocks. A record is a specified
number of characters or words. Reading or writing is always done on entire records.
The transfer rate is the number of characters or words that the device can transfer
per second, after it has been positioned at the beginning of the record.

Magnetic drums and disks are quite similar in operation. Both consist of high-speed
rotating surfaces coated with a magnetic recording medium. The rotating surface o f
the drum is a cylinder and that of the disk, a round flat plate. The recording surface
rotates at uniform speed and is not stared or stopped during access operations. Bits
are recorded as magnetic spots on the surface as it passes a stationary mechanism
called a write head. Stored bits are detected by a change in magnetic field produced
by a recorded spot on the surface as it passes through a read head. The amount of
surface available for recording in a disk is greater than in a drum of equal physical
size. Therefore, more information can be stored on a disk than on a drum of
comparable size. For this reason, disks have replaced drums in more recent computers

4.2 Memory Related Concepts

Virtual Memory

Virtual memory is a concept used in some large computer systems that permit the
user to construct programs as though a large memory space were available, equal to
the totality of auxiliary memory. In a virtual memory system, programmers are made
to believe that they have the total address space at their disposal. Moreover, the
address field of the instruction code has a sufficient number of bits to specify all
virtual addresses. Each address that is referenced by the CPU goes through an
address mapping from the so-called virtual address to a physical address in main
memory. Virtual memory is used to give programmers the illusion that they have a

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very large memory at their disposal, even though the computer actually has a
relatively small main memory. A virtual memory system provides a mechanism for
translating program-generated addresses into correct main memory locations. This is
done dynamically, while programs are being executed in the CPU. The translation or
mapping is handled automatically by the hardware by means of a mapping table.

Address space and memory space

An address used by a programmer will be called a virtual address, and the set of such
addresses the address space. An address in main memory is called a location or
physical address. The set of such locations is called the memory space. Thus the
address space is the set of addresses generated by programs as they reference
instructions and data; the memory space consists of the actual main memory
locations directly addressable for processing. In most computers the address and
memory spaces are identical. The address space is allowed to be larger than the
memory space in computers with virtual memory.

As an illustration, consider a computer with a main-memory capacity of 32K words (K

= 1024). Fifteen bits are needed to specify a physical address in memory since 32K =
215. Suppose that the computer has available auxiliary memory for storing 2 20 =
1024K words. Thus auxiliary memory has a capacity for storing information
equivalent to the capacity of 32 main memories. Denoting the address space by N
and the memory space by M, we then have for this example N = 1024K and M = 32K.

In a multi-program computer system, programs and data are transferred to and from
auxiliary memory and main memory based on demands imposed by the CPU.
Suppose that program 1 is currently being executed in the CPU. Program 1 and a
portion of its associated data are moved from auxiliary memory into main memory
as shown in Figure 4.10. Portions of programs and data need not be in contiguous
locations in memory since information is being moved in and out, and empty spaces
may be available in scattered locations in memory.

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Figure 4.10: Relation between address and memory space in a virtual memory
system

In this example, the address field of an instruction code will consist of 20 bits but
physical memory addresses must be specified with only 15 bits. Thus CPU will
reference instructions and data with a 20-bit address, but the information at this
address must be taken from physical memory because access to auxiliary storage for
individual words will be prohibitively long. (Remember hat for efficient transfers,
auxiliary storage moves an entire record to the main memory). A table is then
needed, as shown in Figure 4.11 to map a virtual address of 20 bits to a physical
address of 15 bits. The mapping is a dynamic operation, which means that every
address is translated immediately as a word is referenced by CPU.
The mapping table may be stored in a separate memory as shown in Figure 4.11 or in
main memory. In the first case, an additional memory unit is required as well as one
extra memory access time. In the second case, the table takes space from main
memory and two accesses to memory are required with the program running at half
speed. A third alternative is to use an associative memory as explained below.

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Figure 4.11: Memory table for mapping a virtual address.

Direct Memory Access - DMA

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The transfer of data between a fast storage device such as magnetic disk and
memory is often limited by the speed of the CPU. Removing the CPU from the path
and letting the peripheral device manage the memory buses directly would improve
the speed of transfer. This transfer technique is called direct memory access (DMA).
During DMA transfer, the CPU is idle and has no control of the memory buses.

Two control signals in the CPU that facilitate the DMA transfer are the bus request
input and bus grant output. The bus request (BR) input is used by the DMA controller
to request the CPU to relinquish control of the buses. When this input is active, the
CPU terminates the execution of the current instruction. The CPU activates the bus
grant (BG) output to inform the external DMA that the buses are in the high-
impedance state. The DMA that originated the bus request can now take control of
the buses to conduct memory transfers without processor intervention.

Figure 4.12: DMA transfer in a computer system

When the DMA terminates the transfer, it disables the bus request line. The CPU
disables the bus grant, takes control of the buses, and returns to its normal

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operation. When the DMA takes control of the bus system, it communicates directly
with the memory.

4.3 Pipelining
Pipelining is a technique used that allows multiple instructions to be overlapped in
execution. This allows different parts of the hardware to work on different
instructions at the same time.

Pipeline
It is a series of stages of work to be done as required in an instruction. Each of these
stages or steps is referred to as Pipe stage. Once a stage is completed, it passes the
result to the next segment in the pipeline and fetches the next operations from the
preceding stage. When an instruction proceeds from one stage to the next, it is
temporarily stored in a pipeline latch, so it does not interfere with a previous
instruction.
The time required for moving an instruction from one stage to the next is known as a
machine cycle (one clock cycle). The execution of one instruction involves several
machine cycles as it goes through the pipeline.
A basic five-stage pipeline in a RISC machine is illustrated in figure 4.13 below. (IF =
Instruction Fetch, ID = Instruction Decode, EX = Execute, MEM = Memory access, WB
= Register write back). In the fourth clock cycle (the green column), the earliest
instruction is in MEM stage, and the latest instruction has not yet entered the
pipeline.

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Figure 4.13: A five-stage pipelining

Advantages of pipelining
 It ensures an efficient use of the processor
 The time taken to execute instructions are most often reduced
Disadvantages of pipelining
 It involves the addition of hardware/hardware complexity
 The full potential of pipelining may not be achieved due to pipeline hazards.

Pipeline Hazards
For efficient pipelining, each stage of the instruction execution must be completed in
the same time but this is not usually the case. Pipelining hazards occur when the
next instruction cannot proceed until the previous instruction has either completed
or reached a certain point in the pipeline. The three kinds of pipelining hazards are:
structural hazards, data hazards and control hazards.

Structural hazards: these occur when a hardware component does not support the
execution of two instructions at the same time. An instance of structural hazard may
arise in a situation whereby instruction is being fetched from memory at the same
time another instruction is being written to memory.

Data hazards: these arise when a needed operand is not ready, because either the
current instruction has not finished computing it, or it has not arrived from storage.
Control hazards: they occur due to branch operations or branches in code. That is
when there is a need for a decision to be made based on the result of an instruction.

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CHAPTER FIVE

5.1 Microcontrollers
Whereas a microprocessor may be viewed as ‘CPU on chip’, a microcontroller is
usually described as ‘computer on chip’. Even though microcontroller share some
features with microprocessor, they differ in many aspects.

The microcontroller has built-in ROM, RAM, I/O ports, Timers, Serial Ports and other on-chip
peripherals to execute a single and dedicated task. This means that a microcontroller
requires less hardware to build a complete system.

Microcontrollers are mainly used in products that require a degree of control to be exerted by
the user.

A block diagram of a typical microcontroller is indicated in figure 5.1 below:

Figure 5.1: Layout of a typical microcontroller

5.2 Microcontroller modules

Processor Core: The CPU of the controller. It contains the arithmetic logic unit, the
control unit, and the registers (stack pointer, program counter, accumulator
register).

Memory: The memory is sometimes split into program memory and data memory. In
larger controllers, a DMA controller handles data transfers between peripheral
components and the memory.

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Interrupt Controller: Interrupts are useful for interrupting the normal program flow
in case of (important) external or internal events. In conjunction with sleep modes,
they help to conserve power.

Timer/Counter: Most controllers have at least one and more likely 2-3
Timer/Counters, which can be used to timestamp events, measure intervals, or
count events. Many controllers also contain PWM (pulse width modulation) outputs
which can be used to drive motors or for safe breaking (antilock brake system, ABS).
Furthermore the PWM output can, in conjunction with an external filter, be used to
realize a cheap digital/analog converter.

Digital I/O: Parallel digital I/O ports are one of the main features of microcontrollers.
The number of I/O pins varies from 3-4 to over 90, depending on the controller
family and the controller type.

As far as digital I/O is concerned, three registers control the behaviour of the pins:

Data Direction Register (DDR): Each bidirectional port has its own DDR, which
contains one bit for each pin of the port. The functionality of a pin (input or output)
is determined by clearing or setting its bit in the DDR. Different pins of a port may be
configured differently, so it is perfectly okay to have three pins configured to output
and use the other five as inputs. After a reset, the DDR bits are generally initialized to
input. Reading the register returns its value.

Port Register (PORT): This register is used to control the voltage level of output pins.
Assuming a pin has been configured to output. If its bit in the PORT register is set,
the pin will be high; if the bit is cleared, the pin will be low. To avoid overwriting the
other bits in the port when setting a particular bit, it is generally best to use the
controller’s bit operations. Otherwise, you must use a read-modify-write access and
hence must ensure that this access is not interrupted. For output pins, reading the
register returns the value you have written. For input pins, the functionality depends
on the controller. Some controllers allow you to read the state of input pins through
the port register. Other controllers, e.g. the ATmega16, use the port bits for other

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purposes if the corresponding pins are set to input, so here you will read back the
value you have written to the register.

Port Input Register (PIN): The PIN register is generally read-only and contains the
current state (high or low) of all pins, whether they are configured as output or as
input. It is used to read the state of input pins, but it can also be used to read the
state of output pins to verify that the output was taken over correctly. A write to this
register generally has no effect.

Analog I/O: Apart from a few small controllers, most microcontrollers have
integrated analog/digital converters, which differ in the number of channels (2-16)
and their resolution (8-12 bits). The analog module also generally features an analog
comparator. In some cases, the microcontroller includes digital/analog converters.

Interfaces: Controllers generally have at least one serial interface which can be used
to download the program and for communication with the development PC in
general. Parallel connections between the microcontroller and peripherals
established over I/O ports are the ideal solution for shorter distances up to several
meters. However, in other cases, when it is necessary to establish communication
between two devices on longer distances it is obviously not possible to use parallel
connections. Then, serial communication is the best solution. Many microcontrollers
also contain integrated bus controllers for the most common busses.

Larger microcontrollers may also contain PCI, USB, or Ethernet interfaces.

Watchdog Timer: The Watchdog Timer is a timer connected to a completely

separate RC oscillator within the microcontroller. Since safety-critical systems form a
major application area of microcontrollers, it is important to guard against errors in
the program and/or the hardware. The watchdog timer is used to reset the
controller in case of software “crashes”. If instructions resetting the watchdog timer are
set at the appropriate program locations, besides commands being regularly executed, then
the operation of the watchdog timer will not affect the program execution.

If for any reason (usually electrical noise in industry), the program counter "gets
stuck" at some memory location from which there is no return, the watchdog will

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not be cleared, so the register’s value being constantly incremented will reach the
maximum et voila! Reset occurs!

Debugging Unit: Some controllers are equipped with additional hardware to allow
remote debugging of the chip from the PC. So there is no need to download special
debugging software, which has the distinct advantage that erroneous application
code cannot overwrite the debugger.

Interrupt: In order to prevent the microcontroller from spending most of its time
endlessly checking for logic state on input pins and registers, an interrupt is
generated. It is the signal which informs the central processor that something
demands. As its name suggests, it interrupts regular program execution. It can be
generated by different sources so when it occurs, the microcontroller immediately
stops operation and checks for the cause. If it is needed to perform some operations,
a current state of the program counter is pushed onto the Stack and the appropriate
program is executed. This process is called interrupt routine.

Power Supply Circuit

There are two things worth attention concerning the microcontroller power supply
circuit:

Brown out is a potentially dangerous state which occurs at the moment the
microcontroller is being turned off or when power supply voltage drops to the
lowest level due to electric noise. Since the microcontroller consists of several
circuits which have different operating voltage levels, this can cause its out of control
performance. In order to prevent it, the microcontroller usually has a circuit for
brown out reset built-in. This circuit immediately resets the whole electronics when
the voltage level drops below the lower limit.

Reset pin is usually referred to as Master Clear Reset (MCLR) and serves for external
reset of the microcontroller by applying logic zero (0) or one (1) depending on the
type of the microcontroller. In case the brown out is not built in the microcontroller,
a simple external circuit for brown out reset can be connected to this pin.

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5.3 Microcontroller Architecture

There are mainly two categories of processors, namely, Von-Neumann (or Princeton)
architecture and Harvard Architecture. These two architecture differ in the way data
and programs are stored and accessed.

Von-Neumann/Princeton Architecture

Microcontrollers based on the Von-Neumann architecture have a single data bus

that is used to fetch both instructions and data. Program instructions and data are
stored in a common main memory. When such a controller addresses main memory,
it first fetches an instruction, and then it fetches the data to support the instruction.
The two separate fetches slows up the controller’s operation. Figure 5.2 shows the
Von-Neumann Architecture. The Von-Neumann architecture’s main advantage is
that it simplifies the microcontroller design because only one memory is accessed. In
microcontrollers, the contents of RAM can be used for data storage and program
instruction storage. For example, the Motorola 68HC11 microcontroller is based on
Von-Neumann architecture.

Example: An Instruction “Read a byte from memory and store it in the accumulator”
as follows:

Cycle 1 :- Read instruction

Cycle 2 - Read data out of RAM and put into Accumulator

Figure 5.2: Von Neuman Architecture

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Harvard Architecture

Microcontrollers based on the Harvard Architecture have separate data bus and an
instruction bus. This allows execution to occur in parallel. As an instruction is being
“pre-fetched”, the current instruction is executing on the data bus. Once the current
instruction is complete, the next instruction is ready to go. This pre-fetch
theoretically allows for much faster execution than Von-Neumann architecture, on
the expense of complexity. Figure 5.3 shows the Harvard Architecture. The Harvard
Architecture executes instructions in fewer instruction cycles than the Von-Neumann
architecture. For example, the Intel MCS-51 family of microcontrollers and PIC
microcontrollers uses Harvard Architecture. The same instruction (as shown under
Von-Newman architecture) would be executed as follows:

Cycle 1: - Complete previous instruction

- Read the “Move Data to Accumulator” instruction

Cycle 2: - Execute “Move Data to Accumulator” instruction

- Read next instruction

Hence each instruction is effectively executed in one instruction cycle.

Figure 5.3: Harvard Architecture

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5.4 Microprocessors and Microcontrollers Compared

Microprocessor is a single chip CPU, microcontroller contains, a CPU and much of the
remaining circuitry of a complete microcomputer system in a single chip.

Microcontroller includes RAM, ROM, serial and parallel interface, timer, interrupt
schedule circuitry (in addition to CPU) in a single chip.

–RAM is smaller than that of even an ordinary microcomputer, but enough

for its applications.

–Interrupt system is an important feature, as microcontrollers have to respond to

control oriented devices in real time. E.g., opening of microwave oven’s door cause
an interrupt to stop the operation. (Most microprocessors can also implement
powerful interrupt schemes, but external components are usually needed).

Microprocessors are most commonly used as the CPU in microcomputer systems.

Microcontrollers are used in small, minimum component designs performing
control-oriented activities.

Microprocessor instruction sets are processing intensive, implying powerful

addressing modes with instructions catering to large volumes of data. Their
instructions operate on nibbles, bytes, etc. Microcontrollers have instruction sets
catering to the control of inputs and outputs. Their instructions operate also on a
single bit. E.g., a motor may be turned ON and OFF by a 1-bit output port

5.5 Uses of microcomputer and microcontrollers

Microcontrollers and microprocessors share a lot of similarities in terms of their uses
largely due to the fact that one is virtually a subset of the other.

Microprocessors are typically used in either reactive or embedded systems.

 Reactive systems: are those that have an ongoing interaction with their
environment - for example, a fire-control system that constantly reacts to
buttons pressed by a pilot.
 Embedded systems are those used to control specialized hardware in which
the computer system is installed - for example, the microprocessor system
used to control the fuel/air mixture in the carburettor of many automobiles.
In embedded systems the software system is completely encapsulated by the
hardware that it controls.

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Microcontrollers are frequently found in household appliances such as microwave,

oven, refrigerators, television, VCRs and stereos; computers and computer
equipment (laser printers, modems, and disk drives), automobiles (engine control,
diagnostics, and climate control), environmental control (greenhouse, factory,
home), instrumentation, aerospace, and thousands of other uses. In many items,
more than one processor can be found.

Microcontrollers could be used where processing power is not so important. For

instance, controlling a microwave oven is easily accomplished with the smallest of
microcontrollers. On the other hand, if you are putting together a cruise missile you
will probably need to use processors with a bit more computing power.

Embedded processors and microcontrollers are used extensively in robotics. In this

application, many specific tasks might be distributed among a large number of
controllers in one system. Communications between each controller and a central,
possibly more powerful controller (or micro/mini/mainframe) would enable
information to be processed by the central computer, or to be passed around to
other controllers in the system.

A special application that microcontrollers are well suited for is data logging. Stick
one of these chips out in the middle of a corn field or up in a balloon, and monitor
and record environmental parameters (temperature, humidity, rain, etc). Small size,
low power consumption, and flexibility make these devices ideal for unattended data
monitoring and recording.

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PAST QUESTIONS

END OF FIRST SEMESTER EXAMINATION – 2014/2015

INSTRUCTION: Attempt All Questions In Section A TIME: 3 HRS

SECTION A
1. A microprocessor is a _______ chip integrating all the functions of a CPU of a
computer.
a. single b. double. c. all of the above d. None of the above

2. The Intel 8086 microprocessor is a _______ processor.

a. 8 bit. b. 16 bit. C. 20 bit d. 32 bit

3. The BIU pre-fetches the instruction from memory and store them in ________.
a. queue. b. register. c. memory. d. stack.

4. The process of copying data from a memory location is known as _____

a. reading b. writing c. controlling d. Booting

5. A flip-flop is a binary cell capable of storing information of

a. One bit b. Byte c. Zero bit d. Eight bit

6. ALE stands for ____________.

a. Address Latch Enable b. Address Level Enable

c. Address Leak Enable d. Address Leak Extension

7. The first microprocessor was__________.

a. 4004. b. 8080. c. 8085. d. 4008.

8. The performance of cache memory is frequently measured in terms of a quantity

called
a. Miss ratio. b. Hit ratio. c. Latency ratio. d. Read ratio.

9. Which of these registers is also known as the programme counter?

a. AX Register b. SP Register c. IP Register d. BP Register

10. A four bit number is given as 1001. Its 1's complement is

a. 1001 b. 11001 c. 0110 d. 0101

11. A nibble corresponds to

a. 4 bits b. 8 bits c. 16 bits d. 32 bits

12. The value of binary 1111 is

a. 23 -1 b. 24 c. 24 - 1 d. None of the above

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13. The memory unit that communicates directly with the CPU is called ______?

a. main memory b. Secondary memory

c. shared memory d. auxiliary memory.

14. A Kb corresponds to ________

a. 1024 bits b. 1000 bytes c. 210 bytes d. 210 bits

15. A 20-bit address bus allows access to a memory of capacity

a. 1 Mb b. 2 Mb c. 32Mb d. 64 Mb

16. A 32-bit address bus allows access to a memory of capacity

a. 64 Mb b. 16 Mb c. 1Gb d. 4 Gb

17. CPU performance may be measured in __________

a. BPS b. MIPS c. MHz d. VLSI

18. Which of the following is NOT a type of processor?

a. PowerPC 601 b. Motorola 8086 c. Motorola 68000 d. Intel Pentium

19. The program counter __________

a. stores the address of the instruction that is currently being executed

b. stores the next instruction to be executed

c. stores the address of the next instruction to be executed

d. stores the instruction that is being currently executed.

20. An assembly language program is translated to machine code by _______

a. an assembler b. a compiler c. an interpreter d. a linker

21. The word size of an 8086 processor is ________

a. 8 bits b. 16 bits c. 20 bits d 32 bits

22. The code used to boot up a computer is stored in __________

a. RAM b. ROM c. PROM d. EPROM

23. For a logical circuit there are 'n' binary inputs. Then the number of different input
combinations in the truth table is
a. 2n b. 2/n c. 2n d. 2(n+1)

24. A logical shift right micro-operation is performed on a register R, containing

11011010. What will be the content of R after the operation has been performed
four times?
a. 00001101 b. 11000010 c. 10100000 d. 11011010

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25. What is the 2’s complement of 01100010?

a. 01100010 b. 10011101 c. 10011110 d. 10011111

26. The stack is implemented by means of ______.

a. LIFO buffer b. FIFO buffer c. Stack d. None of the above
27. The method for updating the main memory as soon as a word is removed from
the Cache is called _______
a. write-through b. write-back c. protected write d. cache-write

28. The negative numbers in the binary system can be represented by

a. Sign magnitude b. 1's complement

c. 2's complement d. none of the above

29. Which memory is non-volatile and may be written only once.

a. RAM b. EE-PROM c. EPROM d. PROM

30. Which of these memories holds the information when the Power Supply is
switched off?
a. Static RAM b. Dynamic RAM c. EEROM d. None of the above

31. In Assembly language programming, it is possible to have zero address

instructions.
a. True b. False

32. Cache memory works on the principle of ________

a. Locality of data. b. Locality of memory

c) Locality of reference d. Locality of reference & memory

33. In _______ addressing mode the operand is given explicitly in the instruction.
a. Absolute. b. Immediate. c. Indirect. d. Direct.

34. If a register containing data (11001100)2 is subjected to arithmetic shift left

operation, then the content of the register after 'ashl' will be
a. (11001100)2 b. (1101100)2
c. (10011001)2 d. (10011000)2
35. In 8086 microprocessor, the address bus is ________ wide.
a. 10-bit. b. 12-bit. c. 16-bit. d. 20-bit

36. _______ are instructions that copy information from one location to another
either in the processor’s internal register set or in the external main memory.
a. Data transfer instructions. b. Program control instructions.

c. Input-output instructions. d. Logical instructions.

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37. Which of these is true about assembly language?

a. uses alphabetic codes in place of binary numbers used ain machine language

b. it is easier than machine language program

c. all of the above d. None of the above

38. _______ is executed on data stored in registers.

a. Macro-operation b. Micro-operation

c. Bit-operation d. Byte-operation

39. Which of the following statements correctly describe the Arithmetic logic unit?
I. perform arithmetic operations II. store data

III. perform comparison

a. I only b. II only c. I and II only d. I and III only

40. ______ is programmed at the time of its manufacturing.

a. ROM b. RAM c. PROM d. EPROM

41. Which of these two registers of the 8086 µP combine to form the address of the
next instruction?
a. SS and CS b. ES and DI c. DS and SP d. IP and CS

42. Which of these two registers of the 8086 µP combine to point to the destination
for a string copy?
a. SS and CS b. ES and DI c. DS and SP d. IP and CS

43. The pre-fetched instructions in the 8086 µP Queue are implemented by means of
_______.
a. LIFO buffer b. FIFO buffer c. Stack d. None of the above
44. The following instruction: MOV AL, 59H is specified for 8086 µP. What type of
addressing mode is used?
a. Direct addressing mode b. Register addressing mode

c. Immediate addressing mode d. Indexed relative addressing mode

45. Which of the following is not a micro-operation?

a. register transfer micro-operation b. arithmetic micro-operations
c. control micro-operation d. Shift micro-operation

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46. A watchdog timer is an __________.

a. external timer that resets the system if the software fails to operate properly.

b. internal timer that sets the system if the software fails to operate properly.

c. internal timer that resets the system if the software fails to operate properly.

d. None of the above

47. Which processor structure is pipelined?

a. all x80 processors b. all x85 processors

c. all x86 processors d. None of the above

48. Which of these flags is a control flag in 8086 µP?

a. sign flag b. auxiliary carry flag c. interrupt flag d. Zero flag

49. In 8086 µP the BIU pre-fetches instructions from memory and stores them in
________.
a. queue. b. register. c. memory. d. stack.

50. Which of the following technology can give high speed RAM?
a. TTL b. CMOS c. ECL d. NMOS

SECTION B

(Answer Any 5 Questions In This Section)

1. a. With the aid of a clearly labeled block diagram, explain what a microcontroller
is. [5marks]

b. What is the essence the interrupt controller in a microcontroller? [3marks]

List two applications of a microcontroller. [2marks]

2. a. State and explain what the following terms stand for:

i) SP ii) SS [4marks]

b. Given that SP = 634AH and SS = 24F6H, determine the following:

[6marks]

i) Logical address ii) Offset address

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iii) Physical address iv) The lower range of SS

3. Using only MOV, ADD, INC, NOT and HLT instructions, write an assembly language
program for an Intel 8086 µP that will load AL with 3FH and BL with 23H; subtract
the content of BL from AL, and keep the result in AL.

Add comments to explain each line of code. [10marks]

4. a. Explain the following terms:

i. Cache memory [2marks]

it is the average memory access time can be reduced, thus reducing the total
execution time of the program. Such a fast small memory

ii. Virtual memory [2marks]

is a concept used in some large computer systems that permit the user to
construct programs as though a large memory space were available

iii. Pipelining [2marks]

is a technique used that allows multiple instructions to be overlapped in

execution.

b. List and explain any two pipelining hazards. [4marks]

Structural hazards: these occur when a hardware component does not support the
execution of two instructions at the same time. An instance of structural hazard may
arise in a situation whereby instruction is being fetched from memory at the same
time another instruction is being written to memory.

Data hazards: these arise when a needed operand is not ready, because either the
current instruction has not finished computing it, or it has not arrived from storage.
Control hazards: they occur due to branch operations or branches in code. That is
when there is a need for a decision to be made based on the result of an instruction.

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5. a. List and explain the two sub-divisions of the flag register in the 8086
microprocessor. [4marks]

b. Given that AX = 874EH and BX = 9901H, determine whether ZF, CF and OF will
be set or reset after the following operations:
i) ADD AX, BX ii) XOR BX, AX [6marks]

END OF FIRST SEMESTER EXAMINATION – 2015/2016

EEE 301 MICROCOMPUTERS HND-EEE III

INSTRUCTION: Attempt All Questions In Section A TIME: 3 HRS

SECTION A

(1 MARK FOR EACH CORRECT ANSWER)

1. Assembly language
a. uses alphabetic codes in place of binary numbers used in machine

language

b. is the easiest language to write programs

c. need not be translated into machine language

d. None of these

2. In computers, subtraction is generally carried out by

a. 9’s complement b. 10’s complement

c.1’s complement d. 2’s complement

3. What characteristic of RAM memory makes it not suitable for permanent
storage?
a. too slow b. unreliable

c. it is volatile d. too bulky

4. The circuit used to store one bit of data is known as

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a. Register b. Encoder

c. Decoder d. Flip Flop

5. Q. 11 (2FAOC)16 is equivalent to
a. (195 084)10 b. (0010 1111 1010 0000 1100)2

c. Both (A) and (B) d. None of these

6. The average time required to reach a storage location in memory and obtain
its contents is called the
a. seek time b. turnaround time c. access time d. transfer time

7. The idea of cache memory is based ________

a. on the property of locality of reference

b. on the heuristic 90-10 rule

c. on the fact that references generally tend to cluster

d. all of the above

8. Cache memory acts between

a. CPU and RAM b. RAM and ROM

c. CPU and Hard Disk d. None of these

9. A Stack-organised Computer uses instruction of

a. Indirect addressing b. Two-addressing

c. Zero addressing d. Index addressing

10. Logic X-OR operation of (4ACO)H & (B53F)H results
a. AACB b. 0000 c. FFFF d. ABCD

11. An n-bit microprocessor has

a. n-bit program counter b. n-bit address register

c. n-bit ALU d. n-bit instruction register

12. Cache memory works on the principle of _______
a. Locality of data b. Locality of memory

c. Locality of reference d. Locality of reference & memory

13. In computers, subtraction is carried out generally by ______
a. 1's complement method b. 2's complement method

c. signed magnitude method d. BCD subtraction method

14. n bits in operation code imply that there are ___________ possible distinct
operators

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a. 2n b. 2n c. n/2 d. n2

15. A group of bits that tell the computer to perform a specific operation is
known as __________
a. Instruction code b. Micro-operation

c. Accumulator d. Register

16. The communication between the components in a microcomputer takes

place via the address and ________
a. I/O bus b. Data bus c. Address bus d. Control
lines

17. An instruction pipeline can be implemented by means of _______

a. LIFO buffer b. FIFO buffer c. Stack d. None of the above

18. Data input command is just the opposite of a ___________

a. Test command b. Control command

c. Data output d. Data channel

19. A binary digit is called a ___________

a. Bit b. Byte c. Number d. Character

20. The operation executed on data stored in registers is called

a. Macro-operation b. Micro-operation

c. Bit-operation d. Byte-operation
21. An interface that provides a method for transferring binary information
between internal storage and external devices is called ________
a. I/O interface b. Input interface

c. Output interface d. I/O bus

22. An address in main memory is called _________

a. Physical address b. Logical address

c. Memory address d. Word address

23. The instructions which copy information from one location to another either
in the processor’s internal register set or in the external main memory are
called _______
a. Data transfer instructions. b. Program control instructions.

c. Input-output instructions. d. Logical instructions.

24. An interface that provides I/O transfer of data directly to and from the
memory unit and peripheral is termed ________
a. DDA. b. Serial interface. c. BR. d. DMA.
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25. The 2s compliment form (Use 6 bit word) of the number 1010 is _______
a. 111100. b. 110110. c. 110111. d. 1011.

26. A register capable of shifting its binary information either to the right or the
left is called a ________
a. parallel register. b. serial register.

. c. shift register d. storage register.

27. What is the content of Stack Pointer (SP)?

a. Address of the current instruction b. Address of the next instruction

c. Address of the top element of the stack d. Size of the stack.

28. In Assembly language programming, minimum number of operands required

for an instruction is/are _________
a. Zero. b. One. c. Two. d. Both (B) & (C).

29. The memory unit that communicates directly with the CPU is called the
a. main memory b. Secondary memory

c. shared memory d. auxiliary memory.

30. A byte is a group of 16 bits.

a. True b. False

31. A nibble is a group of 16 bits.

a. True b. False

32. RAM chips _____.

a. allow the computer to store data electronically

b. store data indefinitely unless you delete it

c. are secondary memories

d. are programmed by the manufacturer.

33. Which of the following statements correctly describe the Arithmetic logic
unit?
I. Perform arithmetic operations II. Store data

III. Perform comparison

a. I only b. II only c. I and II only d. I and III only

34. Which of these statements is most accurate about DRAM? It is _____

a. used for cache memory b. more expensive than SRAM

c. cheaper than SRAM d. is only used at boot up time

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35. Which of these statements is most accurate about SRAM? It is

a. cheaper than DRAM b. used at boot up time only
c. used for cache memory d. slower to access than DRAM

36. To copy the hexadecimal number A to the BH register you write….

a. MOV 0BH, Ah b. MOV BH,[BH][ 0Ah]
c. MOV BH, Ah d. MOV BH, [Ah]

37. Given that the BL register contains 1111 0000, the effect of the following
instruction OR BL, 0000 1111 is to ….
a. clear BL b. store 1111 1111 in BL
c store 0000 1111 in BL d. leave BL unchanged

38. The SP register is typically used for accessing

a. strings b. memory c. stack d. data segment

39. Which of the following technology can give high speed RAM?
a. TTL b. CMOS c. ECL d. NMOS
40. After reset, CPU begins execution of instruction from memory address
a. 0101H b. 8000H c. 0000H d. FFFFH

41. If a register containing data (11001100)2 is subjected to arithmetic shift left

operation, then the content of the register after 'ashl' will be
a. (11001100)2 b. (1101100)2 c. (10011001)2 d.
(10011000)2

42. In 8086 microprocessor, the address bus is ________ wide.

a. 10-bit. b. 12-bit. c. 16-bit. d. 20-bit
43. The value of binary 1111 is ….
a. 23 -1 b. 24 c. 24 - 1 d. None of the above

44. The memory unit that communicates directly with the CPU is called ______?
a. main memory b. Secondary memory

c. shared memory d. auxiliary memory.

45. A Kb corresponds to ________

a. 1024 bits b. 1000 bytes c. 210 bytes d. 210 bits

46. A 20-bit address bus allows access to a memory of capacity

a. 1 Mb b. 2 Mb c. 32Mb d. 64 Mb

47. A 32-bit address bus allows access to a memory of capacity

a. 64 Mb b. 16 Mb c. 1Gb d. 4 Gb

48. CPU performance may be measured in __________

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a. BPS b. MIPS c. MHz d. VLSI

49. Which of the following is NOT a type of processor?

a. PowerPC 601 b. Motorola 8086

c. Motorola 68000 d. Intel Pentium

50. The program counter __________

a. stores the address of the instruction that is currently being executed

b. stores the next instruction to be executed

c. stores the address of the next instruction to be executed

d. stores the instruction that is being currently executed.

SECTION B

(Answer Any 5 Questions In This Section)

1. a. What is a micro-operation? [2marks]

A micro-operation is an elementary operation performed on the information
stored in one or more registers
b. List the four main types of micro-operations and give one example in each

case. [8marks]

 Arithmetic Micro-operations:
I. Addition
II. Subtraction
III. Increment
IV. decrement, add with carry
V. subtract with borrow
 Logic Micro-operations:
I. AND operator
II. OR operator
III. XOR operator
IV. Complement/NOT operator

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 Shift Micro-operations: these involve logical shift (right shift/ left shift),
circular shift (right circular shift/left circular shift), and arithmetic shift
operations (right arithmetic shift/left arithmetic shift).
 Register transfer micro-operations: The data transfer instructions are used to
move data between internal registers or between internal register and the
memory. The content of the source remains the same after the execution of
data transfer instructions. Flags are not affected by any of the instruction in
the group.
2. With the aid of clearly labelled block diagrams differentiate between a
microprocessor and a microcontroller. [10marks]

Microprocessor

Microcontroller

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3. a. Write and explain the instruction format for Intel 8086. [6marks]
b. Consider the following MOV instructions written for an Intel 8086 µP.

For each instruction, state with reasons whether it is legal or not.

[4marks]

i. MOV ES, 14AFH ii. MOV DS, CS

iii. MOV BX, 14AFH iv.MOV CX, 3AFF21H

4. a. i) What is memory segmentation? [2marks]

It is the division of memory in to a number of logical segment in an 8086 based
systems
ii) List the memory segments in the 8086 microprocessor. [4marks]

I. Code segment
II. Data segment
III. Extra segment
IV. Stack segment

b. Given that SP = 21F6H and SS = 35B7H, determine the following: [4marks]

i) Logical address ii) Offset address

iii) Physical address iv) The lower range of SS

5. a. Explain with examples the two main categories of bits in the flag register.
[4marks]
(a) Conditional or Status Flags and
(b) Control Flags.

b. Given that AX = 874EH and BX = 9901H, determine whether ZF, CF and OF

will be set or reset after the following operations:
i) ADD AX, BX ii) XOR BX, AX [6marks]

6. a. What is addressing mode? [2marks]

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It is a different modes used to access data or

It is a way of specifying data to be operated by an instruction

b. Explain the following addressing modes and give an example in each case.
[8marks]

i) Immediate addressing ii) Register addressing

iii) Direct addressing iv) Indexed addressing

Register addressing mode:

With register addressing mode, the operand to be accessed is specified as residing in
an internal register. Since memory is not accessed, it is faster.
Source and destination registers must match in size.
Example:
MOV AX, BX ; copies the content of register BX into register AX
MOV BX, DX
MOV ES, AX
ADD AL, BH
MOV AL, CX ; not possible due varying register sizes.

3.3.2 Immediate addressing mode:

Source operand is a constant
Immediate addressing is possible in all registers except segment and flag registers.
Example:
MOV BX, 1234H ; move 1234H into BX
MOV CX, 625 ; load the decimal value 625 into CX
ADD AL, 40H ; AL=AL+33H
MOV DS, 1234H ; illegal (data cannot be transferred directly into a segment
register)

Direct addressing:
The address of the data in memory comes immediately after the instruction operand
is a constant. The address is the offset address and this is put in a rectangular
bracket.
Example:

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MOV DL,[2400] ; move contents of DS:2400H into DL

Exercise: Find the physical address of the memory location and its content
after the execution of the following operation. Assume DS=1512H
MOV AL, 99H
MOV [3518], AL
Physical address of DS: 3518 => 15120+3518=18638H
The memory location 18638H will contain the value 99H
Indexed addressing: this mode work in similar manner to that of the based
addressing mode but the effective address is obtained by adding the displacement to
the value in an index register (SI or DI). SI and DI hold the offset address.

Examples:
MOV DX, [SI]+5 ;PA=DS(shifted left)+SI+5
MOV CL, [DI]+20 ;PA=DS(shifted left)+DI+20
MOV AL, [SI]+1234H

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