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 Fetching Instruction Register

Debug System
NVIC ALU
Circuit Decoder File

System Tick
Memory Protection Unit
Timer
 R0
R1 • These registers are used for data operations
Low Level Registers

R2 • Registers from R0 to R7 are called Low Level Registers

R3 because they are represented only by 3 bits ( 0 To 7 ).
R4
Therefor they are used mainly by the 16 bit instructions
R5
• Registers from R8 to R12 are called High Level Registers
R6
because they are represented by 4 bits. All of the 32 bit
R7
instructions can access these registers while Few of the
R8
High Level Registers

16 bit instructions can access these registers.

R9
• The initial value of these registers are not defined !
R10
R11
R12
 Physically there are 2 stack pointers, Main Stack Pointer MSP and Process Stack
Pointer PSP. The R13 is pointing to one of them.

R13

MSP PSP

Control [1] = 0 Control [1] = 1

• MSP is the default stack pointer, the processor uses it by default after reset.
• Changing the stack the pointer is done by changing bit 1 in the control register.

• The processor uses the MSP always when executing the exception handler.
It stores the return information for function calls and exceptions. On reset, the
processor sets the LR value to 0xFFFFFFFF.
Branch(B) vs Branch With Link(BL) :
Example
The Cortex-M architecture supports two similar
instructions: B and BL. /*
• B Instruction allows the user to branch to an
Some Code
instruction that does not immediately follow 1
the current instruction without saving any */
information about the current address.
Func(); Func
• BL Instruction saves the address of the
instruction immediately following the BL /*
command into the Link Register (R14). By Some Code
storing the address of the next instruction into 2

the link register, a function can “return” by */

moving the contents of the LR back into the PC
using the BX (Branch and Exchange) command.
 void main (void) void func (void)

; main assembly program ; func assembly program

;******************** ;********************
__main PROC __func PROC

; Initialize R0 ;Check if R0 equals 1 or not

MOV R0, #0x01 ;and save 0 or 1 to R1
TST R0, #0x01
; Call the function MOVEQ R1, #0
BL __func MOVNE R1, #1

;Loop forever ; Return from the function

B __main BX LR

ENDP ENDP
The Program Counter (PC) is register R15. It contains the current program address.
On reset, the processor loads the PC with the value of the reset vector, which is at
address 0x00000004.
Processor Reset Sequence:
Reset Handler • After reset, the PC is
0x00000000 0x20008000 loaded by 0x00000000
by hardware
• Processor saves the
0x00000004 0x20001000 value of the address
Jump to 0x00000000 to the
0x20001000 Start up Instruction 1 Startup Code MSP then jump to the
reset handler
0x20001004 Start up Instruction 2 • The instruction in the
reset handler is a jump
Jump to
0x2000FF00 Application Instruction 1 instruction to the
main function
startup code
0x2000FF04 Application Instruction 2 N.B. All addresses in Blue are for example
The CONTROL register controls the stack used and the privilege level for software
execution when the processor is in Thread mode.
Power On
“ Reset “
Handler

Privileged

Unprivileged
Example 1

; Write 1 to Control register to enable all interrupts

MOV R0, #1
MSR CONTROL, r0

Example 2

; Write 0 to Control register to enable all interrupts

MOV R0, #0
MSR CONTROL, r0
The Processor Status Word (xPSR) combines 3 registers:
1. Application Program Status Register (APSR)
2. Interrupt Program Status Register (IPSR )
3. Execution Program Status Register (EPSR)
The Application Program Status Register APSR contains the status flags of the
integer operations ( N, Z, C, V and Q ) resulted from the previous instruction
execution.
The Interrupt Program Status Register IPSR contains index of the current executing
exception.
The Execution Program Status Register EPSR is giving information about the execution
state of the processor. It contains the following bits:

1. The Thumb state bit which indicate the current used instruction set. In our case
it should be always 1 because we have only one instruction set (Thumb 2).
2. Interruptible Continuable Instruction (ICI).
When an interrupt occurs during the execution of an LDM or STM instruction, the processor:
• Stops the load multiple or store multiple instruction operation temporarily
• Stores the next register operand in the multiple operation to EPSRbits[15:12].
After servicing the interrupt, the processor:
• Returns to the register pointed to by bits[15:12]
• Resumes execution of the multiple load or store instruction.
When the EPSR holds ICI execution state, bits[26:25,11:10] are zero.

3. IF-Then Instruction
These three registers are used to mask interrupts.

To access the exception mask registers use the MSR and MRS instructions, or
the CPS instruction to change the value of PRIMASK or FAULTMASK.
The PRIMASK register prevents activation of all exceptions with configurable priority. It
disables all interrupts have a priority more than or equals to 0. It is used to disable
all exceptions except Reset, NMI and hard fault.
Example 1

; Clear PRIMASK (Enable interrupts)

CPSIE I
; Set PRIMASK (Disable interrupts)
CPSID I

Example 2
; Write 0 to PRIMASK to enable all interrupts
MOV R0, #0
MSR PRIMASK, R0
; Write 1 to PRIMASK to disable all interrupts
MOV R0, #1
MSR PRIMASK, R0
The FAULTMASK disables all interrupts have a priority more than or equals to -1. It is
used to disable all exceptions except Reset and NMI.
Example 1

; Clear FAULTMASK (Enable interrupts)

CPSIE F
; Set FAULTMASK (Disable interrupts)
CPSID F

Example 2
; Write 0 to FAULTMASK to enable all interrupts
MOV R0, #0
MSR FAULTMASK , R0
; Write 1 to FAULTMASK to disable all interrupts
MOV R0, #1
MSR FAULTMASK , R0
The BASEPRI register defines the minimum priority for exception processing. When
BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with the
same or lower priority level as the BASEPRI value.
Example 1

; Disable interrupts with priority 0x60-0xFF

MOV R0, #0x60
MSR BASEPRI, R0

Example 2

;Turn off BASEPRI masking

MOV R0, #0x0
MSR BASEPRI, R0
 Name Type Privilege Reset Value
R0-R12 RW Either Unknown

MSP RW Privileged See description

PSP RW Either Unknown

LR RW Either 0xFFFFFFFF

PC RW Either See description

PSR RW Privileged 0x01000000

ASPR RW Either Unknown

IPSR RO Privileged 0x00000000

EPSR RO Privileged 0x01000000

PRIMASK RW Privileged 0x00000000

FAULTMASK RW Privileged 0x00000000

BASEPRI RW Privileged 0x00000000

CONTROL RW Privileged 0x00000000

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