Microcontroller All Notes Ee
Microcontroller All Notes Ee
PABITRA MANDAL
LECTURER IN ETCE
RAGHUNATHPUR GOVERNMENT POLYTECHNIC
(Special thanks to my beloved students of 2025 batch EE)
8051 INTERRUPTS
8051 supports 5 interrupts.
2 External Interrupts are on the following pins
𝐼𝑁𝑇1, 𝐼𝑁𝑇𝑂
These interrupts can be ve edge or low-level triggered depending upon the ITO and IT1 bit in
TCON SFR. (ITX = 1-ve edge triggered) When any of these interrupts occur the respective bits
TE1 or IEO are set in the TCON SFR. If External Interrupts are enabled then the ISR is
executed from the respective address.
Interrupt Sequence
The following sequence is executed to service an interrupt: Address of next instruction of
the main program i.e. PC is Pushed into the Stack. All interrupts are disabled, by making EA
bit in IE SFR 0. Program Control is shifted to the Vector Address (location) of the ISR. The ISR
begins.
INTERRUPT PRIORITIES
8051 has only two priority levels for the interrupts: Low
and High. Interrupt priorities are set using the IP SFR.
Q1. Write a Program to add the contents of Internal RAM locations 40H and
41H. Store Result at 42H and Carry at 43H.
Q2. Write a Program to multiply the numbers B2H and 2FH. Store
Result in registers RO (LSB) and R1 (MSB) of Bank 2.
Q3.WAP to add a series of 10 numbers. The series begins from location 20H in
Internal RAM. Store the result at locations 30 and 31H.
DJNZ R1, REPEAT ; Decrement count. If Count is NOT ZERO then repeat.