MODULE 5 (chapter 2)

Structured Design and Testing

A good VLSI design system should ensure consistency across all stages of the design flow,
including:

 Behavioral level
 Structural (circuit) level
 Physical (layout) level

These stages are part of a structured design flow that transforms a high-level problem
specification into a working silicon chip.
To maintain clarity and avoid errors, the design flow must handle abstractions and
descriptions consistently at each level.

Throughout the design flow, designers must balance multiple parameters:

 Performance – speed, power, functionality.

 Die size – affects cost and yield.
 Time to design – affects development cycle.
 Ease of use and testing – impacts debug and verification effort.

Role of Design Tools in Flow

 Tools simplify the flow by automating steps like simulation, synthesis, and layout.
 Use of abstractions and constraints reduces complexity and speeds up design.
 Helps manage repetition and optimization in large, complex VLSI systems.

Design Strategy

The choice of design flow (manual vs automated) depends on:

 Project size and complexity

 Time and cost constraints
 Available tools and methods

The goal is to choose the most efficient design flow that leads to a reliable and testable chip
with minimal effort and maximum performance.
(a) CURRENT DESIGN APPROACH

This is the traditional method that many designers follow, which involves multiple manual
steps and iterative simulations to ensure correctness at each stage.

1. Problem Specification

 Define the functionality and requirements of the system to be designed.

2. Architecture Definition

 Decide the overall system architecture (e.g., processor type, memory structure, data
paths).
3. Simulate & Compare

 Simulate the architecture to check if it meets the requirements.

 Compare outputs to expected behavior.

4. Logic Design

 Create the logical representation using Boolean expressions, truth tables, or state
machines.
 Define how the system will behave logically.

5. Simulate & Compare

 Again, simulate the logic to verify correctness.

6. Circuit Design

 Convert the logic into gate-level circuits using transistors.

 Map the logical components to physical gates and cells.

7. Simulate & Compare

 Perform circuit-level simulation to ensure the behavior matches the specification.

8. Layout

 Design the physical layout of the chip, placing and routing components.
 Translate the schematic into a geometrical representation suitable for fabrication.

9. Extract, Simulate, Compare

 Extract parasitics (resistances, capacitances) from the layout.

 Simulate the extracted netlist to confirm post-layout behavior.
 Compare with previous simulations.

10. FAB (Fabrication)

 Final step where the chip is manufactured.

Note: This approach involves multiple iterations and manual simulations at each stage,
making it time-consuming and error-prone.

(b) IDEAL DESIGN APPROACH

This method represents a streamlined, automated design flow using high-level synthesis
tools and compilers. It's the vision for the future of digital design.

1. Problem Specification
  As in the current method, the design begins with defining what the system should do.

2. Behavioral Compiler

 A compiler converts high-level behavioral descriptions (e.g., in Verilog, VHDL, or C-

based hardware languages) into a more refined design.
 This abstracts away lower-level implementation details.

3. Behavioral Description

 A high-level description of the system's behavior (not logic gates, but algorithms or
operations like "add" or "compare").

4. Structural Compiler

 Transforms the behavioral description into a structural description (a netlist of

components such as ALUs, registers, multiplexers).
 This is close to logic design in the current method but automated.

5. Structural Description (Circuit)

 Represents how various hardware components are interconnected to perform the

intended operations.

6. Physical Compiler

 Automatically converts the structural design into a physical layout (placement and
routing).
 It handles delays, area, power, and other physical constraints.

7. Physical Description (Layout)

 Final layout ready for fabrication.

8. FAB (Fabrication)

 Same as the current flow, this is the chip manufacturing step.

Note: This approach eliminates the need for repeated manual simulations and comparisons at
each step. The compilers take care of translation, verification, and optimization, making
the flow faster, more reliable, and less error-prone.
 Structured design strategies
Objective of Structured Design

 Goal: Reduce the complexity of IC design so that even non-experts can design efficient chips.
 Inspired by Mead and Conway, structured strategies aim to make the chip design process
more systematic and manageable.

Key Techniques in Structured Design

1. Hierarchy

 Divide the design into modules, then further into submodules.

 Helps manage complexity by allowing focus on smaller sections at a time.
 Similar to software design—break large programs into functions.
 Parallel hierarchy allows concurrent design in behavior, structure, and layout.

In design flow:
Used during design entry and planning to organize and structure the chip design process.

2. Modularity

 Divide system into well-defined submodules with clear interfaces.

 Promotes reusability, easier debugging, and team collaboration.
 Clarifies the design and improves flexibility.

In design flow:
Supports RTL design, where different blocks (ALU, control unit, etc.) are developed
separately.

3. Regularity

 Use repeating patterns or identical structures (like arrays of cells).

 Simplifies layout and makes designs easier to verify.
 At higher levels, helps build complex systems using repeated functional blocks (like
processor cores).

In design flow:
Used in physical design and layout generation, where repeated blocks are placed and
routed.
4. Locality

 Locality means making sure each part does most of its work on its own—without
needing to talk too much to far-away parts.
 This keeps the connections short and simple (less "global wiring").
 It helps the machine run faster, and it's easier to fix if something goes wrong.
 Also, if two parts often work together, it's smart to place them near each other.

In design flow:
Important in floorplanning and placement steps to reduce interconnect delay and wiring
complexity.

Design styles
HANDCRAFTED MASK LAYOUT:

 This is the oldest and most detailed method of chip design.

 Designers manually design the layout of circuits at the mask level, which means they
define exactly how each transistor and wire should be placed.
 It takes a lot of expertise in logic, circuit design, and manufacturing.
 Over time, this method evolved from physical drawings to using computer tools.
 Advantage: You get the best performance and smallest chip size.
 Disadvantage: It's very time-consuming and hard to do when there are millions of
transistors.
 This method is rarely used now except for very high-performance or special-
purpose chips.

GATE ARRAY DESIGN:

A gate array is design where most of the transistor structures and layers are pre-
manufactured, and only a few metal layers are customized to create the desired logic
function. The metal layers define how these transistors are connected to form the logic circuit
the customer needs.

A key disadvantage of gate arrays is the predefined location of transistors. Because the
silicon wafer comes with transistors already diffused (placed), you can’t move them to
optimize for space or logic density.

As a result:

 Not all transistors are used in a design.

 Some silicon area is left unused or underutilized.
  You can't achieve the same density or performance as in a full-custom design, where
every transistor is placed manually for the specific logic function.

But the advantage is:

 Faster fabrication (because only metal layers need to be designed and

manufactured).
 Lower design cost compared to full-custom ASICs.

Routing Channels:
These are spaces left between rows of cells for placing metal interconnects. You need enough
channels to connect all gates without congestion.

Channelled Gate Array

 Has fixed empty spaces (channels) between rows of transistors for wiring.
 Easier to route wires but takes more chip area.
 Layout is simple and predictable.

Channelless Gate Array

 No fixed wiring spaces; wires run over the transistors using multiple metal layers.
 Saves chip area, so the chip is smaller and cheaper.
 Routing is more complex and needs advanced tools.


TYPICAL gate array Floor Plan:
Fig a:
Core (Centre Area):
is the main part of the chip where all the logic work happens.
filled with logic cells — tiny building blocks that perform basic operations like AND,
OR, NOT, etc.

I/O Pads (Outer Border):

These cells are pre-designed and arranged in neat rows and columns.
Input/Output pads.
connection points that allow the chip to talk to the outside world — like
getting signals in or sending results out.

Routing Channels (Between Logic Cells):

 These are paths or tracks used to connect one logic cell to another.
 The paths are laid out in rows and columns — like city roads — to carry signals.
 Some go left-right (horizontal), others go up-down (vertical).
 This organized routing helps keep the connections clean and efficient — no traffic
jams!

FIG (b) NAND Gate CMOS Schematic

Shows a 2-input NAND gate implemented with CMOS logic.

 Two PMOS transistors in parallel (pull-up network).

 Two NMOS transistors in series (pull-down network).
 VDD at the top and VSS at the bottom.
 Uses polysilicon for gates and metal for connections.
(a) SITE SCHEMATIC / SITE LAYOUT
Shows a general arrangement of NMOS and PMOS transistors in a CMOS gate array. The
layout distinguishes between poly, metal, and transistor diffusion areas.

(b) Transistor-Level Cell with Substrate Contacts

Shows how the transistors are placed and how VDD and VSS buses are connected to ensure
proper power supply.

(c) Cell Circuit and Layout

Shows the actual circuit of a cell and how the layout corresponds to it. Power rails are

(d) Flip-Flop Circuit

A circuit for a D flip-flop, a common sequential logic element. Useful in memory and state-
holding logic.

(e) NAND Gate Example Layout

Illustrates how a 2-input NAND gate can be implemented using the standard gate array
structure, connecting p- and n-devices via metal layers.
Phase 1: Design Translation

1. Customer creates schematic and test vectors, verifies functionality.

2. Customer & Intersil translate the design into CMOS macros and simulate.
3. Intersil does a preliminary layout and suggests changes if needed.
4. Revisions are made until the layout is acceptable.

Phase 2: Design Implementation

5. Intersil performs final placement and routing.

6. Customer reviews and approves layout.
7. Intersil simulates post-layout delays and performance.
8. Customer provides complete test vectors.
9. Intersil creates the final pattern generator tape.

Phase 3: Fabrication

10. Intersil fabricates chips, tests them, packages, and ships prototypes.

This flow ensures the gate array design is correct, optimized, and ready for fabrication.
STRAND CELL DESIGN:

This shows the typical layout of a standard cell chip, including:

 Pads: For input/output connections around the perimeter.

 Cells: Predefined functional units (like logic gates).
 Routing Channels: Horizontal and vertical spaces used to interconnect the cells.
 Functional Blocks: Areas containing specific logic functions.

Standard Cells are fixed.

 They are pre-designed and stored in a library by the foundry or EDA tool provider
(like Synopsys, Cadence).

Functional Blocks are not fixed.

 These are custom-designed for your particular chip.

 You write RTL code (in Verilog or VHDL), and then synthesis tools map that code to
a group of standard cells.
This figure details how standard cells are arranged on a chip:

o Cells have a fixed height but variable width.

o Circuitry is connected through power/ground rails (metal).
o Signals use polysilicon or metal connections.
o Dual Entry: I/O on both sides of the cell.
o Back-to-Back: Cells placed with their backs touching, sharing power
rails.
o Route Through: Empty cell space used just for routing signals.
o These formats support efficient cell placement and interconnection.

Symbolic Layout Methods:

Symbolic layout methods are high-level techniques ,Instead of immediately designing the
chip at the geometric (physical) level, symbolic layout allows you to represent circuit
components and their connections abstractly.

 Instead of defining exact geometries (like metal/poly layers), symbols are used to
represent cells, wires, power rails, and contacts.
 Designers define logical structure and interconnections between blocks.
 The CAD tools later translate (compile) this symbolic representation into mask-level
geometric layout (actual layers for fabrication).
 DESIGN FOR TESTABILITY (DFT)

Design for Testability (DFT) is a technique used in digital circuit design to make it easier to
test whether the hardware is working correctly after manufacturing.

Stuck-at Faults:
The most fundamental and widely used fault model is the stuck-at fault. This model assumes
a single fault in a circuit that forces a particular net (wire) to be stuck at either a logic 0 or a
logic 1, regardless of the intended signal. Imagine a broken wire stuck in the ground (logic 0)
or a faulty transistor permanently turned on (stuck-at-1). Stuck-at faults can be further
categorized as:

 Stuck-at-0 (SA0): The net is permanently stuck at logic 0.

 Stuck-at-1 (SA1): The net is permanently stuck at logic 1.
Stuck Open/short Faults:
Two Main Concepts in DFT

1. Controllability
o It is the ability to set a particular node (point) in the circuit to 0 or 1.
o Example: If you can force a flip-flop to 0 or 1 through inputs, it's controllable.
o Helps in applying test patterns.
2. Observability
o It is the ability to observe the value of an internal node from outside the
circuit.
o Example: If a change at a node reflects at the output, it is observable.
o Helps in detecting faults.

Tools like SCOAP help calculate controllability and observability automatically.

Three Main Approaches to DFT

1. Ad hoc testing – Simple, manual techniques.

2. Structured design for testability – Uses standard design methods like scan chains.
3. Self-test and built-in testing – Circuit tests itself using built-in test logic.

Ad Hoc Testing:

A group of simple methods to make circuits easier to test by:

 Reducing logic complexity

 Partitioning large circuits into smaller ones
 Adding extra inputs/outputs for testing (called test points)

Bit-Slice Testing and ILAs

What is a Bit-Sliced System?

 A design made by repeating small blocks (slices) to create bigger circuits (e.g., 4-bit
ALU made of four 1-bit slices).

What is an ILA (Iterative Logic Array)?

 A repeated unit of logic used in bit-sliced designs.

 Easier to test if all blocks behave similarly.

Types of ILA Testability

Type Description
C-testable Needs constant number of test patterns, no matter how many blocks.
I-testable All blocks give the same output for the same input. Easy to compare.
CI-testable Combines both above. Most efficient testing.

 Fig (a) Basic 1-bit counter cell with inputs (CI), outputs (CO), and a flip-flop (FF).
 Fig (b) Modified version with:
o A 2:1 multiplexer (MUX)
o Extra gates for controlling and comparing values
o Added logic makes it I-testable (same test works for all cells)

Structured Design for Testability

It involves inserting specific test features or modifying circuit structure to improve

controllability and observability of internal nodes.

Popular Method: LSSD (Level-Sensitive Scan Design)

Level-sensitive scan design (LSSD) is a DFT scan design method in which latches are used
in pairs, the two latches form a master/slave pair.
Normal-Mode: clk1 is on and data input is taken as input . we receive output at Q.
Clk2 and clk3 are off. It work as normal D flip flop.

Scan Mode: clk2 and clk3 are on and scan input is given as input .we receive output at scan
out. Clk1 is off. It works as scan D flip flop.

BILBO (Built-In Logic Block Observer:

This above diagram shows 3-bit BILBO (Built-In Logic Block Observer) circuitry, which
is used in VLSI testing for both scan and pattern generation (BIST - Built-In Self-Test)
purposes. The BILBO can function as:

1. A normal register (parallel load and shift)

2. A Linear Feedback Shift Register (LFSR) for pseudo-random pattern generation
3. A scan register for boundary scan testing

COMPONENTS:

 MUX: Multiplexer to select between functional data input and feedback data (for
LFSR)
 XOR gates: Used for LFSR feedback logic
 AND gates: Controlled by control signals (C0 and C1)
 Flip-flops (D-type): Store the state Q1, Q2, Q3
 Control Lines (C0, C1): Define the operating mode of the BILBO

OPERATING MODES:

Controlled by C1 and C0, which select one of the four modes of operation:

C1 C0 Mode Function

0 0 Normal mode Operates as a regular register (load Din)

0 1 Scan mode Acts as a scan register

1 0 LFSR (BIST pattern generation) Feedback logic through XORs

1 1 Reset or hold (optional or idle) Sometimes used for reset or undefined

DATA FLOW:

1. MUX Input Selection:

 The MUX takes Din or the XOR of outputs from flip-flops (used during test modes).
 Selection controlled by the XOR gate and control signals.

2. AND Gates:

 Control signals C0 and C1 ANDed with a1, a2, a3 to selectively enable feedback
paths.
3. Feedback and XORing:

 The XOR gates combine feedback from previous stages to generate new inputs in
LFSR mode.

4. Flip-Flops:

 Three D flip-flops store intermediate outputs Q1, Q2, Q3.

 Output Dout comes from Q3.