ECEN474: (Analog) VLSI Circuit Design

Fall 2010

Lecture 6: Layout Techniques

Sam Palermo
Analog & Mixed-Signal Center
Texas A&M University
Announcements
• Lab 2 next week
• Has a prelab
• Upgrading Cadence version

• Reading
• Johns/Martin 2.1, 2.3-2.5

• HW1 will be assigned this weekend and

due a week from Monday

2
Agenda
• MOS Fabrication Sequence
• CMOS Design Rules
• Layout Techniques
• Layout Examples

3
ECEN-474-2009 Jose Silva-Martinez

Fundamentals on Layout Techniques:

N-Well CMOS Technologies

P+ N+ P+

N-Well
Substrate is always connected
to the most negative voltage,
and is shared by all N-type
transistors

4
 MOS Fabrication Sequence
[Razavi]

5
 MOS Fabrication Sequence
[Razavi]

6
 MOS Fabrication Sequence
[Razavi]

“Front-End”
“Back-End”

7
 Contact and Metal Fabrication
[Razavi]

8
Transistor Geometries
• λ-based design rules allow a process and feature size-
independent way of setting mask dimensions to scale
• Due to complexity of modern processing, not used often today

• Minimum drawing feature = λ

L • Assume w.c. mask alignment <0.75λ
2λ

X • Relative misalignment between 2

5λ
masks is <1.5λ
λ

4λ
AGate = W * L
W 2λ λ
AD, AS = W * X
PS , PS = W + 2 X (3 sides)
2λ

• X depends on contact size

• 5λ in this example

9
ECEN-474-2009 Jose Silva-Martinez

BASIC SCNA CMOS LAYERS

Physical Layer P-channel MOSFET

N-well Metal 1
CVD Oxide
Drain Source
Silicon Nitride
Poly Gate
Polysilicon Layer 1
p+ Gate Oxide p+
Polysilicon Layer 2 n-well Bulk
p substrate
P+ Ion Implant
Bulk
N+ Ion Implant
Contact cut to n+/p_
N-channel MOSFET
CVD Oxide
Metal 1 Source
Metal 1
Drain
Via Oxide Cuts Poly Gate
Metal 2
n+ n+
Gate Oxide
Pad Contact (Overglass)
p substrate

Bulk
10
 ECEN-474-2009 Jose Silva-Martinez

X
Design Rule Basics d

X X

Metal

d
n+
n+
Implanted dopants
p, Na p, Na (a) Contact size
(a) Mask definition (b) After annealing Metal
S

Patterning sequence for a doped n+ n+

Minimum width and line. p, Na

spacing
xp
S (b) Side view
Geometry of a contact
cut
Depletion
regions
x
n+ n+
Nd Nd

n+ n+

p, Na (a) Masking (b) Registration

Design tolerance
Depletion regions due to parallel n+ lines
11 Contact spacing rule
 Nselect
Active area border
ECEN-474-2009 Jose Silva-Martinez

Poly gate
Active
W

Nselect Active Gate overhang in MOSFET

layout
n+
n+
p-Substrate
p-Substrate
Poly gate Poly gate

(a) Correct mask sizing (b) Incorrect mask sizing

Formation of n+ regions in an n-channel (a) No overhang (b) With

MOSFET misalignment
Active area border
Effect of misalignment without overhang
Resist
Metal Metal Metal
s

poly
Poly gate
substrate substrate substrate
W

Gate spacing form an (a) Resist pattern (b) Isotropic etch (c) anisotropic etch
n+ edge
Effect12 of misalignment without overhang
ECEN-474-2009 Jose Silva-Martinez

Mask Number Mask Layer

1 NWELL Nselect

Poly
2 ACTIVE Active

W'
W
3 POLY
L'
4 SELECT Side View

5 POLY CONTACT

6 ACTIVE CONTACT

7 METAL1 n+ n+
L

8 VIA FrontView

9 METAL2
Difference between the drawn and physical
10 PAD
values for channel length and the channel
11 POLY2 width

Design Rule Layers

13
ECEN-474-2009 Jose Silva-Martinez

Polysilicon Gate L'

Metal Drain
xox
Polysilicon
Gate
n+ n+ W
Gate Oxide Field
oxide n+ L n+
p substrate (Bulk)
p
Bulk

Structure of a n-channel MOSFET Perspective view of an n-channel

2λ MOSFET
2λ 2λ
λ n+/p+ n+/p+ 2 or 3λ
• Minimum transistor width is set
2λ by minimum diffusion width
λ
Active
Poly
Poly
• 2 or 3λ (check with TA)
contact

• Often, we use a use a slightly

contact

λ 2λ λ larger “minimum” that is equal

Example of Layout Rules to the contact height (4λ in this
example)
14
ECEN-474-2009 Jose Silva-Martinez
N-channel MOSFET P-channel MOSFET
CVD Oxide CVD Oxide
Metal 1 Metal 1
Source Drain Drain Source

Poly Gate Poly Gate

n+ n+ p+ Gate Oxide p+
Gate Oxide
n-well Bulk
p substrate p substrate

Bulk Bulk
Gate
(a) Cross section Gate

Source Drain Drain Source

Bulk Bulk

(b) Circuit symbol

n+ Poly n+ n+ Poly n+

W
W

L L
n-well

(c) Top 15view

ECEN-474-2009 Jose Silva-Martinez

Stick Diagrams
D
Poly
G
Metal 1
N+/P+
Contact S

(a) Definitions (b) MOSFET

VDD VDD

Mp Mp In

In Out
Out

Mn
Mn

Gnd Gnd

Stick diagrams for the CMOS Inverter

16
ECEN-474-2009 Jose Silva-Martinez

The CMOS Inverter

VDD

Mp

Vin Vout

Mn

Wp

Lp

N-Well
Metal
Metal VDD VDD p+
n+
pFET
Lp

pFET

Wp
Metal Out

p+
nFET Poly In

WN
nFET
LN

Metal GND

n+
WN
LN

Basic Inverter Layout Alternate Inverter Layout

17
ECEN-474-2009 Jose Silva-Martinez

Standard Cells: VDD, VSS and output run in Parallel

Metal VDD
pFET

B MpB MpA

Vo

MnB
Out

A MnA
n+
CMOS NAND2 logic gate
A B nFET
Metal GND

Metal VDD

MpA pFET

p+
MpB

Vo Out
A B nFET

MnA MnB

CMOS NOR2 logic gate

A B
Metal GND

18
 ECEN-474-2009 Jose Silva-Martinez

Wide Analog Transistor: Analog techniques

• Unacceptable drain and source resistance
• Stray resistances in transistor structure
• Contacts short the distributed resistance of diffused areas
Most of the current will be shrunk to this side Current is spread

19
ECEN-474-2009 Jose Silva-Martinez

Transistor orientation
• Orientation is important in analog circuits for matching purposes

20
 ECEN-474-2009 Jose Silva-Martinez

Stacked Transistors

• Wide transistors need to be split

• Parallel connection of n elements (n = 4 for this example)
• Contact space is shared among transistors
• Parasitic capacitances are reduced (important for high speed )

Drain

Gate
Source

Note that parasitic capacitors are lesser at the drain

21
ECEN-474-2009 Jose Silva-Martinez

Matched Transistors

• Simple layouts are prone to process variations, e.g. VT, KP, Cox
• Matched transistors require elaborated layout techniques

M1 M2

Differential pair requiring “matched transistors”

Process Variations

Drain M1 Drain M2

Source
22
ECEN-474-2009 Jose Silva-Martinez

Interdigitized Layout
• Averages the process variations among transistors
• Common terminal is like a serpentine

23
ECEN-474-2009 Jose Silva-Martinez

Why Interdigitized?

M1 M2 M2 M1 M1 M2 M2 M1

KP=1 KP2 KP3 KP4 KP5 KP6 KP7 KP8

• Process variations are averaged among transistors

KPs for M1: KP1+KP4+KP5+KP8 M2: KP2+KP3+KP6+KP7
• Technique maybe good for matching dc conditions
• Uneven total drain area between M1 and M2. This is undesirable for ac
conditions: capacitors and other parameters may not be equal
• A more robust approach is needed (Use dummies if needed !!)

24
ECEN-474-2009 Jose Silva-Martinez
A method of achieving good matching is shown in the following figure :

• Each transistor is split in four equal parts interleaved in two by two’s.

So that for one pair of pieces of the same transistor we have currents
flowing in opposite direction.
• Transistors have the same source and drain area and perimeters, but
this topology is more susceptible to gradients
25 (not common centroid)
 ECEN-474-2009 Jose Silva-Martinez

Common Centroid Layouts

Usually routing is more complex
CENTROID
3 M1 M2 M1 M2 (complex layout)

M1: 8 transistors
M2 M1 M2 M1 (0,3) (0,1)
2
(1,2) (1,0)
(2,3) (2,1)
(3,2) (3,0)
1 M1 M2 M1 M2
M2: 8 transistors
(0,2) (0,0)
M2 M1 M2 M1 (1,3) (1,1
0 (2,2) (2,0)
(3,3) (3,1)
0 1 2 3

26
ECEN-474-2009 Jose Silva-Martinez

Common Centroid Layouts

• Split into parallel connections of even parts
• Half of them will have the drain at the right side and half at the left
• Be careful how you route the common terminal
•Cross talk (effect of distributed capacitors  RF applications)!

27
ECEN-474-2009 Jose Silva-Martinez

•Many contacts placed close to one another reduces series resistance

and make the surface of metal connection smoother than when we use
only one contact; this prevents microcraks in metal;

• Splitting the transistor in a number of equal part connected in parallel

reduces the area of each transistor and so reduces further the parasitic
capacitances, but accuracy might be degraded!

28
ECEN-474-2009 Jose Silva-Martinez

Diffusion resistors

Diffused resistance

Diffused resistance

well resistance

Pinched n-well resistance

29
 ECEN-474-2009 Jose Silva-Martinez

Integrated Resistors
• Highly resistive layers (p+, n+, well or polysilicon)
• Rdefines the resistance of a square of the layer
• Accuracy less than 30% L
Current flow t
Resistivity (volumetric
measure of material’s
resistive characteristic)
ρ (Ω-cm) W

L
Sheet resistance (measure
of the resistance of a R= ρ/t (Ω/)
uniform film with arbitrary W
thickness t

W R = 2Rcontact + (L/W) R
L
30
ECEN-474-2009 Jose Silva-Martinez

TYPICAL INTEGRATED RESISTORS

L
R = 2R cont + R W
W L

Type Sheet Accuracy Temperature Voltage

of layer Resistance Coefficient Coefficient
W/0 % ppm/oC ppm/V
n + diff 30 - 50 20 - 40 200 - 1K 50 - 300
p + diff 50 -150 20 - 40 200 - 1K 50 - 300
n - well 2K - 4K 15 - 30 5K 10K
p - well 3K - 6K 15 - 30 5K 10K
pinched n - well 6K - 10K 25 - 40 10K 20Κ
pinched p - well 9K - 13K 25 - 40 10K 20Κ
first poly 20 - 40 25 - 40 500 - 1500 20 - 200
second poly 15 - 40 25 - 40 500 - 1500 20 - 200

Special poly sheet resistance for some analog processes might be as high as 1.2 KΩ/
31
 ECEN-474-2009 Jose Silva-Martinez

Large Resistors
In order to implement large resistors :

• Use of long strips (large L/W)

• Use of layers with high sheet resistance (bad performances)

Layout : rectangular “serpentine”

L L ρ
R= R = ⋅
W W xj

32
 ECEN-474-2009 Jose Silva-Martinez

Well-Diffusion Resistor
• Example shows two long resistors for KΩ range
• Alternatively, “serpentine” shapes can be used
• Noise problems from the body
• Substrate bias surrounding the well
• Substrate bias between the parallel strips

Dummies

33
 ECEN-474-2009 Jose Silva-Martinez

Factors affecting accuracy :

Plastic packages cause a large pressure on the die (= 800 Atm.). It determines a variation of
the resistivity.

For <100> material the variation is unisotropic, so the minimum is obtained if the resistance
have a 45o orientation. compensated

Temperature :

Temperature gradient on the

chip may produce thermal
induced mismatch.

uncompensated

34
 ECEN-474-2009 Jose Silva-Martinez

Etching

Wet etching : isotropic (undercut effect)

HF for SiO2 ; H3PO4 for Al
∆x for polysilicon may be 0.2 – 0.4 µm with
standard deviation 0.04 – 0.08 µm.
Reactive ion etching (R.I.E.)(plasma etching
associated to “bombardment”) : unisotropic.
∆x for polysilicon is 0.05 µm with standard deviation 0.01 µm

Boundary :

The etching depends on the

boundary conditions

• Use dummy strips

35
ECEN-474-2009 Jose Silva-Martinez

Side diffusion effect : Contribution of endings

Side Diffusion “widens” R Impact of Rcont depends on relative geometry

Interdigitized structure :

36
ECEN-474-2009 Jose Silva-Martinez

Poly Resistors
First polysilicon resistance

First polysilicon resistance with a

well shielding

Second polysilicon resistance

Second polysilicon resistance with a

well shielding

37
 ECEN-474-2009 Jose Silva-Martinez

Typical Resistance Process Data

0.8 µm process
Sheet Resistance Width Variation Contact
(Ω/ ) (µm ) Resistance
(measured-drawn) (Ω)
N+Actv 52.2 -0.66 66.8
P+Actv 75.6 -0.73 37.5
Poly 36.3 -0.10 30.6
Poly 2 25.5 0.31 20.7
Mtl 1 0.05 0.56 0.05
Mtl 2 0.03 -0.06
N-Well 1513

Gate oxide thickness 316 angstroms

38
 ECEN-474-2009 Jose Silva-Martinez

TYPES OF INTEGRATED CAPACITORS

Electrodes : metal; polysilicon; diffusion

ε ox
Insulator : silicon oxide; polysilicon oxide; CVD oxide C= WL
t ox

2 2
  ∆ε r   ∆t ox   ∆L  2  ∆W  2
2
 ∆C
  =   +   +   + 
 C   ε r   t ox   L   W 

TOP VIEW 39
ECEN-474-2009 Jose Silva-Martinez

Factor affecting accuracy

• Oxide damage
• Impurities
 ∆ε ox   ∆t ox



 
• Grow rate
• Bias condition
• Bias history (for CVD)  ε ox  • Poly grain size  t ox 
• Stress
• Temperature

 ∆L   ∆W 
• Etching  ; 
• Alignment  L   W 

2 2
 ∆C   ∆ε r
2
  ∆t ox   ∆L   ∆W 
2 2
∆C
 =   +   + ≈ 1 − 0.1%

 C   εr    L  +  W  C
  t ox 
40
 ECEN-474-2009 Jose Silva-Martinez

Poly1 - Poly2 Capacitor

Poly 2

Poly 1

• Area is determined by poly2

• Problems
• undercut effects
• nonuniform dielectric thickness
• matching among capacitors
•Minimize the rings (inductors)

41
ECEN-474-2009 Jose Silva-Martinez

Accuracy of integrated capacitors

Perimeter effects led the total capacitance:

C = CA A
A = (x-2∆x)(y- 2∆y)
CA = capacitance per unit area
= (xy - 2x∆y - 2y∆x - 4∆x ∆y)
Assuming that ∆x = ∆y = ∆e ∆y
A = (xy - 2∆e(x + y) - 4∆2e)
A ≈ xy - 2∆e(x + y)
Real Area ∆x
∴Ce = - 2∆e(x + y) y of Poly 2
The relative error is
ε = Ce/C
= -2∆e(x + y) / xy
x
Then maximize the area and minimize the
perimeter  use squares!!!

42
 ECEN-474-2009 Jose Silva-Martinez

Common Centroid Capacitor Layout

•Unit capacitors are connected in

parallel to form a larger capacitance

•Typically the ratio among capacitors

is what matters

•The error in one capacitor is

proportional to perimeter-area ratio

•Use dummies for better matching

(See Johns & Martin Book, page
112)

43
ECEN-474-2009 Jose Silva-Martinez
Common centroid structures

C1 C2 C3 C4 C5

TC1 TC2 TC3 TC4 TC5

C2 = C1
C3 = 2C1
C4 = 4C1
C5 = 8C1

44
 ECEN-474-2009 Jose Silva-Martinez

“Floating” Capacitors
Be aware of parasitic capacitors

poly2
Polysilicon-Polysilicon: Bottom plate
CP1 C1 CP2’’
capacitance is comparable (10-30 %) poly1
with the poly-poly capacitance CP2’

substrate
C1
CP1, CP2’’ are very small (1-5 % of C1)
CP1 CP2’ is around 10-50 % of C1
CP2

metal2
Metal1-Metal2: More clean, C1
but the capacitance per
CP1 metal1
micrometer square is smaller. CP2 Thick oxide
Good option for very high
frequency applications ( C~ 0.1- substrate
0.3 pF).
CP2 is very small (1-5 % of C1)

45
ECEN-474-2009 Jose Silva-Martinez

Typical Capacitance Process Data (See MOSIS webside for the

AMI 0.6 CMOS process)

Capacitance N+Actv P+Actv Poly Poly 2 Mtl 1 Mtl 2 UNITS

Area 292 290 35 20 13 aF/µm2

(substrate)
Area 1091 684 49 26 aF/µm2
(N+active)
Area 1072 677 aF/µm2
(P+active)
Area (poly) 599 45 23 aF/µm2
Area (poly2) 900 45 aF/µm2
Area (metal1) 42 aF/µm2
Fringe 80 170 36 25 aF/µm
(substrate)
Fringe (poly) 59 39 aF/µm

a=10-18, f=10-15, p=10-12, n=10

46
-9 µ=10-6, m=10-3
ECEN-474-2009 Jose Silva-Martinez

Stacked Layout for Analog Cells

Stack of elements with the same width

Transistors with even number of parts have the source (drain) on both
sides of the stack

Transistors with odd number of parts have the source on one end and the
drain on the other. If matching is critical use dummies

If different transistors share a same node they can be combined in the

same stack to share the area of the same node (less parasitics)

Use superimposed or side by side stacks to integrate the cell

47
ECEN-474-2009 LATCH-UP ISSUES: Guard rings Jose Silva-Martinez

B Sn G Dn Dp G Sp BW

P+ N+ N+ P+ P+ P+

substrate N

P
substrate P

Sp

Sn BW

BW RBW
B

RB
POSITIVE FEEDBACK!

RBW Sp System may lock!

Reduce as much as possible RB and RBW: Place guard

contacts everywhere

Be sure Base-Emitter voltages are such that the BJTs are off!

RB If possible, B and BW must be connected to the most negative

and positive voltages, respectively!
Sn 48
ECEN-474-2009 Jose Silva-Martinez

Analog Cell Layout

• Use transistors with the same orientation

• Minimize S/D contact area by stacking transistors (to

reduce parasitic capacitance to substrate)

• Respect symmetries

• Use low resistive paths when current needs to be carried (to

avoid parasitic voltage drops)

• Shield critical nodes (to avoid undesired noise injection)

• Include guard rings everywhere; e.g. Substrate/well should

not have regions larger than 50 um without guard
protections (latchup issues) 49
 ECEN-474-2009 Jose Silva-Martinez

•M1 and M2 must match. Layout is interdigitized

•M3 and M4 must match. M6 must be wider by 4*M3
•M7 must be 2*M5
•Layout is an interconnection of 3 stacks; 2 for NMOS and 1 for PMOS
•Capacitor made by poly-poly
Not the best floorplan

M3 M6 M6 M6 M6 M4
M3 M4

M6 C
M1 M2 M1 M2 M1 M2
M1 M2

M8
M5 M5 M7 M7 M7 M7 M5 M8
M7

Pay attention to your floor plan! It is critical for

minimizing50iterations: Identify the critical elements
ECEN-474-2009 Jose Silva-Martinez

51
ECEN-474-2009 Jose Silva-Martinez

52
Layout (of something we should not do) example (cap related)
ECEN-474-2009 Jose Silva-Martinez

Following slides were provided by some of Dr. Silva’s

graduate students.

Special thanks to Fabian Silva-Rivas, Venkata Gadde, Marvin

Onabajo, Cho-Ying Lu, Raghavendra Kulkarni and Jusung Kim

53
 ECEN-474-2009 Jose Silva-Martinez

Figure: Layout of a single stage fully differential

54
amplifier and its CMFB circuit.
1. I/p NMOS diff pair 2. PMOS (Interdigitated) 3. Resistors for VCM 4.Capacitors (Common centroid)
 ECEN-474-2009 Jose Silva-Martinez

Capacitive network
Resistive network (Common centroid)

Fully differential
amplifier

Figure: Layout of a second order Active

55 RC low-pass Filter (Bi-quad)
ECEN-474-2009 Jose Silva-Martinez

• 3-bit quantizer in Jazz 0.18μm CMOS technology

• S/H: sample-and-hold circuit that is used to sample the continuous-input signal
• Core: contains matched differential pairs and resistors to create accurate reference levels for the analog-to-
digital conversion 56
• Latches: store the output bits; provide interface to digital circuitry with rail-to-rail voltage levels
ECEN-474-2009 Jose Silva-Martinez

• High-speed D-Flip-Flop in Jazz 0.18μm CMOS technology

• Resolves a small differential input with 10mV < Vp-p < 150mV in less than 360ps
• Provides digital output (differential, rail-to-rail) clocked at 400MHz
• The sensitive input stage (1st differential pair) has a57separate “analog” supply line to isolate it from the noise
on the supply line caused by switching of digital circuitry
ECEN-474-2009 Jose Silva-Martinez

Design example (industrial quality): Simplest OTA

58
ECEN-474-2009 Jose Silva-Martinez

Overall amplifier: Have a look on the

59
guard rings and additional well!
ECEN-474-2009 Jose Silva-Martinez

BIAS: you may be able to see the dummies,

60
symmetry and S/D connections
ECEN-474-2009 Jose Silva-Martinez

From downstairs

Differential pair
61
ECEN-474-2009 Jose Silva-Martinez

62
ECEN-474-2009 Jose Silva-Martinez

Details on the P-type current mirrors

63
ECEN-474-2009 Jose Silva-Martinez

Q-value of Spiral
Inductors in CMOS
Process
Most of the following slides were taken from

Seminar by: Park, Sang Wook

TAMU, 2003

64
 What is Q?
energy stored
Q ≡ω
average power dissipated

ωLs
Q=
Simple Inductor Model: Rs

Integrated Spiral Inductor “Pi” Model

65
ECEN-474-2009 De-Embedding Jose Silva-Martinez

66
 ECEN-474-2009 Jose Silva-Martinez
Equivalent Circuit & Calculation

Cs

9
Q-factor
Port1 Ls Rs Port2 8

6
Cox1 Cox2 5

2
Csub Rsub Csub Rsub 1

0
0 1 2 3 4 5 6
Frequncy (GHz)

Equivalent Circuit Parameter Calculation

67
ECEN-474-2009 Jose Silva-Martinez
Layout & Structure

Metal-6
(thickness=2um)

Metal-5
under path
N : # of Turns
Via-5

R : Radius
Oxide

Substrate

S : Space W : Width
(=1.5um) (=14.5um)

68
ECEN-474-2009
Layout Split 1 Jose Silva-Martinez

Shape & Radius

9
Q-factor
8 NxWxS s�q�u�a�
r �e��
)
0
6
=
(R
(4.5x15x1.5)
7

5
o�c�t �a�
g�o �n�
)
0
6
=
(R
�

3
square (R=60)
2 octagon (R=60) s�q�u�a�
r �e��
)
0
3
=
(R
square (R=30)
1
octagon (R=30)
0
0 1 2 3 4 5 6 o�c�t �a�
g�o �n�
)
0
3
=
(R
�
Frequncy (GHz)

" S�h�a�p�
e � �: � �O�
c �t �a�
re
a
u
q
S
>
n
o
�
g
" R�a�d�i�
u�s � �:�
3
>
0
6
69
ECEN-474-2009 Layout Split 2 Jose Silva-Martinez

PGS (Patterned Ground Shield) material

9
Q-factor n�o�
e
�
n
8
NxRxWxS
(4.5x60x15x1.5)
7

6
n�w�
l
�
e
5

3
none p�o�
ly
2 nwell
poly
1
metal1
0
0 1 2 3 4 5 6
m�e�t�
l1
�
a
Frequncy (GHz)

P�G�
S� �:��P�o �l�
y� �>� �
N�w�e�l�
1
ta
M
e
o
n
>
l�

70
ECEN-474-2009 Layout Split 3 Jose Silva-Martinez

GS (Ground Shield) type

none
Q-factor

poly PGS(wide)

71
ECEN-474-2009 Layout Split 4 Jose Silva-Martinez

Metal Stack
9

8
Q-factor
NxRxWxS
7 (4.5x60x15x1.5)

5
M�
6
�
4

3 M��
/6
�
5
M6
2 M 5/6
M 4/5/6 M��
4�6
5
/�
1
M 3/4/5/6
0
0 1 2 3 4 5 6 M��
3�/�
6
/5
�
4
Frequncy (GHz)

" S�
t �a�
c�k ��
6>�
:M �
M�5�/�6� �>� �
M�4 �/�5�/�
5
4
/
3
M
>
�
6

72
 ECEN-474-2009 Jose Silva-Martinez

Chip microphotograph
Chip was fabricated in 0.35um
CMOS through MOSIS.

Total area 2mm×2mm.

It includes the monolithic PLL,

standalone prescaler, loop filter
and VCO, etc.

The chip was packaged in 48-

pin TPFQ.
Best student paper
award: Radio Frequency Keliu Shu1, Edgar Sánchez-Sinencio1, Jose
Intl Conference 2003 Silva-Martinez1, and Sherif H. K. Embabi2
1Texas A&M University
IEEE-JSSC-June 2003 2Texas Instruments
73
Next Time
• Table-Based (gm/ID) Design Examples

74