CSC 311 DIGITAL DESIGN AND MICROPROCESSORS

❖ Course Outline
Introduction to microprocessor architecture-systems operations and interfacing, Encoders, decoders and
multiplexers. Registers and counters. Arithmetic circuits: binary adders-parallel and serial adders; full and
half adders, binary substractors - full and half subtractors, At least 16 or 32-bit microprocessor (Architecture
and instruction set). Microcomputer interfacing, microcomputer-based A-D and D-A converters. Design,
construction, programming and testing of microprocessors control systems.

1.0 Microprocessor
A microprocessor is a computer processor where the data processing logic and control is included on a single
integrated circuit (IC), or a small number of ICs. The microprocessor contains the arithmetic, logic, and
control circuitry required to perform the functions of a computer's central processing unit (CPU). The
microprocessor is a multipurpose, clock- driven, register-based, digital integrated circuit that accepts binary
data as input, processes it according to instructions stored in its memory, and provides results (also in binary
form) as output. Microprocessors contain both combinational logic and sequential digital logic, and operate
on numbers and symbols represented in the binary number system.

1.1 Microprocessor - Overview

Microprocessor is a controlling unit of a micro-computer, fabricated on a small chip capable of performing
ALU (Arithmetic Logical Unit) operations and communicating with the other devices connected to it.
Microprocessor consists of an ALU, register array, and a control unit. ALU performs arithmetical and logical
operations on the data received from the memory or an input device. Register array consists of registers
identified by letters like B, C, D, E, H, L and accumulator. The control unit controls the flow of data and
instructions within the computer.
Arithmetic and Logic Unit: In this area of the microprocessor, computing functions are performed on data.
The CPU performs arithmetic operations such as addition and subtraction, and logic operations such as AND,
OR, and exclusive OR. Results are stored either in register or in memory or sent to output devices.

Register Unit: This area of the microprocessor consists of various registers. The register is used primarily
to store data temporarily during the executing of a program. Some of the registers are accessible to the user
through instructions.

Control Unit: The control unit provides the necessary timing and control signals to all the operations in the
microcomputer. It controls the flow of data between the microprocessor and peripherals (including memory).

In figure 1.0 is the basic diagram of a microprocessor comprises of the input, microprocessor (ALU, register
& control unit), memory and the output.
Fig 1.0 Block Diagram of a Basic Microcomputer

1.1.1 How does a Microprocessor Work?

The microprocessor follows a sequence: Fetch, Decode, and then Execute.
Initially, the instructions are stored in the memory in a sequential order. The microprocessor fetches those
instructions from the memory, then decodes it and executes those instructions till STOP instruction is reached.
Later, it sends the result in binary to the output port. Between these processes, the register stores the
temporarily data and ALU performs the computing functions.

1.1.2 List of Terms Used in a Microprocessor

Here is a list of some of the frequently used terms in a microprocessor −
• Instruction Set − It is the set of instructions that the microprocessor can understand.
• Bandwidth − It is the number of bits processed in a single instruction.
• Clock Speed − It determines the number of operations per second the processor can perform.
It is expressed in megahertz (MHz) or gigahertz (GHz).It is also known as Clock Rate.
• Word Length − It depends upon the width of internal data bus, registers, ALU, etc. An 8-bit
microprocessor can process 8-bit data at a time. The word length ranges from 4 bits to 64 bits
depending upon the type of the microcomputer.
• Data Types − The microprocessor has multiple data type formats like binary, BCD, ASCII,
signed and unsigned numbers.

1.1.3 Features of a Microprocessor

Here is a list of some of the most prominent features of any microprocessor −
• Cost-effective − The microprocessor chips are available at low prices and results its low cost.
• Size − The microprocessor is of small size chip, hence is portable.
• Low Power Consumption − Microprocessors are manufactured by using metaloxide
semiconductor technology, which has low power consumption.
• Versatility − The microprocessors are versatile as we can use the same chip in a number of
applications by configuring the software program.
• Reliability − The failure rate of an IC in microprocessors is very low, hence it is reliable.
1.2 Microprocessor - Classification
A microprocessor can be classified into three categories as shown in figure 1.1

Fig. 1.1 Classification of microprocessor

1.2.1 RISC Processor

RISC stands for Reduced Instruction Set Computer. It is designed to reduce the execution time by
simplifying the instruction set of the computer. Using RISC processors, each instruction requires only one
clock cycle to execute results in uniform execution time. This reduces the efficiency as there are more lines
of code, hence more RAM is needed to store the instructions. The compiler also has to work more to convert
high-level language instructions into machine code.
Some of the RISC processors are −
• Power PC: 601, 604, 615, 620
• DEC Alpha: 210642, 211066, 21068, 21164
• MIPS: TS (R10000) RISC Processor
• PA-RISC: HP 7100LC

1.2.2 Architecture of RISC

RISC microprocessor architecture uses highly-optimized set of instructions. It is used in portable devices like
Apple iPod due to its power efficiency. The diagram in figure 1.2 shows the structural flow of the RISC

Fig. 1.2 RISC Architecture

1.2.3 Characteristics of RISC

The major characteristics of a RISC processor are as follows −
 • It consists of simple instructions.
• It supports various data-type formats.
• It utilizes simple addressing modes and fixed length instructions for pipelining.
• It supports register to use in any context.
• One cycle execution time.
• “LOAD” and “STORE” instructions are used to access the memory location.
• It consists of larger number of registers.
• It consists of less number of transistors.

1.3.0 CISC Processor

CISC stands for Complex Instruction Set Computer. It is designed to minimize the number of instructions
per program, ignoring the number of cycles per instruction. The emphasis is on building complex instructions
directly into the hardware.
The compiler has to do very little work to translate a high-level language into assembly level
language/machine code because the length of the code is relatively short, so very little RAM is required to
store the instructions.
Some of the CISC Processors are −
• IBM 370/168
• VAX 11/780
• Intel 80486

1.3.1 Architecture of CISC

Its architecture is designed to decrease the memory cost because more storage is needed in larger programs
resulting in higher memory cost. To resolve this, the number of instructions per program can be reduced by
embedding the number of operations in a single instruction, see figure 1.3.

Fig. 1.3 CISC architecture

1.3.2 Characteristics of CISC
• Variety of addressing modes.
• Larger number of instructions.
 • Variable length of instruction formats.
• Several cycles may be required to execute one instruction.
• Instruction-decoding logic is complex.
• One instruction is required to support multiple addressing modes.

2.0 Special Processors

These are the processors which are designed for some special purposes. Few of the special processors are
briefly discussed –

2.1 Coprocessor
A coprocessor is a specially designed microprocessor, which can handle its particular function many times
faster than the ordinary microprocessor.
For example − Math Coprocessor.
Some Intel math-coprocessors are −
• 8087-used with 8086
• 80287-used with 80286
• 80387-used with 80386

2.1.1 Input/Output Processor

It is a specially designed microprocessor having a local memory of its own, which is used to control I/O
devices with minimum CPU involvement.
For example −
• DMA (direct Memory Access) controller
• Keyboard/mouse controller
• Graphic display controller
• SCSI port controller

2.1.2 Transputer (Transistor Computer)

A transputer is a specially designed microprocessor with its own local memory and having links to connect
one transputer to another transputer for inter-processor communications. It was first designed in 1980 by
Inmos and is targeted to the utilization of VLSI technology.
A transputer can be used as a single processor system or can be connected to external links, which reduces
the construction cost and increases the performance.
For example − 16-bit T212, 32-bit T425, the floating point (T800, T805 & T9000) processors.
2.1.3 DSP (Digital Signal Processor)
This processor is specially designed to process the analog signals into a digital form. This is done by sampling
the voltage level at regular time intervals and converting the voltage at that instant into a digital form. This
process is performed by a circuit called an analogue to digital converter, A to D converter or ADC.
A DSP contains the following components −
• Program Memory − It stores the programs that DSP will use to process data.
• Data Memory − It stores the information to be processed.
• Compute Engine − It performs the mathematical processing, accessing the program from the
program memory and the data from the data memory.
• Input/Output − It connects to the outside world.
Its applications are −
• Sound and music synthesis
• Audio and video compression
• Video signal processing
• 2D and 3d graphics acceleration.
For example − Texas Instrument’s TMS 320 series, e.g., TMS 320C40, TMS320C50.

2.2 Various Microprocessor Operations and Interface

The Microprocessor Unit (MPU) performs the following operations with other parts of the computer to
compute arithmetic and logic functions to handle task using an instruction set to execute all tasks within a
computer.
I. Input/output: Microprocessor accepts input from devices, such as a mouse, keyboard or scanner,
and executes a function on that data. It makes a decision based on the data, the microprocessor
computes the information, and then it sends the results to the output devices, such as a monitor or
printer, as readable information for the user. For example, if a user using a word processor presses
"v" on the keyboard, the microprocessor will accept that and send the letter "v" to the monitor.
II. The arithmetic logic unit: Gathers information as input from the CPU registers and operands
and then does the arithmetic operations (addition, subtraction, multiplication and division) and
logic operations (AND, OR and XOR). During data processing, the ALU tests conditions and
prepares to take different actions based on results. The ALU also gathers data from additional
sources, including number systems, instructions, timing and data routing circuits, such as adders
and subtracters.
III. Memory: The microprocessor accesses and stores binary instructions into memory, or circuits
that store bits. Random access memory is a control memory that uses registers to temporarily
store data. The microprocessor stores volatile data used by programs in RAM. Read only
memory stores data permanently on chips with instructions built in. It takes longer to access the
information in ROM, but it does not lose information when a computer shuts down as it does in RAM
(lost data when the computer is turned off).
IV. The control unit: Directs the flow of operations and data by selecting one program statement
at a time, interpreting it, and sending messages to the ALU or registers to carry out the
instruction. It also decides where to keep information in memory and which devices to
 communicate with by interfacing with the ALU, memory and input/output devices. The control
unit can also shut down a computer if it or another device, such as the power source, detects
abnormal conditions.
V. Information Exchange: The system bus connects the microprocessor to the peripherals, such
as a keyboard, mouse, printer, scanner, speaker or digital camera. The microprocessor sends and
receives data through the system bus to communicate with the peripherals. It only communicates
with one peripheral at a time to not mix up any information and send it to the wrong place. The
control unit controls the timing of the information exchange.

2.3 However, based on size of data bus, microprocessors are grouped as follows:

I. 4-bit microprocessor
II. 8-bit microprocessor
III. 16-bit microprocessor
IV. 32-bit microprocessor

2.4 Interface Techniques in Microprocessor

Interfacing is the mating of one component in a system to another to form a totally operational unit. Since a
microprocessor standing alone is essentially useless, extensive interfacing is required to build a usable
system.
Microprocessor systems vary in size and configuration. With present microprocessor it is possible to build a
complete system from just one Lager Scale Integration (LSI) chip and a few discrete parts, but the most
common microcomputer systems consist of considerably more. A microprocessor chip, memory chips, and
a few 1/0 interfaces are usually included.

In figure 2.0, the interfaces have been broken into four basic categories: operational overhead, user-
interaction, sensory, and control.

Operational overhead interfaces: are those interface components necessary to make a processor function on
the most basic level. This class includes data and address bus drivers, bus receivers, and the clock circuit surrounding
the microprocessor. Larger interface items such as those for memory and data storage devices would also fall into this
category.
User-interaction interfaces: are those circuits required to send and receive user specified data to and
from a processing system. This interface class includes computer terminal interfaces, keyboard
interfaces, graphic-device interfaces, and voice recognition and synthesis interfaces.
Sensor interface: When dealing with strict scientific computing or business data processing, a central
processing unit, operational overhead interfaces (including memory and disk interfaces), and a few user-
interaction interfaces for computer terminals and line printers are usually sufficient to accomplish the
task. Control systems are a different matter, however. Events in the real world must be monitored.
Sensory interfaces are those circuits required to monitor events in the real world and send the results to
a microprocessor system. Pressure sensor, thermal sensor, flow-rate indicator, and tachometer interfaces
are but a few of the interfaces that fall into this class.
 Fig. 2.0 Typical Microprocessor and its interfaces

Control interface: Once the sensor provides the status and the microcomputer decides what action is to be
taken, a control interface is usually needed to carry out the action. Control interfaces take a microcomputer's
milliampere-level data signals and convert them to the proper voltage and current levels to control real-
world devices. The circuitry needed to drive a stepping motor on a machine tool, to activate a solenoid-
controlled valve, control signal, or to illuminate a bank of stoplights falls into this interface category.

2.5 Microprocessor - I/O Interfacing Overview

In this chapter, we will discuss Memory Interfacing and IO Interfacing with 8085.
Interface is the path for communication between two components. Interfacing is of two types, memory
interfacing and I/O interfacing.

2.5.1 Memory Interfacing

When we are executing any instruction, we need the microprocessor to access the memory for reading
instruction codes and the data stored in the memory. For this, both the memory and the microprocessor
requires some signals to read from and write to registers.
The interfacing process includes some key factors to match with the memory requirements and
microprocessor signals. The interfacing circuit therefore should be designed in such a way that it matches
the memory signal requirements with the signals of the microprocessor.
2.5.2 IO Interfacing
There are various communication devices like the keyboard, mouse, printer, etc. So, we need to interface the
keyboard and other devices with the microprocessor by using latches and buffers. This type of interfacing is
known as I/O interfacing.

Fig. 2.1 Block Diagram of Memory and I/O Interfacing

2.5.3 8085 Interfacing Pins

Following is the list of 8085 pins used for interfacing with other devices −
• A15 - A8 (Higher Address Bus)
• AD7 - AD0(Lower Address/Data Bus)
• ALE
• RD
• WR
• READY

2.6 Ways of Communication − Microprocessor with the Outside World?

There are two ways of communication in which the microprocessor can connect with the outside world.
• Serial Communication Interface
• Parallel Communication interface
Serial Communication Interface − In this type of communication, the interface gets a single byte of data
from the microprocessor and sends it bit by bit to the other system serially and vice-a-versa.
Parallel Communication Interface − In this type of communication, the interface gets a byte of data from
the microprocessor and sends it bit by bit to the other systems in simultaneous (or) parallel fashion and vice-
a-versa.

3.0 Microprocessor - 8086 Overview

8086 Microprocessor is an enhanced version of 8085Microprocessor that was designed by Intel in 1976. It
is a 16-bit Microprocessor having 20 address lines and16 data lines that provides up to 1MB storage, see
figure 2.2. It consists of powerful instruction set, which provides operations like multiplication and division
easily.

Fig. 3.0 8086 microprocessor

It supports two modes of operation, i.e. Maximum mode and Minimum mode. Maximum mode is suitable
for system having multiple processors and Minimum mode is suitable for system having a single processor.

3.1 Features of 8086

The most prominent features of a 8086 microprocessor are as follows −
• It has an instruction queue, which is capable of storing six instruction bytes from the memory
resulting in faster processing.
• It was the first 16-bit processor having 16-bit ALU, 16-bit registers, internal data bus, and 16-
bit external data bus resulting in faster processing.
• It is available in 3 versions based on the frequency of operation −
o 8086 → 5MHz
o 8086-2 → 8MHz
o (c)8086-1 → 10 MHz
• It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage, which improves
performance.
• Fetch stage can prefetch up to 6 bytes of instructions and stores them in the queue.
• Execute stage executes these instructions.
• It has 256 vectored interrupts.
• It consists of 29,000 transistors.
•

3..1.1 Comparison between 8085 & 8086 Microprocessor

• Size − 8085 is 8-bit microprocessor, whereas 8086 is 16-bit microprocessor.
 • Address Bus − 8085 has 16-bit address bus while 8086 has 20-bit address bus.
• Memory − 8085 can access up to 64Kb, whereas 8086 can access up to 1 Mb of memory.
• Instruction − 8085 doesn’t have an instruction queue, whereas 8086 has an instruction queue.
• Pipelining − 8085 doesn’t support a pipelined architecture while 8086 supports a pipelined
architecture.
• I/O − 8085 can address 2^8 = 256 I/O's, whereas 8086 can access 2^16 = 65,536 I/O's.
• Cost − The cost of 8085 is low whereas that of 8086 is high.

3.2 8086 Microprocessor Architecture and Operation.

It is a 16 bit processor. It has a 20 bit address bus can access upto 220 memory location (1 MB). It can
support up to 64K I/O ports. It provides 14, 16-bit registers. It has multiplexed address and data bus AD0-
AD15 and A16 – A19. It requires single phase clock with 33% duty cycle to provide internal timing. 8086
is designed to operate in two modes, Minimum and Maximum. It can prefetches up to 6 instruction bytes
from memory and queues them in order to speed up instruction execution. It requires +5V power supply.
A 40 pin dual in line package.

3.2.1 Minimum and Maximum Modes

The minimum mode is selected by applying logic 1 to the MN / MX# input pin. This is a single
microprocessor configuration. The maximum mode is selected by applying logic 0 to the MN / MX#
input pin. This is a multi-microprocessors configuration.

3.3 Architecture of 8086

The diagram below depicts the architecture of a 8086 Microprocessor −

3.3.1 Microprocessor - 8086 Functional Units

8086 Microprocessor is divided into two functional units, i.e., EU (Execution Unit) and BIU (Bus Interface
Unit).
EU (Execution Unit)
Execution unit gives instructions to BIU stating from where to fetch the data and then decode and execute
those instructions. Its function is to control operations on data using the instruction decoder & ALU. EU has
no direct connection with system buses as shown in the above figure, it performs operations over data through
BIU.
Let us now discuss the functional parts of 8086 microprocessors.
ALU
It handles all arithmetic and logical operations, like +, −, ×, /, OR, AND, NOT operations.
Flag Register
It is a 16-bit register that behaves like a flip-flop, i.e. it changes its status according to the result stored in the
accumulator. It has 9 flags and they are divided into 2 groups − Conditional Flags and Control Flags.
Conditional Flags
It represents the result of the last arithmetic or logical instruction executed. Following is the list of conditional
flags −
• Carry flag − This flag indicates an overflow condition for arithmetic operations.
• Auxiliary flag − When an operation is performed at ALU, it results in a carry/barrow from
lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), then this flag is set, i.e. carry given
by D3 bit to D4 is AF flag. The processor uses this flag to perform binary to BCD conversion.
• Parity flag − This flag is used to indicate the parity of the result, i.e. when the lower order 8-
bits of the result contains even number of 1’s, then the Parity Flag is set. For odd number of
1’s, the Parity Flag is reset.
• Zero flag − This flag is set to 1 when the result of arithmetic or logical operation is zero else
it is set to 0.
• Sign flag − This flag holds the sign of the result, i.e. when the result of the operation is
negative, then the sign flag is set to 1 else set to 0.
• Overflow flag − This flag represents the result when the system capacity is exceeded.
Control Flags
Control flags controls the operations of the execution unit. Following is the list of control flags −
• Trap flag − It is used for single step control and allows the user to execute one instruction at
a time for debugging. If it is set, then the program can be run in a single step mode.
• Interrupt flag − It is an interrupt enable/disable flag, i.e. used to allow/prohibit the
interruption of a program. It is set to 1 for interrupt enabled condition and set to 0 for interrupt
disabled condition.
• Direction flag − It is used in string operation. As the name suggests when it is set then string
bytes are accessed from the higher memory address to the lower memory address and vice-a-
versa.
General purpose register
There are 8 general purpose registers, i.e., AH, AL, BH, BL, CH, CL, DH, and DL. These registers can be
used individually to store 8-bit data and can be used in pairs to store 16bit data. The valid register pairs are
AH and AL, BH and BL, CH and CL, and DH and DL. It is referred to the AX, BX, CX, and DX respectively.
• AX register − It is also known as accumulator register. It is used to store operands for
arithmetic operations.
• BX register − It is used as a base register. It is used to store the starting base address of the
memory area within the data segment.
• CX register − It is referred to as counter. It is used in loop instruction to store the loop counter.
• DX register − This register is used to hold I/O port address for I/O instruction.
Stack pointer register
It is a 16-bit register, which holds the address from the start of the segment to the memory location, where a
word was most recently stored on the stack.

BIU (Bus Interface Unit)

BIU takes care of all data and addresses transfers on the buses for the EU like sending addresses, fetching
instructions from the memory, reading data from the ports and the memory as well as writing data to the
ports and the memory. EU has no direction connection with System Buses so this is possible with the BIU.
EU and BIU are connected with the Internal Bus.
It has the following functional parts −
• Instruction queue − BIU contains the instruction queue. BIU gets upto 6 bytes of next
instructions and stores them in the instruction queue. When EU executes instructions and is
ready for its next instruction, then it simply reads the instruction from this instruction queue
resulting in increased execution speed.
• Fetching the next instruction while the current instruction executes is called pipelining.
• Segment register − BIU has 4 segment buses, i.e. CS, DS, SS& ES. It holds the addresses of
instructions and data in memory, which are used by the processor to access memory locations.
It also contains 1 pointer register IP, which holds the address of the next instruction to executed
by the EU.
o CS − It stands for Code Segment. It is used for addressing a memory location
in the code segment of the memory, where the executable program is stored.
o DS − It stands for Data Segment. It consists of data used by the program andis
accessed in the data segment by an offset address or the content of other register
that holds the offset address.
o SS − It stands for Stack Segment. It handles memory to store data and addresses
during execution.
o ES − It stands for Extra Segment. ES is additional data segment, which is used
by the string to hold the extra destination data.
• Instruction pointer − It is a 16-bit register used to hold the address of the next instruction to
be executed.
3.4 Microprocessor - 8086 Pin Configuration
8086 was the first 16-bit microprocessor available in 40-pin DIP (Dual Inline Package) chip as displayed in
figure 3.1. Let us now discuss in detail the pin configuration of a 8086 Microprocessor.

Fig. 3.1 8086 Pin Diagram

Let us now discuss the signals in detail;

Power supply and frequency signals
It uses 5V DC supply at VCC pin 40, and uses ground at VSS pin 1 and 20 for its operation.
Clock signal
Clock signal is provided through Pin-19. It provides timing to the processor for operations. Its frequency is
different for different versions, i.e. 5MHz, 8MHz and 10MHz.
Address/data bus
AD0-AD15. These are 16 address/data bus. AD0-AD7 carries low order byte data and AD8AD15 carries
higher order byte data. During the first clock cycle, it carries 16-bit address and after that it carries 16-bit
data.
Address/status bus
A16-A19/S3-S6. These are the 4 address/status buses. During the first clock cycle, it carries 4-bit address
and later it carries status signals.
S7/BHE
BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the transfer of data using data
bus D8-D15. This signal is low during the first clock cycle, thereafter it is active.
Read($\overline{RD}$)
It is available at pin 32 and is used to read signal for Read operation.
Ready
It is available at pin 22. It is an acknowledgement signal from I/O devices that data is transferred. It is an
active high signal. When it is high, it indicates that the device is ready to transfer data. When it is low, it
indicates wait state.
RESET
It is available at pin 21 and is used to restart the execution. It causes the processor to immediately terminate
its present activity. This signal is active high for the first 4 clock cycles to RESET the microprocessor.
INTR
It is available at pin 18. It is an interrupt request signal, which is sampled during the last clock cycle of each
instruction to determine if the processor considered this as an interrupt or not.
NMI
It stands for non-maskable interrupt and is available at pin 17. It is an edge triggered input, which causes an
interrupt request to the microprocessor.
$\overline{TEST}$
This signal is like wait state and is available at pin 23. When this signal is high, then the processor has to
wait for IDLE state, else the execution continues.
MN/$\overline{MX}$
It stands for Minimum/Maximum and is available at pin 33. It indicates what mode the processor is to operate
in; when it is high, it works in the minimum mode and vice-aversa.
INTA
It is an interrupt acknowledgement signal and id available at pin 24. When the microprocessor receives this
signal, it acknowledges the interrupt.
ALE
It stands for address enable latch and is available at pin 25. A positive pulse is generated each time the
processor begins any operation. This signal indicates the availability of a valid address on the address/data
lines.
DEN
It stands for Data Enable and is available at pin 26. It is used to enable Transreceiver 8286. The transreceiver
is a device used to separate data from the address/data bus.
DT/R
It stands for Data Transmit/Receive signal and is available at pin 27. It decides the direction of data flow
through the transreceiver. When it is high, data is transmitted out and vice-a-versa.
M/IO
This signal is used to distinguish between memory and I/O operations. When it is high, it indicates I/O
operation and when it is low indicates the memory operation. It is available at pin 28.
WR
It stands for write signal and is available at pin 29. It is used to write the data into the memory or the output
device depending on the status of M/IO signal.
HLDA
It stands for Hold Acknowledgement signal and is available at pin 30. This signal acknowledges the HOLD
signal.
HOLD
This signal indicates to the processor that external devices are requesting to access the address/data buses. It
is available at pin 31.
QS1 and QS0
These are queue status signals and are available at pin 24 and 25. These signals provide the status of
instruction queue. Their conditions are shown in the table below;

QS0 QS1 Status

0 0 No operation

0 1 First byte of opcode from the queue

1 0 Empty the queue

1 1 Subsequent byte from the queue

S0, S1, S2
These are the status signals that provide the status of operation, which is used by the Bus Controller 8288 to
generate memory & I/O control signals. These are available at pin 26, 27, and 28. Following is the table
below, showing their status −
 S2 S1 S0 Status

0 0 0 Interrupt acknowledgement

0 0 1 I/O Read

0 1 0 I/O Write

0 1 1 Halt

1 0 0 Opcode fetch

1 0 1 Memory read

1 1 0 Memory write

1 1 1 Passive

LOCK
When this signal is active, it indicates to the other processors not to ask the CPU to leave the system bus. It
is activated using the LOCK prefix on any instruction and is available at pin 29.
RQ/GT1 and RQ/GT0
These are the Request/Grant signals used by the other processors requesting the CPU to release the system
bus. When the signal is received by CPU, then it sends acknowledgment. RQ/GT0 has a higher priority than
RQ/GT1.

3.5 Microprocessor - 8086 Instruction Sets

The 8086 microprocessor supports 8 types of instructions −
• Data Transfer Instructions
• Arithmetic Instructions
• Bit Manipulation Instructions
• String Instructions
• Program Execution Transfer Instructions (Branch & Loop Instructions)
• Processor Control Instructions
• Iteration Control Instructions
• Interrupt Instructions
Let us now discuss these instruction sets in detail.
3.5.1 Data Transfer Instructions
These instructions are used to transfer the data from the source operand to the destination operand. Following
are the list of instructions under this group −
Instruction to transfer a word
• MOV − Used to copy the byte or word from the provided source to the provided destination.
• PPUSH − Used to put a word at the top of the stack.
• POP − Used to get a word from the top of the stack to the provided location.
• PUSHA − Used to put all the registers into the stack.
• POPA − Used to get words from the stack to all registers.
• XCHG − Used to exchange the data from two locations.
• XLAT − Used to translate a byte in AL using a table in the memory.
Instructions for input and output port transfer
• IN − Used to read a byte or word from the provided port to the accumulator.
• OUT − Used to send out a byte or word from the accumulator to the provided port.
Instructions to transfer the address
• LEA − Used to load the address of operand into the provided register.
• LDS − Used to load DS register and other provided register from the memory
• LES − Used to load ES register and other provided register from the memory.
Instructions to transfer flag registers
• LAHF − Used to load AH with the low byte of the flag register.
• SAHF − Used to store AH register to low byte of the flag register.
• PUSHF − Used to copy the flag register at the top of the stack.
• POPF − Used to copy a word at the top of the stack to the flag register.

3.5.2 Arithmetic Instructions

These instructions are used to perform arithmetic operations like addition, subtraction, multiplication,
division, etc.
Following is the list of instructions under this group −
Instructions to perform addition
• ADD − Used to add the provided byte to byte/word to word.
• ADC − Used to add with carry.
• INC − Used to increment the provided byte/word by 1.
• AAA − Used to adjust ASCII after addition.
• DAA − Used to adjust the decimal after the addition/subtraction operation.
Instructions to perform subtraction
• SUB − Used to subtract the byte from byte/word from word.
• SBB − Used to perform subtraction with borrow.
• DEC − Used to decrement the provided byte/word by 1.
• NPG − Used to negate each bit of the provided byte/word and add 1/2’s complement.
• CMP − Used to compare 2 provided byte/word.
• AAS − Used to adjust ASCII codes after subtraction.
 • DAS − Used to adjust decimal after subtraction.
Instruction to perform multiplication
• MUL − Used to multiply unsigned byte by byte/word by word.
• IMUL − Used to multiply signed byte by byte/word by word.
• AAM − Used to adjust ASCII codes after multiplication.
Instructions to perform division
• DIV − Used to divide the unsigned word by byte or unsigned double word by word.
• IDIV − Used to divide the signed word by byte or signed double word by word.
• AAD − Used to adjust ASCII codes after division.
• CBW − Used to fill the upper byte of the word with the copies of sign bit of the lower byte.
• CWD − Used to fill the upper word of the double word with the sign bit of the lower word.

3.5.3 Bit Manipulation Instructions

These instructions are used to perform operations where data bits are involved, i.e. operations like logical,
shift, etc.
Following is the list of instructions under this group −
Instructions to perform logical operation
• NOT − Used to invert each bit of a byte or word.
• AND − Used for adding each bit in a byte/word with the corresponding bit in another
byte/word.
• OR − Used to multiply each bit in a byte/word with the corresponding bit in another
byte/word.
• XOR − Used to perform Exclusive-OR operation over each bit in a byte/word with the
corresponding bit in another byte/word.
• TEST − Used to add operands to update flags, without affecting operands.
Instructions to perform shift operations
• SHL/SAL − Used to shift bits of a byte/word towards left and put zero(S) in LSBs.
• SHR − Used to shift bits of a byte/word towards the right and put zero(S) in MSBs.
• SAR − Used to shift bits of a byte/word towards the right and copy the old MSB into the new
MSB.
Instructions to perform rotate operations
• ROL − Used to rotate bits of byte/word towards the left, i.e. MSB to LSB and to Carry Flag
[CF].
• ROR − Used to rotate bits of byte/word towards the right, i.e. LSB to MSB and to Carry Flag
[CF].
• RCR − Used to rotate bits of byte/word towards the right, i.e. LSB to CF and CF to MSB.
• RCL − Used to rotate bits of byte/word towards the left, i.e. MSB to CF and CF to LSB.

3.5.4 String Instructions

String is a group of bytes/words and their memory is always allocated in a sequential order.
Following is the list of instructions under this group −
• REP − Used to repeat the given instruction till CX ≠ 0.
 • REPE/REPZ − Used to repeat the given instruction until CX = 0 or zero flag ZF = 1.
• REPNE/REPNZ − Used to repeat the given instruction until CX = 0 or zero flag ZF = 1.
• MOVS/MOVSB/MOVSW − Used to move the byte/word from one string to another.
• COMS/COMPSB/COMPSW − Used to compare two string bytes/words.
• INS/INSB/INSW − Used as an input string/byte/word from the I/O port to the provided
memory location.
• OUTS/OUTSB/OUTSW − Used as an output string/byte/word from the provided memory
location to the I/O port.
• SCAS/SCASB/SCASW − Used to scan a string and compare its byte with a byte in AL or
string word with a word in AX.
• LODS/LODSB/LODSW − Used to store the string byte into AL or string word into AX.

3.5.5 Program Execution Transfer Instructions (Branch and Loop Instructions)

These instructions are used to transfer/branch the instructions during an execution. It includes the following
instructions −
Instructions to transfer the instruction during an execution without any condition −
• CALL − Used to call a procedure and save their return address to the stack.
• RET − Used to return from the procedure to the main program.
• JMP − Used to jump to the provided address to proceed to the next instruction.
Instructions to transfer the instruction during an execution with some conditions −
• JA/JNBE − Used to jump if above/not below/equal instruction satisfies.
• JAE/JNB − Used to jump if above/not below instruction satisfies.
• JBE/JNA − Used to jump if below/equal/ not above instruction satisfies.
• JC − Used to jump if carry flag CF = 1
• JE/JZ − Used to jump if equal/zero flag ZF = 1
• JG/JNLE − Used to jump if greater/not less than/equal instruction satisfies.
• JGE/JNL − Used to jump if greater than/equal/not less than instruction satisfies.
• JL/JNGE − Used to jump if less than/not greater than/equal instruction satisfies.
• JLE/JNG − Used to jump if less than/equal/if not greater than instruction satisfies.
• JNC − Used to jump if no carry flag (CF = 0)
• JNE/JNZ − Used to jump if not equal/zero flag ZF = 0
• JNO − Used to jump if no overflow flag OF = 0
• JNP/JPO − Used to jump if not parity/parity odd PF = 0
• JNS − Used to jump if not sign SF = 0
• JO − Used to jump if overflow flag OF = 1
• JP/JPE − Used to jump if parity/parity even PF = 1
• JS − Used to jump if sign flag SF = 1

3.5.6 Processor Control Instructions

These instructions are used to control the processor action by setting/resetting the flag values.
Following are the instructions under this group −
 • STC − Used to set carry flag CF to 1
• CLC − Used to clear/reset carry flag CF to 0
• CMC − Used to put complement at the state of carry flag CF.
• STD − Used to set the direction flag DF to 1
• CLD − Used to clear/reset the direction flag DF to 0
• STI − Used to set the interrupt enable flag to 1, i.e., enable INTR input.
• CLI − Used to clear the interrupt enable flag to 0, i.e., disable INTR input.

3.5.7 Iteration Control Instructions

These instructions are used to execute the given instructions for number of times. Following is the list of
instructions under this group −
• LOOP − Used to loop a group of instructions until the condition satisfies, i.e., CX = 0
• LOOPE/LOOPZ − Used to loop a group of instructions till it satisfies ZF = 1 & CX = 0
• LOOPNE/LOOPNZ − Used to loop a group of instructions till it satisfies ZF = 0 & CX = 0
• JCXZ − Used to jump to the provided address if CX = 0

Interrupt Instructions
These instructions are used to call the interrupt during program execution.
• INT − Used to interrupt the program during execution and calling service specified.
• INTO − Used to interrupt the program during execution if OF = 1
• IRET − Used to return from interrupt service to the main program

3.6.0 Microprocessor - 8086 Interrupts

Interrupt is the method of creating a temporary halt during program execution and allows peripheral devices
to access the microprocessor. The microprocessor responds to that interrupt with an ISR (Interrupt Service
Routine), which is a short program to instruct the microprocessor on how to handle the interrupt.
The image in figure 3.2 shows the types of interrupts we have in a 8086 microprocessor −
Fig. 3.2 Types of Interrupts in 8086 Microprocessor

3.6.1 Hardware Interrupts

Hardware interrupt is caused by any peripheral device by sending a signal through a specified pin to the
microprocessor.
The 8086 has two hardware interrupt pins, i.e. NMI and INTR. NMI is a non-maskable interrupt and INTR is
a maskable interrupt having lower priority. One more interrupt pin associated is INTA called interrupt
acknowledge.
NMI
It is a single non-maskable interrupt pin (NMI) having higher priority than the maskable interrupt request pin
(INTR)and it is of type 2 interrupt.
When this interrupt is activated, these actions take place −
• Completes the current instruction that is in progress.
• Pushes the Flag register values on to the stack.
• Pushes the CS (code segment) value and IP (instruction pointer) value of the return address on
to the stack.
• IP is loaded from the contents of the word location 00008H.
• CS is loaded from the contents of the next word location 0000AH.
• Interrupt flag and trap flag are reset to 0.
INTR
The INTR is a maskable interrupt because the microprocessor will be interrupted only if interrupts are enabled
using set interrupt flag instruction. It should not be enabled using clear interrupt Flag instruction.
The INTR interrupt is activated by an I/O port. If the interrupt is enabled and NMI is disabled, then the
microprocessor first completes the current execution and sends ‘0’ on INTA pin twice. The first ‘0’ means
INTA informs the external device to get ready and during the second ‘0’ the microprocessor receives the 8
bit, say X, from the programmable interrupt controller.
These actions are taken by the microprocessor −
• First completes the current instruction.
• Activates INTA output and receives the interrupt type, say X.
• Flag register value, CS value of the return address and IP value of the return address are pushed
on to the stack.
• IP value is loaded from the contents of word location X × 4
• CS is loaded from the contents of the next word location.
• Interrupt flag and trap flag is reset to 0

3.6.2 Software Interrupts

Some instructions are inserted at the desired position into the program to create interrupts. These interrupt
instructions can be used to test the working of various interrupt handlers. It includes −
INT- Interrupt instruction with type number
It is 2-byte instruction. First byte provides the op-code and the second byte provides the interrupt type number.
There are 256 interrupt types under this group.
Its execution includes the following steps −
• Flag register value is pushed on to the stack.
• CS value of the return address and IP value of the return address are pushed on to the stack.
• IP is loaded from the contents of the word location ‘type number’ × 4
• CS is loaded from the contents of the next word location.
• Interrupt Flag and Trap Flag are reset to 0
The starting address for type0 interrupt is 000000H, for type1 interrupt is 00004H similarly for type2 is
00008H and ……so on. The first five pointers are dedicated interrupt pointers. i.e. −
• TYPE 0 interrupt represents division by zero situation.
• TYPE 1 interrupt represents single-step execution during the debugging of a program.
• TYPE 2 interrupt represents non-maskable NMI interrupt.
• TYPE 3 interrupt represents break-point interrupt.
• TYPE 4 interrupt represents overflow interrupt.
The interrupts from Type 5 to Type 31 are reserved for other advanced microprocessors, and interrupts from
32 to Type 255 are available for hardware and software interrupts.
INT 3-Break Point Interrupt Instruction
It is a 1-byte instruction having op-code is CCH. These instructions are inserted into the program so that when
the processor reaches there, then it stops the normal execution of program and follows the break-point
procedure.
Its execution includes the following steps −
• Flag register value is pushed on to the stack.
• CS value of the return address and IP value of the return address are pushed on to the stack.
• IP is loaded from the contents of the word location 3×4 = 0000CH
 • CS is loaded from the contents of the next word location.
• Interrupt Flag and Trap Flag are reset to 0
INTO - Interrupt on overflow instruction
It is a 1-byte instruction and their mnemonic INTO. The op-code for this instruction is CEH. As the name
suggests it is a conditional interrupt instruction, i.e. it is active only when the overflow flag is set to 1 and
branches to the interrupt handler whose interrupt type number is 4. If the overflow flag is reset then, the
execution continues to the next instruction.
Its execution includes the following steps −
• Flag register values are pushed on to the stack.
• CS value of the return address and IP value of the return address are pushed on to the stack.
• IP is loaded from the contents of word location 4×4 = 00010H
• CS is loaded from the contents of the next word location.
• Interrupt flag and Trap flag are reset to 0

3.7 Microprocessor - 8086 Addressing Modes

The different ways in which a source operand is denoted in an instruction is known as addressing modes.
There are 8 different addressing modes in 8086 programming which are –

3.7.1 Immediate addressing mode

The addressing mode in which the data operand is a part of the instruction itself is known as immediate
addressing mode.
Example
MOV CX, 4929 H, ADD AX, 2387 H, MOV AL, FFH

3.7.2 Register addressing mode

It means that the register is the source of an operand for an instruction.
Example
MOV CX, AX ; copies the contents of the 16-bit AX register into
; the 16-bit CX register),
ADD BX, AX

3.7.3 Direct addressing mode

The addressing mode in which the effective address of the memory location is written directly in the
instruction.
Example
MOV AX, [1592H], MOV AL, [0300H]
3.7.4 Register indirect addressing mode
This addressing mode allows data to be addressed at any memory location through an offset address held in
any of the following registers: BP, BX, DI & SI.
Example
MOV AX, [BX] ; Suppose the register BX contains 4895H, then the contents
; 4895H are moved to AX
ADD CX, {BX}

3.7.5 Based addressing mode

In this addressing mode, the offset address of the operand is given by the sum of contents of the BX/BP
registers and 8-bit/16-bit displacement.
Example
MOV DX, [BX+04], ADD CL, [BX+08]

3.7.6 Indexed addressing mode

In this addressing mode, the operands offset address is found by adding the contents of SI or DI register and
8-bit/16-bit displacements.
Example
MOV BX, [SI+16], ADD AL, [DI+16]

3.7.7 Based-index addressing mode

In this addressing mode, the offset address of the operand is computed by summing the base register to the
contents of an Index register.
Example
ADD CX, [AX+SI], MOV AX, [AX+DI]

3.7.8 Based indexed with displacement mode

In this addressing mode, the operands offset is computed by adding the base register contents. An Index
registers contents and 8 or 16-bit displacement.
Example
MOV AX, [BX+DI+08], ADD CX, [BX+SI+16]

4.0 Multiprocessor Configuration Overview

Multiprocessor means a multiple set of processors that executes instructions simultaneously. There are three
basic multiprocessor configurations.
• Coprocessor configuration
• Closely coupled configuration
• Loosely coupled configuration

4.1 Coprocessor Configuration

A Coprocessor is a specially designed circuit on microprocessor chip which can perform the same task very
quickly, which the microprocessor performs. It reduces the work load of the main processor. The coprocessor
shares the same memory, IO system, bus, control logic and clock generator. The coprocessor handles
specialized tasks like mathematical calculations, graphical display on screen, etc.
The 8086 and 8088 can perform most of the operations but their instruction set is not able to perform complex
mathematical operations, so in these cases the microprocessor requires the math coprocessor like Intel 8087
math coprocessor, which can easily perform these operations very quickly. The diagram as presented in figure
4.0.

Fig. 4.0 Block Diagram of Coprocessor Configuration

How is the coprocessor and the processor connected?

• The coprocessor and the processor is connected via TEST, RQ-/GT- and QS0 & QS1 signals.
• The TEST signal is connected to BUSY pin of coprocessor and the remaining 3 pins are
connected to the coprocessor’s 3 pins of the same name.
• TEST signal takes care of the coprocessor’s activity, i.e. the coprocessor is busy or idle.
• The RT-/GT-is used for bus arbitration.
• The coprocessor uses QS0 & QS1 to track the status of the queue of the host processor.

4.2 Closely Coupled Configuration

Closely coupled configuration is similar to the coprocessor configuration, i.e. both share the same memory,
I/O system bus, control logic, and control generator with the host processor as presented in figure 4.1.
However, the coprocessor and the host processor fetches and executes their own instructions. The system bus
is controlled by the coprocessor and the host processor independently.
Fig. 4.1 Block Diagram of Closely Coupled Configuration

How is the processor and the independent processor connected?

• Communication between the host and the independent processor is done through memory
space.
• None of the instructions are used for communication, like WAIT, ESC, etc.
• The host processor manages the memory and wakes up the independent processor by sending
commands to one of its ports.
• Then the independent processor accesses the memory to execute the task.
• After completion of the task, it sends an acknowledgement to the host processor by using the
status signal or an interrupt request.

4.3 Loosely Coupled Configuration

Fig. 4.2 Block Diagram of Loosely Coupled Configuration

Loosely coupled configuration consists of the number of modules of the microprocessor based systems, which
are connected through a common system bus. Each module consists of their own clock generator, memory,
I/O devices and are connected through a local bus.

Advantages
• Having more than one processor results in increased efficiency.
• Each of the processors have their own local bus to access the local memory/I/O devices. This
makes it easy to achieve parallel processing.
• The system structure is flexible, i.e. the failure of one module doesn’t affect the whole system
failure; faulty module can be replaced later.

5.0 Microcontrollers - Overview

A microcontroller is a small and low-cost microcomputer, which is designed to perform the specific tasks of
embedded systems like displaying microwave’s information, receiving remote signals, etc.
The general microcontroller consists of the processor, the memory (RAM, ROM, EPROM), Serial ports,
peripherals (timers, counters), etc.
Difference between Microprocessor and Microcontroller
The table below, highlights the differences between microprocessor and microcontroller −

Microcontroller Microprocessor

Microcontrollers are used to execute a single task Microprocessors are used for big
within an application. applications.

Its designing and hardware cost is low. Its designing and hardware cost is high.

Easy to replace. Not so easy to replace.

It is built with CMOS technology, which requires Its power consumption is high because it
less power to operate. has to control the entire system.

It consists of CPU, RAM, ROM, I/O ports. It doesn’t consist of RAM, ROM, I/O
ports. It uses its pins to interface to
peripheral devices.

5.1 Types of Microcontrollers

As earlier mentioned in session 2.3, microcontrollers can also be divided into various categories based on
memory, architecture, bits and instruction sets. Following is the detailed list and explanation of their types −
Bit
Based on bit configuration, the microcontroller is further divided into three categories.
• 8-bit microcontroller − This type of microcontroller is used to execute arithmetic and logical
operations like addition, subtraction, multiplication division, etc. For example, Intel 8031 and
8051 are 8 bits microcontroller.
• 16-bit microcontroller − This type of microcontroller is used to perform arithmetic and logical
operations where higher accuracy and performance is required. For example, Intel 8096 is a
16-bit microcontroller.
• 32-bit microcontroller − This type of microcontroller is generally used in automatically
controlled appliances like automatic operational machines, medical appliances, etc.
Memory
Based on the memory configuration, the microcontroller is further divided into two categories.
• External memory microcontroller − This type of microcontroller is designed in such a way
that they do not have a program memory on the chip. Hence, it is named as external memory
microcontroller. For example: Intel 8031 microcontroller.
• Embedded memory microcontroller − This type of microcontroller is designed in such a way
that the microcontroller has all programs and data memory, counters and timers, interrupts, I/O
ports are embedded on the chip. For example: Intel 8051 microcontroller.
Instruction Set
Based on the instruction set configuration, the microcontroller is further divided into two categories.
• CISC − CISC stands for complex instruction set computer. It allows the user to insert a single
instruction as an alternative to many simple instructions.
• RISC − RISC stands for Reduced Instruction Set Computers. It reduces the operational time
by shortening the clock cycle per instruction.

5.2 Applications of Microcontrollers

Microcontrollers are widely used in various different devices such as −
• Light sensing and controlling devices like LED.
• Temperature sensing and controlling devices like microwave oven, chimneys.
• Fire detection and safety devices like Fire alarm.
• Measuring devices like Volt Meter.

6.0 Register and Counters

A processor register is a quickly accessible location available to a computer processor. Registers usually
consist of a small amount of fast storage, although some registers have specific hardware functions and may
be read-only or write-only. In computer architecture, registers are typically addressed by mechanisms other
than main memory but may in some cases be assigned a memory address.
Processor registers are normally at the top of the memory hierarchy, and provide the fastest way to access
data. The term normally refers only to the group of registers that are directly encoded as part of an instruction
as defined by the instruction set. However, modern high- performance CPUs often have duplicates of these
architecture registers in order to improve performance via register renaming, allowing parallel and speculative
execution.

A processor often contains several kinds of registers which can be classified according to the types of values
they can store or instructions that operates on them:

• User-accessible registers can be read or written by machine instructions.

• Internal registers are not accessible by instructions and are used internally for processor operations
• Architecture registers are the registers visible to software and are defined by the architecture. They are not
corresponding to the physical hardware to always return zero when read (mostly to simply indexing
modes), and it cannot be overwritten.

There are several more registers in microprocessor such as floating-point register, general purpose register,
vector register and address registers.

6.1 Counters
Counters are essential to design advanced circuits which are found in digital computers. Counters are
employed to keep track of a sequence of events. Counters are particularly common in the control and
arithmetic units of processor.
Counters can count in two ways: up count it may count from (0, 1, 2 …….N). Example can be seen in
electronic voting machine and in shopping mail counting machine. The second is down count where it starts
from downward direction that may starts from (N, N-1….. 1, 0). Example are found in space related
application such as missile rocket launcher where they will start counting from a point downwards until it gets
to zero and they start launching.

Counters are used:

• To keep track of the sequence of instructions in a program
• To distribute the sequence of timing signals
• For frequency division for causing time delays
• For counting the number of pulses coming at the input
• For other similar operations.

Counters may count in binary or in non-binary fashion. The basic operational characteristics of a counter are
sequential, for every present state there is a well-defined next state. The design of a counter involves
designing combinational logic that decodes the present state and enables entry into the next state of the
counting sequence. Each state frequency (SF) is given as:
6.2 Counters are generally classified into two groups: synchronous and asynchronous

6.2.1 Synchronous counters

A synchronous counter has all Flip Flop (FFs) change state synchronously with the clock input
whether a periodic clock or a periodic plus occurs.
They are distinguished from asynchronous (ripple counter) counters in that the clock pubes in synchronous
counters initiate change in the FFs used in the counter. In synchronous counters, all the flip-flops changes
state simultaneously and they are capable of operating at higher frequencies. Synchronous counter are
generally more complicated and require more logical elements. The following divided-by-10 up counter is
an example of synchronous counter. Example can be found in 2-bit counts where you can use two flip flop
as shown in figure 6.0.

Fig. 6.0 2-bit counts

The flip-flop delay time and possibility of glitches are overcome by the use of a synchronous or parallel
counter. Every flip-flop is triggered in synchronism with the clock.
Synchronous counter is faster than the asynchronous counter.

6.2.2 An asynchronous counter

An asynchronous counter (Ripple Counter) is made up of FFs that do not change state simultaneously
with the clock input.
Asynchronous counter or ripple counter is a basic counter used very commonly because of its simplicity
where the clock input are not tied together. In ripple counter the output of each FF provides the clock signal
for the next FF. This type of counter is called asynchronous counter because all the FF in ripple counter do
not change states in exact synchronism with the clock pulses; only the first FF respond to the clock pulses.
The 2nd FF has to wait for the first; to change states before it is toggled (complemented), the third FF has to
wait for the 2nd and so on. So, there is a delay between the responses of consecutive FFs. Recall the following
points concerning its operation.
• All FFs are first cleared to the 0 state by applying 0 to the direct reset input.
• All T FFs inputs are connected to permanently to logical '1'. The clock pulses are applied only to
CK input of the first FF. As a result 1st FF will toggle (change to its opposite state) each time the clock pulses
make a regulative i.e. 0 transition.
• The least significant (1st) FF are activated by the system clock and the 1→0 transitions of that FF
may be used as clock input signal for the next most significant FF. i.e. The output of 1st FF acts the CK input
for 2nd FF and so 2nd FF will toggle each time the 1st FF output goes from 1 to 0. Similarly 3rd and 4th FF
will toggle when 1→0 transition occurs at 2nd FF and 3rd FF respectively. The state of the FF as incoming
pulse arrives are given in table 6.0

Table 6.0 Timing diagram

From the timing diagram, the frequency of Q4 pulse is the 1 /16 th of the frequency of input clock pulse.

Advantage of asynchronous counter

• Circuit design is easy
• Less Expensive
• Minimum number of FF is required, so cost is low
Disadvantage
• Slow speed of operation.
• Operating frequency is low.
• Undesirable decoding transient condition

7.0 Encoder and Decoder

Encoder and Decoder are combinations of logic circuits in digital electronics. A major difference between
these two terminologies is that the encoder gives the binary code as output whereas the decoder receives the
binary code. Let us explore the difference between encoder and decoder. An encoder is a mechanism that
can convert a data signal into a message that can be read by some kind of control device. Or in other words,
combinational circuits that modify binary data into N output lines are known as encoders. The combinational
circuit that converts binary data into 2N output lines is called a decoder.
7.1 What is an Encoder in digital electronics?

An encoder is a digital circuit that performs the reverse operation of a decoder. An encoder has 2 n input
lines and n output lines and the output lines produce binary code corresponding to the input value. An encoder
is a device, algorithm, that is a software program that converts the information from one format (code) to
another. The main purpose of the encoder is security, speed ,standardization or saving space by shrinking
size. They can be accepted one or more inputs and generates a multibit output code. Here this article gives
the application of encoder to better understand this topic.

The encoder is also a combinational logic circuit; it converts information, such as a decimal number or an
alphabetic character, into some coded form such as binary or Binary Code Decimal (BCD) or it performs
inverse operation of a decoder.
The octal-to-binary encoder consists of eight inputs, one for each of the eight digits, and three outputs that
generate the corresponding binary number, see figure 7.1. It is constructed with OR gates whose inputs can
be determined from the truth table given in table 2.1. The lower order output bit Z is 1 if the input octal digit
is odd. Output X is 1 for octal digits 4, 5, 6 or 7. Note that D 0 is not connected to any OR gate, the binary
inputs are all 0's.

Fig. 7.0 Encoder

An example of an encoder is the octal-to-binary encoder whose truth table is given in following table 7.0. It
has eight (23 ) inputs (one for each of the octal digits) and three outputs that generate the corresponding their
binary number. It is assumed that only one input has a value of 1 at a times.

The encoder can be applied with OR gates whose inputs are determined directly from the truth table. These
conditions can be expressed by the following Boolean output functions:

Fig. 7.1 Logic diagram octal-to-binary encoder.

 Note that the circuit has eight inputs and could have 28 =256 possible input combinations. Only
eight of these combinations have any meaning. The other inputs combinations are don't care
conditions. The operation of the encoder listed in table 2.1

Table 7.0 True table of octal-to-binary encoder

Limitation to encoder

• Exactly one input must be active at any given time.

• If the number of active inputs is less than one or more than one, the output will be
incorrect.
• For example, if E3 = E6 = 1, the output of the encoder A2A1A0 = 111, which
implies incorrect output.

7.2 Combinational logic of encoder

The limit of the encoder shown in the table is that only one input can be active at any given time. If two
inputs are simultaneously activated the output produces an undefined combination. For example, if D3 and
D6 are 1 together, the output of the encoder will be 111 because all three outputs are equal 1 and Output 111
does not represent either binary 3 or binary 6. To resolve this ambiguity, the encoder circuit has to be installed
. It has an input priority to ensure that only one input is encoded. If we set a higher priority to an input with
a higher subscript number, and if both D3 and D6 are 1 at the same time, the output will be 110 because D6
has a higher priority than D3. Another ambiguity in octal-to-binary encoders is that an output with all 0s is
produced when all inputs are 0; But this output is the same when D0 equals 1. The discrepancy can be
resolved by providing another output to indicate whether at least one of the inputs is equal to 1.

Uses of encoder :-

• Encoders are a very common electronic circuit used in all digital systems.
• Encoder is used to translate decimal values into binary so that binary functions like addition,
 subtraction, multiplication etc. can be performed.
• Other applications may include interrupt detection in microprocessor applications,
specifically for priority encoders.
• It is used in automatic health monitoring systems and RF-based home automation system.
• it is metal detector with robotics vehicle.
• War field flying robot with a using night-vision flying camera.
• Speed can be synchronized of multiple motors in industries.
• Encoder can be used for CNC machines and the medical industry most common for breast
cancer treatment in the world.

7.3 Decoder | what is decoder

A decoder is a combinational circuit that converts coded information, such as binary, into a
recognizable form, such as decimal.

A decoder has a combinational circuit that converts binary information from n input lines to a maximum of
2n output lines. If the n -bit coded information has unused combinations, the decoder may have fewer than
2n outputs. Each combination of inputs will assert a unique output. The name decoder is also used with other
code converters, such as the BCD-to-seven segment decoder. At a particular tie one output line is active.
The input to a decoder is parallel binary number and it is used to detect the presence of a specific binary
number at the input. The output indicates the presence or absence of specific number at the decoder input.

Fig. 7.2 Combinational logic of decoder

Example of 2-to 4 decoder

Figure below shows a 2-to-4 line decoder circuit. The two inputs are decoded into four outputs, each output
representing one of the minterms of the 2-input variables. The two inverters provide the complement of the
input, each one of the minterms. However, a 2-to-4 line decoder can be used for decoding any 2-bit code to
provide four outputs, one of each element at the code.
 Fig. 7.3 Logic circuit of 2 to 4 lines decoder

The operation of the decoder may be further classified from its input-output relationships, listed in table 2
observe that one output variable are mutually exclusive because only one output can be equal to 1 at one
time. The operation of the encoder is shown table 1

Table 7.1 True table of 2-to-4 line decoder

Enabling line: In figure 2.1 shows the block diagram of a typical decoder with enabling line, which has
n input lines, and m output lines, where m is equal to 2n. The decoder is called n-to- m decoder. Apart
from this, there is also a single line connected to the decoder called enable line.

Fig. 7.4 The decoder with the enabling line

General decoders have the “enable” input .The enable input performs no logical operation, but is only
responsible for making the decoder ACTIVE or INACTIVE.

If the enable “E”

• is zero, then all outputs are zero regardless of the input values.
 • is one, then the decoder performs its normal operation.
Example of decoder with enable

7.3.1 Uses of decoder

• It is used for code conversion. i.e analog to digital conversion in the analog decoder and also
used for data distribution.
• Decoder can be used to minimize the effect of system decoding for high performance memory
system and it is used as address deoders in CPU memory location identification…
• Decoders are mainly used in logical circuits, data transfer and They can also be used to create
simple other digital logics like half adders and full adders .
• Microprocessor can be selected different I/O devices.
• It is decoding to binary input to activate the LED segments so that the decimal number can be
displayed.
• Microprocessor memory system an be selected different banks of memory.
• The decoder can be used as sequencing or a timing signals to turn the device on or off at
specific times because when the decoder inputs come from a counter that is being continually
pulsed, the decoder output will be activated sequentially.
• It is used whenever an output or a group of output is to be activated only on the occurrence of
a specific combination of input signals.
• It can be the application of switching function often with the fewer integrated circuit.

7.3.2 Applications of Decoder

The applications of decoder involve in the making of various electronic projects.

• War- Field -Flying Robot with a Night Vision Flying Camera
• Robotic Vehicle with Metal Detector
• RF-based Home Automation System
 • Speed Synchronization of Multiple Motors in Industries
• Automatic Wireless Health Monitoring System in Hospitals for Patients
• Secret Code Enabled Secure Communication using RF Technology

7.4 Difference between Encoder and Decoder

As mentioned above encoder and decoder are exact different from each other in terms of functioning. The
given table summarizes the difference between the encoder and decoder in detail.

Basis Encoder Decoder

Maps a smaller
Maps multiple inputs to a
Purpose representation back to the
smaller representation
original inputs

Fixed, outputs are Dynamic, outputs can

Operation determined by the input change based on the
combination input code

Compression, encoding, Expansion, decoding,

error correction, D/A A/D conversion,
Application
conversion, address demultiplexing, address
decoding decoding

Number of
Input lines are 2^n, Input lines are n, Output
inputs and
Output lines are n lines are 2^n
outputs:

Data flow Parallel to serial Serial to parallel

 Basis Encoder Decoder

High, compact
Depends on the
representation of data
Efficiency implementation, may
reduces transmission
have a higher overhead
time

Limited, output
High, can be designed to
representation is
Flexibilty handle different input
determined by the input
codes
combination

Reprsentation Compact Expanded

7.5 Implementation of Encoder and Decoder

Implementation of an encoder and decoder in digital signal processing typically involves the following steps:

Encoder Implementation

• Sampling: The analog signal is sampled at regular intervals to obtain a series of discrete values.

• Quantization: The discrete values are quantized, or mapped to a finite set of numerical values, to
reduce the number of bits required to represent the signal.

• Compression: The quantized values are compressed to reduce the size of the data for efficient
transmission or storage. This can be achieved using lossless or lossy compression algorithms,
depending on the desired level of compression and the acceptable level of data loss.

Decoder Implementation

• Decompression: The compressed data is decompressed to reconstruct the quantized values.

• Dequantization: The quantized values are dequantized to obtain an approximation of the original
discrete values.
 • Reconstruction: The discrete values are reconstructed to obtain an approximation of the original
analog signal.

It's worth noting that the exact implementation details of an encoder and decoder in digital signal processing
will vary depending on the specific signal and application. Different encoding and decoding algorithms may
use different techniques for sampling, quantization, compression, and reconstruction, tailored to the specific
requirements of the signal and the system.

7.6 Applications of Encoder and Decoder

Encoder and decoder are widely used in many applications in digital circuits and systems, including:

• Computer Memory: Encoders are used to encode addresses in computer memory, allowing for
efficient access to specific memory locations. Decoders are used to decode the encoded addresses
and access the corresponding memory locations.

• Digital Communication Systems: Encoder and Decoder are used in the Digital Communication
Systems for the interconversion of signals so that they can be transferred from one place to another.

• Computer Peripherals: Encoders are used in computer peripherals, such as keyboards and mice, to
encode user inputs and transmit them to the computer. Decoders are used to decode the encoded
inputs and interpret them in the computer.

• Robotics and Automation: Encoders are used in robotics and automation systems to encode and
decode positional information, allowing for precise control of motors and actuators.

• Data Compression: Encoders are used in data compression algorithms to reduce the size of data for
efficient transmission or storage. Decoders are used to decompress the compressed data and
reconstruct the original data.

• Digital Signal Processing: Encoders are used in digital signal processing to quantize and compress
signals, allowing for efficient processing and analysis. Decoders are used to dequantize and
decompress the signals and reconstruct the original data.

• Display Technology: Encoder and Decoder are used in display technology, such as televisions and
computer monitors, to encode and decode video signals.

So these are some of the major applications of encoder and decoder.

7.7 Summary
Encoder and decoder are fundamental building blocks in digital circuits and play a crucial role in converting
digital signals from one format to another. An encoder is a digital circuit that converts information from
multiple inputs into a coded format that can be transmitted or stored more efficiently. Encoders are commonly
used in applications such as data compression, error correction, and digital-to-analog conversion.
A decoder, on the other hand, is a digital circuit that performs the reverse operation of an encoder, converting
coded information into multiple outputs. Decoders are used in applications such as memory address
decoding, data demultiplexing, and digital-to-analog conversion. In memory address decoding, a decoder is
used to convert binary addresses into specific memory locations, allowing the processor to access specific
data stored in the memory. In data demultiplexing, a decoder is used to distribute one data input to multiple
outputs, based on the input signal.

Encoder and decoder can be implemented using different digital logic circuits such as AND gates, OR gates,
NOT gates, and NAND gates. The choice of encoder or decoder size and type depends on the specific
requirements of the application. Encoder and decoder are widely used in a variety of digital systems such as
computers, communication systems, and digital control systems.

Encoder and decoder play a crucial role in converting digital signals from one format to another, allowing
for efficient data storage and transmission. Their applications range from simple data compression to
complex memory address decoding, and they are widely used in a variety of digital systems.
8.0 Multiplexer
A multiplexer (sometimes spelled multiplexor and also known as a MUX) is defined as a combinational
circuit that selects one of several data inputs and forwards it to the output. The inputs to a multiplexer can
be analog or digital. Multiplexers are also known as data selectors.
A multiplexer is useful for transmitting a large amount of data over the network within a certain amount
of time and bandwidth.

Multiplexers that are built from transistors and relays are termed as analog multiplexers which are used in
analog applications and Multiplexers that are built from logic gate termed as digital multiplexers which
are used in digital applications. The inverse of a multiplexer is known as a demultiplexer.

What Does a Multiplexer Do?

In digital systems, many times it is necessary to select a single data line from several data-input lines and
the data from the selected data input line should be available on the output line. The digital circuit which
does this task is a multiplexer.

A multiplexer is a digital circuit that selects one of the n data inputs and forwards it to the output. The
selection of one of the n inputs is done by the select inputs. To select one of several inputs, we need m
select lines such that 2m=n.
Depending on the digital code applied at the select inputs, one of the n data inputs is selected and
transmitted to the single output. Hence, a multiplexer has maximum 2 n data input lines, ‘m’ selects lines,
and one output line.
The block diagram of an n-to-1 multiplexer and its equivalent circuit is shown in the figure below.
How Does a Multiplexer Work?
The multiplexer works like a multiple-input and single-output switch. The output gets connected to only
one of the n data inputs at a given instant of time. Therefore, the multiplexer is ‘many into one’ and it
works as the digital equivalent of an analog selector switch.

8.1 Multiplexer Circuit

There are many types of multiplexers – like 2-to-1, 4-to-1, and 8-to-1 multiplexers. Each one has a different
circuit, truth table, boolean expression, and working principle. Let’s discuss each type of multiplexer one
by one.

8.1.1 2 to 1 Multiplexer
2 to 1 Multiplexer Circuit
A 2-to-1 multiplexer is the digital multiplexer circuit that has two data inputs D 0 and D1, one selects line
S and one output Y. To implement a 2-to-1 multiplexer circuit we need 2 AND gates, an OR gate, and a
NOT gate.

The block diagram, logic symbol and switching circuit analogy of 2-to-1 multiplexer is shown in the
figure below.
As shown, D0 is an applied input to one of the AND gate and D1 is an applied input to the other AND gate.
Select input S is applied to the second AND gate as a second input and an inverted input S is applied to
the first AND gate as a second input. The output of both the AND gates is applied as inputs to the OR
gate.2 to 1 Multiplexer Circuit

8.1.2 2 to 1 Multiplexer Working Principle

When S=0, it is applied directly as an input to the second AND gate, and inverted S that is 1 is applied as
a second input to the first AND gate. Now, we know that for AND gate if any one input is zero, the output
is zero. So, the output of the second AND gate is zero. Since the second input to the first AND gate is 1,
its output is equal to its first input, which is Y = D0.
When S=1, Exactly the reverse happens. In this case, the second AND gate output is equal to its first input,
that is Y = D1 and the first AND gate output is 0.
So, by applying either a logic ‘0’ or a logic ‘1’ at the select input S, we can select the appropriate input, D 0 or
D1 with the circuit act like a single pole double throw (SPDT) switch.
2 to 1 Multiplexer Truth Table
The below table shows the truth table for the 2-to-1 multiplexer.

Select input S Data Input Data Input Output Y

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 0
 1 0 1 1

1 1 0 0

1 1 1 1

Here, the 2-input multiplexer connects one of two 1-bit sources to a common output, hence it produces a 2-
to-1 multiplexer.

2 to 1 Multiplexer Boolean Expression

From the truth table, we can write the boolean expression for the output of the 2-to-1 multiplexer.

In simple notation

S Y

0 D0

1 D1

As shown in the above table that when select input S=0 then output Y=D0 and when S=1 then Y=D1. We can
increase the number of data inputs to be selected further and larger multiplexer circuits can be implemented
using smaller 2-to-1 multiplexer.

We can also implement all the multiplexers by using the NAND gate. Note that NAND and NOR gates are
a universal gate and we can implement any digital circuits by using NAND and NOR gates.

8.2 Advantages and disadvantages of Multiplexers in Digital Logic

Advantages of Multiplexers in Digital Logic

• Space-saving: Multiplexers consider numerous signs to be directed through a solitary channel,
which recoveries space in computerized circuits.
 • Cost-successful: Multiplexers can assist with decreasing the expense of Advanced circuits by
diminishing the quantity of parts required.
• Time-saving: Multiplexers can save time in computerized circuits by decreasing the quantity of
parts that should be wired together, subsequently diminishing the intricacy of the circuit.
• Flexibility: Multiplexers are profoundly adaptable and can be utilized in a great many applications

Some other advantages of a Multiplexer include:

• A multiplexer reduces the number of wires used. Hence it reduces the circuit complexity and
overall cost.
• A multiplexer improves the reliability of the digital systems because it reduces the number of
external wired connections.
• We can implement many combinational circuits using MUX.
• Multiplexer simplifies the logic design.
• Multiplexer does not need the k-maps (Karnaugh map) and simplification.

Disadvantages of Multiplexers in Digital Logic:

• Limited number of data sources: The quantity of sources of info that can be taken care of by a
multiplexer is restricted by the quantity of control lines, which can be a disservice in certain
applications.
• Delay: Multiplexers can present some postpone in the sign way, which can influence the
exhibition of the circuit.
• Complex control rationale: The control rationale for multiplexers can be perplexing, particularly
for bigger multiplexers with an enormous number of data sources.
• Power utilization: Multiplexers can consume more power contrasted with other straightforward
rationale entryways, particularly when they have countless data sources.

8.3 Applications of a Multiplexer

Some of the applications of a Multiplexers include:

Communication Systems

•Multiplexers are used as a data selector to select one out of many data inputs in communication
systems to transmit the various types of data (audio, video, etc.) at the same instant. Hence it
increases the efficiency of the communication system by allowing various types of data into
single transmission lines.
Telephone Networks

•
In a telephone network, multiplexers can be used to transmit multiple audio signals into a
single channel.
Computer Memory
 • In computer memory, multiplexers are used to implement a large amount of data, at the same
instant reduces the number of copper wires required to connect memory to other parts in the
computer.
Transmission from the computer system to a satellites

• Multiplexers are also used to transmit the data from the computer system of a spacecraft or
satellite to the earth by utilizing “GPS” (Global Positioning System) and “GSM” (Global
System for Mobile Communication).
Some other applications include:

• Multiplexers can be used to implement the combinational logic circuit like time-multiplexing
systems and frequency multiplexing systems, A/D and D/A converter.
• Multiplexers can be used to implement Boolean functions of multiple variables.
• Multiplexers are used in data acquisition systems.
9.0 Arithmetic circuits

In this session you will study digital arithmetic. Digital arithmetic is, used in the internal calculations
performed in many modem computer systems. An arithmetic circuit is a set of gates with a separate set of
inputs for each number that has to be processed. The gates are connected so as to carry out an arithmetic
action and the outputs of the gate circuit are the digits of the result.

9.1 Half and full adder

Addition is one of the most basic operations performed by different electronic devices like computers,
calculators, etc. The electronic circuit that performs the addition of two or more numbers, more specifically
binary numbers, is called as adder. As we know, the logic circuits use binary number system to perform the
operations, hence the adder is referred to as binary adder.
Depending on the number of binary digits that a circuit can add, adders (or binary adders) are of two types
• Half Adder
• Full Adder

9.1.2 What is a Half-Adder?

A combinational logic circuit which is designed to add two binary digits is called as a half adder. The half
adder provides the output along with a carry value (if any). The half adder circuit is designed by connecting
an EX-OR gate and one AND gate. It has two input terminals and two output terminals for sum and carry.
The block diagram and circuit diagram of a half adder are shown in figure 9.0.

Fig. 9.0 Half adder and Circuit diagram

From the logic circuit diagram of half adder, it is clear that A and B are the two input bits, S is the output
sum, and C is the output carry bit.
In the case of a half adder, the output of the EX-OR gate is the sum of two bits and the output of the AND
gate is the carry. Although, the carry obtained in one addition will not be forwarded in the next addition
because of this it is known as half adder.

9.1.2.1 Operation of Half Adder

Half adder adds two binary digits according to the rules of binary addition. These rules are as follows −
 0+0=0
0+1=1
1+0=1
1 + 1 = 10 (Sum = 0 & Carry = 1)
According to these rules of binary addition, we can see that the first three operations produce a sum whose
length is one digit, whereas in the case of last operation (1 and 1), the sum consists of two digits. Here, the
MSB (most significant bit) of this result is called a carry (which is 1) and the LSB (least significant bit) is
called the sum (which is 0).

9.1.2.2 Truth Table of Half Adder

Truth table is one that gives the relationship between inputs and outputs of a logic circuit and explains the
operation of the circuit. The following is the truth table of the half-adder −

Inputs Outputs

A B S (Sum) C (Carry)

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

9.1.2.3 K-Map for Half Adder

We can use the K-Map (Karnaugh Map), a method for simplifying Boolean algebra, to determine equations
of the sum bit (S) and the output carry bit (C) of the half adder circuit.
The k-map for half adder circuit is shown in Figure 9.1.

Fig. 9.1 K-Map for Half-Adder

9.1.2.4 Characteristic Equations of Half-Adder
The characteristic equations of half adder, i.e., equations of sum (S) and carry (C) are obtained according to
the rules of binary addition. These equations are given below −
The sum (S) of the half-adder is the XOR of A and B. Thus,

Sum, S =A⊕B = AB′+A′B

The carry (C) of the half-adder is the AND of A and B. Therefore,

Carry, C=A⋅B

9.1.3 Advantages and disadvantages of Half Adder in Digital Logic

Advantages of Half Adder in Digital Logic

Simplicity: A half viper is a straightforward circuit that requires a couple of fundamental parts like XOR
AND entryways. It is not difficult to carry out and can be utilized in numerous advanced frameworks.
Speed: The half viper works at an extremely rapid, making it reasonable for use in fast computerized circuits.

Disadvantages of Half Adder in Digital Logic

Limited Usefulness: The half viper can add two single-piece numbers and produce a total and a convey bit.
It can’t perform expansion of multi-bit numbers, which requires the utilization of additional intricate circuits
like full adders.
Lack of Convey Info: The half snake doesn’t have a convey input, which restricts its value in more mind
boggling expansion tasks. A convey input is important to perform expansion of multi-bit numbers and to
chain numerous adders together.
Propagation Deferral: The half snake circuit has a proliferation delay, which is the time it takes for the result
to change in light of an adjustment of the info. This can cause timing issues in computerized circuits,
particularly in fast frameworks.

9.1.4 Application of Half Adder in Digital Logic

Arithmetic circuits: Half adders are utilized in number-crunching circuits to add double numbers. At the
point when different half adders are associated in a chain, they can add multi-bit double numbers.
Data handling: Half adders are utilized in information handling applications like computerized signal
handling, information encryption, and blunder adjustment.
Address unraveling: In memory tending to, half adders are utilized in address deciphering circuits to produce
the location of a particular memory area.
Encoder and decoder circuits: Half adders are utilized in encoder and decoder circuits for computerized
correspondence frameworks.
Multiplexers and demultiplexers: Half adders are utilized in multiplexers and demultiplexers to choose and
course information.
Counters: Half adders are utilized in counters to augment the count by one.

9.2 Full Adder in Digital Electronics

In this tutorial, we will discuss the Full Adder, its definition, circuit diagram, truth table, k-map,
characteristic equations, and applications.
What is a Full Adder?
A combinational logic circuit that can add two binary digits (bits) and a carry bit, and produces a sum bit
and a carry bit as output is known as a full-adder.
In other words, a combinational circuit which is designed to add three binary digits and produces two outputs
(sum and carry) is known as a full adder. Thus, a full adder circuit adds three binary digits, where two are
the inputs and one is the carry forwarded from the previous addition. The block diagram and circuit diagram
of the full adder are shown in Figure 9.2.

Fig. 9.2 Block diagram full adder and Circuit equivalent

Hence, the circuit of the full adder consists of one EX-OR gate, three AND gates and one OR gate, which
are connected together as shown in the full adder circuit in Figure above.

9.2.1 Operation of Full Adder

Full adder takes three inputs namely A, B, and Cin. Where, A and B are the two binary digits, and Cin is the
carry bit from the previous stage of binary addition. The sum output of the full adder is obtained by XORing
the bits A, B, and Cin. While the carry output bit (Cout) is obtained using AND and OR operations.
Truth Table of Full Adder
Truth table is one that indicates the relationship between input and output variables of a logic circuit and
explains the operation of the logic circuit. The following is the truth table of the full-adder circuit –
 Inputs Outputs

A B Cin S (Sum) Cout (Carry)

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Hence, from the truth table, it is clear that the sum output of the full adder is equal to 1 when only 1 input is
equal to 1 or when all the inputs are equal to 1. While the carry output has a carry of 1 if two or three inputs are
equal to 1.

9.2.2 K-Map for Full Adder

K-Map (Karnaugh Map) is a tool for simplifying binary complex Boolean algebraic expressions. The K-Map
for full adder is shown in figure below.

S=A⨁B⨁C C = AB+AC+BC
9.2.3 Advantages and Disadvantages of Full Adder in Digital Logic
Advantages of Full Adder in Digital Logic
Flexibility: A full snake can add three information bits, making it more flexible than a half viper. It can likewise
be utilized to add multi-bit numbers by binding different full adders together.
Carry Info: The full viper has a convey input, which permits it to perform expansion of multi-bit numbers and
to chain different adders together.
Speed: The full snake works at an extremely fast, making it reasonable for use in rapid computerized circuits.

Disadvantages of Full Adder in Digital Logic

Complexity: The full snake is more mind boggling than a half viper and requires more parts like XOR, AND,
or potentially entryways. It is likewise more challenging to execute and plan.
Propagation Deferral: The full viper circuit has a proliferation delay, which is the time it takes for the result to
change in light of an adjustment of the info. This can cause timing issues in computerized circuits, particularly
in fast frameworks.

9.3 Application of Full Adder in Digital Logic

Arithmetic circuits: Full adders are utilized in math circuits to add twofold numbers. At the point when different
full adders are associated in a chain, they can add multi-bit paired numbers.
Data handling: Full adders are utilized in information handling applications like advanced signal handling,
information encryption, and mistake rectification.
Counters: Full adders are utilized in counters to addition or decrement the count by one.
Multiplexers and demultiplexers: Full adders are utilized in multiplexers and demultiplexers to choose and
course information.
Memory tending to: Full adders are utilized in memory addressing circuits to produce the location of a particular
memory area.
ALUs: Full adders are a fundamental part of Number juggling Rationale Units (ALUs) utilized in chip and
computerized signal processors.
10.0 Binary Subtraction Circuits
Another basic arithmetic operation to be performed by Digital Computers is the Subtraction.
Subtraction is a mathematical operation in which one integer number is deducted from another to
obtain the equivalent quantity. The number from which other number is to be deducted is called as
‘Minuend’ and the number subtracted from the minuend is called ‘Subtrahend’.

Similar to the binary addition, binary subtraction also, has four possible basic operations. They are:
• 0–0=0
• 0 – 1 = (Borrow)1
• 1–0=1
• 1–1=0

Fig.10 The subtraction rule

In figure 10 shows the four possible rules or elementary operations of the binary subtractions. In all the
operations, each subtrahend bit is deducted from the minuend bit. But in the second rule, minuend bit is smaller
than the subtrahend bit, hence 1 is borrowed to perform the subtraction. Similar to the adder circuits, basic
subtraction circuits are also of two types:
• Half Substractor
• Full Substractor

10.1 Half Subtractors

A Half Subtractor is a multiple output Combinational Logic Circuit that does the subtraction of two 1-bit
binary numbers. It has two inputs and two outputs. The two inputs correspond to the two 1-bit binary numbers
and the two outputs corresponds to the Difference bit and Borrow bit (in contrast to Sum and Carry in Half
Adder).
From the above truth table, we can say that the ‘Difference’ output of the Half Subtractor is similar to an
XOR output (which is also same as the Sum output of the Half Adder).

Thus, the Half Subtraction is also performed by the Ex-OR gate with an AND gate with one inverted input
and one normal input, requiring to perform the Borrow operation. In table 5 shows the truth table of a half
substractor
 Table 10 Truth table for half substractor

The figure 10.1 below shows the complete diagram for the half substractor

Fig. 10.1 Half Substractors

This circuit is similar to that of the Half Adder with only difference being the minuend input i.e., A is
complemented before applied at the AND gate to implement the borrow output.
In case of multi-digit subtraction, subtraction between the two digits must be performed along with borrow
of the previous digit subtraction, and hence a subtractor needs to have three inputs, which is not possible
with a Half Subtractor. Therefore, a half subtractor has limited set of applications and strictly speaking, it is
not used in practice.

10.1.2 K-Map for half subtractor

We can use the K-Map (or Karnaugh Map), a method for simplifying Boolean algebra, to determine equations
of the difference bit (d) and the output borrow (b).
10.1.3 Application of Half Subtractor in Digital Logic:
Calculators: Most mini-computers utilize advanced rationale circuits to perform numerical tasks. A Half
Subtractor can be utilized in a number cruncher to deduct two parallel digits from one another.
Alarm Frameworks: Many caution frameworks utilize computerized rationale circuits to identify and answer
interlopers. A Half Subtractor can be utilized in these frameworks to look at the upsides of two parallel pieces
and trigger a caution in the event that they are unique.
Automotive Frameworks: Numerous advanced vehicles utilize computerized rationale circuits to control
different capabilities, like the motor administration framework, stopping mechanism, and theater setup. A
Half Subtractor can be utilized in these frameworks to perform computations and examinations.
Security Frameworks: Advanced rationale circuits are usually utilized in security frameworks to identify
and answer dangers. A Half Subtractor can be utilized in these frameworks to look at two double qualities and
trigger a caution in the event that they are unique.
Computer Frameworks: Advanced rationale circuits are utilized broadly in PC frameworks to perform
estimations and examinations. A Half Subtractor can be utilized in a PC framework to deduct two paired
values from one another.

Limitation of Half Subtractor-

• Half subtractors do not take into account “Borrow-in” from the previous circuit.
• This is a major drawback of half subtractors.
• This is because real time scenarios involve subtracting the multiple number of bits which cannot be
accomplished using half subtractors.

Exercise: Write the Boolean expression for the half substractor

10.2 Full substractor

A Full Subtractor is a combinational logic circuit which performs a subtraction between the two 1-bit binary
numbers and it also considers the borrow of the previous bit i.e., whether 1 has been borrowed by the previous
minuend bit.

So, a Full Subtractor has three inputs, in which two inputs corresponding to the two bits to be subtracted
(minuend A and subtrahend B), and a borrow bit, usually represented as BIN, corresponding to the borrow
operation. There are two outputs, one corresponds to the difference D output and the other Borrow output
BO
Table 10.1 shows the truth table for a Full Subtractor. In the table it can be stated as:

• 'A' and' B' are the input variables. These variables represent the two significant bits that are going to be
subtracted.
• 'Borrowin' is the third input which represents borrow.
• The 'Diff' and 'Borrow' are the output variables that define the output values.
• The eight rows under the input variable designate all possible combinations of 0 and 1 that can occur in
these variables.

Table 10.1 Full Subtractor table.

By deriving the Boolean expression for the full subtractor from above truth table, we get the expression that
tells that a full subtractor can be implemented with half subtractors with OR gate as shown in figure 10.3.

By comparing the adder and subtractor circuits and truth tables, we can observe that the output D in the full
subtractor is exactly same as the output S of the full adder (see figure 9.2). And the only difference is that
input variable A is complemented in the full subtractor.

The following image in figure 10.2 shows the block diagram of a full subtractor.

Fig. 10.2 Full Substractors and truth table

Fig. 10.3 Full substractor by two substractor

Therefore, it is possible to convert the full adder circuit into full subtractor by simply complementing the
input A before it is applied to the gates to produce the final borrow bit output B0.
10.2.1 K-Map for Full Subtractor
We can use the K-Map (or Karnaugh Map), a method for simplifying Boolean algebra, to determine equations
of the difference bit (d) and the output borrow bit (b).

Fig. 10.4 K-Map of full subtractor

Logical expression for difference

D = A’B’Bin + A’BBin’ + AB’Bin’ + ABBin
= Bin(A’B’ + AB) + Bin’(AB’ + A’B)
= Bin( A XNOR B) + Bin’(A XOR B)
= Bin (A XOR B)’ + Bin’(A XOR B)
= Bin XOR (A XOR B)
= (A XOR B) XOR Bin

Logical expression for borrow –

Bout = A’B’Bin + A’BBin’ + A’BBin + ABBin
= A’B’Bin +A’BBin’ + A’BBin + A’BBin + A’BBin + ABBin
= A’Bin(B + B’) + A’B(Bin + Bin’) + BBin(A + A’)
= A’Bin + A’B + BBin
 OR

Bout = A’B’Bin + A’BBin’ + A’BBin + ABBin

= Bin(AB + A’B’) + A’B(Bin + Bin’)
= Bin( A XNOR B) + A’B
= Bin (A XOR B)’ + A’B

10.2.2 Applications of Full Subtractor

The following are some important applications of full subtractor −
• Full subtractors are used in ALU (Arithmetic Logic Unit) in computers CPUs.
• Full subtractors are extensively used to perform arithmetical operations like subtraction in electronic
calculators and many other digital devices.
• Full subtractors are used in different microcontrollers for arithmetic subtraction.
• They are used in timers and program counters (PC).
• Full subtractors are also used in processors to compute addresses, tables, etc.
• Full subtractors are also used in DSP (Digital Signal Processing) and networking based systems.

10.3 Disadvantages and Advantages of Subtractor Circuit

The following are some examples of the disadvantages and advantages of this subtraction

Disadvantages
• In case of half subtractor, there is no provision for accepting Borrow as input from
the previous stage.
• The speed of the subtractor is limited by the longest delay through the circuit.

Advantages
• It is simple to design and implement.
• Power deduction in Digital Signal Processing.
• Computational tasks can be carried out at high speed.

11.0 Microcomputer Interface

Before attempting to design microcomputer interfaces and systems, it is wise to get familiar with the interface
components available to the microcomputer designer. What could be more disheartening than spending a
week designing a special interface circuit only to find that a one- chip interface component could have
performed the task?
There are two general levels on which interface parts should be known: the functional level and the electrical
level. In the past, simple devices such as transistors and resistors were well understood' on both levels by
most designers mainly because the functions of these devices were directly related to their electrical
characteristics. A resistor, for example, could be selected to perform a variety of functions, its value being
determined by a simple application of Ohm's law.
In regards to microprocessors and interface parts, however, the functional or logical aspects tend to eclipse
the electrical characteristics. Thinking only on the logical level can lead to trouble when designing a system.
Unless logic thresholds, noise margins, fan-outs, and propagation delays are taken into account, a logically
correct circuit simply will not work.

11.1 Interfacing with the Analog World

A digital quantity will have a value that is specified as one of two possibilities such as 0 or 1, LOW or HIGH,
true or false, and so on. In practice, the voltage representation a digital quantity such as a may actually have
a value that is anywhere within specified ranges. For example, for TTL logic:
0V to 0.8V = logic 0 2V to 5V = logic 1

Any voltage falling in the range 0 to 0.8 V is given the digital value 0, and any voltage in the range 2 to 5 V
is assigned the digital value 1. The digital circuits respond accordingly to all voltage values within a given
range.

Most physical variables are analog in nature and can take on any value within a continuous range of values.
Examples include temperature, pressure, light intensity, audio signals, position, rotational speed, and flow
rate. Digital systems perform all of their internal operations using digital circuitry and digital operations. Any
information that has to be inputted to a digital system must first be put into digital form. Similarly, the outputs
from a digital system are always in digital form.

11.2 Transducer
The physical variable is normally a nonelectrical quantity. A transducer is a device that converts the physical
variable to an electrical variable, see figure 11. Some common transducers include thermistors, photocells,
photodiodes, flow meters, pressure transducers, and tachometers. The electrical output of the transducer is
an analog current or voltage that is proportional to the physical variable it is monitoring. For example, the
physical variable could be the temperature of water. Let’s say that the water temperature varies from 80 to
1500 F and that a thermistor and its associated circuitry convert this water temperature to a voltage ranging
from 800 to 1500mV. Note that the transducer’s output is directly proportional to temperature; such that each
10 F produces a 10mV output. Analog-to digital converter (ADC) and digital-to-converter (DAC) are used
to interface a computer to the analog world so that the computer can monitor and control a physical variable
 Fig. 11 Interfacing with the analog world using Analog-to-Digital Converter (ADC) and Digital-
to- Analog Converter (DAC).

11.3 Actuator
The analog signal from the DAC is often connected to some device or circuit that serves as an actuator to
control the physical variable. For our water temperature example, the actuator might be an electrically
controlled valve that regulates the flow of hot water into the tank in accordance with the analog voltage from
the DAC. The flow rate would vary in proportion to this analog voltage, with 0 V producing no flow and
10 V producing the maximum flow rate.
Thus we see that ADCs and DACs function as interfaces between a completely digital system, like a
computer, and the analog world.

11.4 Analog-to-Digital Converter (ADC)

The transducer’s electrical analog output serves as the analog input to the ADC. The ADC converts this
analog input to a digital output. This digital output consists of a number of bits that represent the value of the
analog input. For example, the ADC might convert the transducer’s 800- to 1500-mV analog values to binary
values ranging from 01010000 (80) to 10010110 (150). Note that the binary output from the ADC is
proportional to the analog input voltages so that each unit of the digital output represents 10mV.
The digital representation of the analog vales is transmitted from the ADC to the digital computer, which
stores the digital value and processes it according to a program of instructions that it is executing.

11.4 Digital-to-Analog Converter (DAC)

This digital output from the computer is connected to a DAC, which converts it to a proportional
analog voltage or current. For example, the computer might produce a digital output ranging from
0000000 to 11111111, which the DAC converts to a voltage ranging from 0 to 10V.

11.4.1 Digital-to-Analog Conversion (DAC)

Basically, D/A conversion is the process of taking a value represented in digital code (such as straight binary
or BCD) and converting it to a voltage or current which is proportional to the digital value. Figure 11 shows
the symbol for a typical 4-bit D/A converter. Now, we will examine the various input/output relationships.
Fig. 11 4 bit DAC with voltage output

The digital inputs D, C, B, and A are usually derived from the output register of a digital system. The 24 =
16 different binary numbers represented by these 4 bits for each input number, the D/A converter output
voltage is a unique value. In fact, for this case, the analog output voltage Vout is equal in volts to the binary
number.

In general,

Analog output = K × digital input

where K is the proportionality factor and it is constant value for a given DAC. The analog output can of
course be a voltage or current. When it is a voltage, K will be in voltage units, and when the output is current,
K will be in current units. For the DAC of K=1 V, so that

VOUT = (1 V) × digital input

We can use this to calculate VOUT for any value of digital input. For example, with a digital input of 11002 =
1210, we obtain

VOUT = 1V × 12 = 12V

Problem 1: A 5-bit DAC has a current output. For a digital input of 101000, an output current of 10mA is
produced. What will IOUT be for a digital input of 11101?

Solution: The digital input 101002 is equal to decimal 20. Since IOUT = 10 mA for this case, the
proportionality factor as 0.5 mA. Thus, we can find for a digital input such as 11101 2 = 2910 as
follows:

IOUT = (0.5mA) × 29
= 14.5 mA
Remember, the proportionality factor, K, will vary from one DAC to another.

Problem 2. What is the largest value of output voltage from an 8-bit DAC that produces 1.0V for a
digital input of 00110010?

Solution: 001100102 = 5010

1.0 V = K× 50
Therefore, K = 20mV

The largest output will occur for an input of 111111112 = 25510.

VOUT(max) =
20mV×255
= 5.10 V
11.5 Analog Output
The output of a DAC is technically not an analog quantity because it can take on only specific
values like the 16 possible voltage levels for Vout. Thus, in that sense, it is actually digital.
However, the number of different possible output levels can be increased and the difference
between successive values can be decreased by increasing the number of input bits. This will
allow us to produce an output that is more and more like an analog quantity that varies
continuously over a range of values.

11.5.1 Input Weights

For the DAC of it should be noted that each digital input contributes a different amount to the analog output.
This is easily seen if we examine the cases where only one input is HIGH as shown in Table 8. The
contributions of each digital input are weighted according to their position in the binary number.

Table 11 Input Weights

Thus, A, which is the LSB, has a weight of 1V, B has a weight of 2V, C has a weight of 4 V, and D, the MSB,
has the largest weight 8V. The weights are successively doubled for each bit, beginning with the LSB. Thus,
we can consider VOUT to be the weighted sum of the digital inputs. For instance, to find VOUT for the digital
input 0111 we can add the weights of the C, B, and A bits to obtain 4 V + 2V + 1V=7V.

Problem 3. A 5-bit D/A converter produces VOUT = 0.2 V for a digital input of 0001. Find the value of
Vout for an input of 11111.

Solution: Obviously, 0.2 V is the weight of the LSB. Thus, the weights of the other bits must be
0.4 V, 0.8 V, 1.6 V, and 3.2 V respectively. For a digital input of 11111, then, the value of VOUT will be
3.2 V + 1.6 V+ 0.8V + 0.4V + 0.2 V = 6.2V.

11.6 Resolution
Resolution of a D/A converter is defined as the smallest change that can occur in an analog output as a result
of a change in the digital input. We can see that the resolution is 1V, since VOUT can change by no less than
1 V when the digital input value is changed. The resolution is always equal to the weight of the LSB and is
also referred to as the step size. As the counter is being continually cycled through its 16 states by the clock
signal, the DAC output is a staircase waveform that goes up 1 V per step. When the counter is at 1111, the
DAC output is at its maximum value of 15 V; this is its full-scale output. When the counter recycles to 0000,
the DAC output returns to 0V. The resolution or step size of the jumps in the staircase waveform; in this

case, each step is 1V.

Fig. 11.1 Output wave forms of a four bit DAC.

Note that the staircase has 16 levels corresponding to the 16 input states, but there are only 15 steps or jumps
between the 0-V level and full-scale, In general, for an N-bit DAC the number of different levels will be 2 N,
and the number of steps will be 2N - 1.

You may have already figured out the resolution (step size) is the same as the proportionality factor in the
DAC input/output relationship:

analog output = K × digital input

A new interpretation of this expression would be that the digital input is equal to the number of the step, K
is the amount of voltage (or current) per step, and the analog output is the product of the two.

Problem 4: For the DAC of Example 3 determine V OUT for a digital input of 10001.

Solution: The step size is 0.2 V, which is the proportionality factor K. The digital input is 10001
= 1710. Thus we have:

VOUT = (0.2 V) × 17
= 3.4V

11.7 Percentage Resolution

Although resolution can be expressed as the amount of voltage or current per step, it is also useful to express
it as a percentage of the full-scale output. To illustrate, in Fig. 11.1 the DAC has a maximum full-scale output
of 15 V (when the digital input is 1111). The step size is 1V, which gives a percentage resolution.

𝑠𝑡𝑒𝑝 𝑠𝑖𝑧𝑒
% 𝑟𝑒𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛 = 𝑥 100%
𝑓𝑢𝑙𝑙 𝑠𝑐𝑎𝑙𝑒 (𝐹𝑆)
 1𝑣
= 15𝑣 𝑥 100% = 6.67%

Problem 5: A 10-bit DAC has a step size of 10 mV. Determine the full-scale output voltage and the
percentage resolution.

Solution
With 10 bits, there will be 210 - 1 = 1023 steps of 10mV each. The fullscale output will therefore be
10mV × 1023 = 10.23 V and

10𝑚𝑉
% 𝑟𝑒𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛 = 𝑋 100 % ≈ 0.1
10.23𝑉
Problem 4 helps to illustrate the fact that the percentage resolution becomes smaller as the number of input
bits is increased. In fact, the percentage resolution can also be calculated from.

1
% resolution = 𝑡𝑜𝑡𝑎𝑙 𝑛𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑠𝑡𝑒𝑝𝑠 𝑥 100 %

For an N-bit binary input code the total number of steps is 2N-1. Thus, for the previous example,
1
% resolution = 𝑥 100 % ≈ 0.1 %
210 −1

This means that it is only the number of bits which determines the percentage resolution. Increase of the
number of bits increases the number of steps to reach full scale.

11.8 Design of D/A Converter

As previous said the aim of D/A converter is to convert a binary word to a proportional current or voltage.
The binary weighted resistors produce binary-weighted current which are summed up by the op-amp to
produce proportional output voltage. The binary word applied to the switches produces a proportional output
voltage. Several different binary codes such as straight binary, BCD and offset binary are commonly used as
inputs to D/A converters.

11.8.1 D/A-Converter Circuitry

There are several methods and circuits for producing the D/A operation. We shall examine several of the
basic schemes, to gain an insight into the ideas used.

Fig. 11.2 DAC circuitry using op-amp with binary weighted resistors.

Figure 11.2 shows the basic circuit of 4-bit DAC. The inputs A,B,C, and D are binary inputs which are
assumed to have values of either 0 V or 5 V. The operational amplifier is employed as a summing amplifier,
which produces the weighted sum of these input voltages. the summing amplifier multiplies each input
voltage by the ratio of the feedback resistor RF to the corresponding input resistor RIN. In this circuit RF
RIN 1kΩ and the input resistors range from 1 to 8 kΩ . The D input has RIN = 1KΩ, so the summing amplifier
passes the voltage at D with no attenuation. The C input has RIN = 2 kΩ, so that it will be attenuated by 1/2.
Similarly, the B input will be attenuated by 1/4 and the A input by 1 /8. The amplifier output can thus be
expressed as
VOUT = - (VD +1 /2 VC + ¼ VB + 1 /8 VA)
The negative sign is present because the summing amplifier is a polarity inverting amplifier, but it will but
concern us here.
Clearly, the summing amplifier output is an analog voltage which represents a weighted sum of the digital
inputs. The output is evaluated for any input condition by setting the appropriate inputs to either 0 V or 5 V.
For example, if the digital input is 1010, then VD = VB = 5V and VC = VA = 0V. Thus, using equation
VOUT = - (5V +OV + ¼ × 5V + OV)
= - 6.25V
The resolution of this D/A converter is equal to the weighting of the lSB, which is 1 /8 × 5V = 0.625 V.
The analog output increases by 0.625 V as the binary input number advances one step.

Problem 6: Assume VREF = 10 V and R = R = 10 kΩ. Determine the resolution and fullscale output for
this DAC. Assume that RL is much smaller than R.
Solution
I0 = VREE/R = 1 mA. This is the weight of the MSB. The other three currents will be 0.5, 0.25, and 0.125
mA. The LSB is 0.125 mA, which is also the resolution.
The full-scale output will occur when the binary inputs are all HIGH so that each current switch is closed
and
IOUT = 1 + 0.5 + 0.25 + 0.125 = 1.875 mA

Note that the output current is proportional to VREF. If VREF is increased or decreased, the resolution and
full-scale output will change proportionally.

11.9 R/2R Ladder

The DAC circuits we have looked at, has some practical limitations. The biggest problem is the large
difference in resistor values between the LSB and MSB, especially in high-resolution DACs. One of the most
widely used DAC circuits that uses resistance’s fairly close in value is the R/2R ladder network. Here the
resistance values span a range of only 2 to 1.
Note, how the resistors are arranged, and only two different values are used, R and 2R. The current I OUT
depends on the positions of the four switches, and the binary inputs B 3B2B1B0 control the states of the
switches. This current is allowed to flow through an op-amp current- to-voltage converter to develop VOUT.
It can be shown that the value of VOUT is given by the expression.

where B is the value of the binary input, which can range from 000 (0) to 1111 (15).
 Fig. 9.1 R/2R ladder DAC

11.9.1 DAC Specifications

The DAC are available with wide range of specification specified by manufacturer. Some of the important
specifications are Resolution, Accuracy, linearity, monotonicity, settling time and monotonicity.
Resolution
The resolution of a converter is the smallest change in voltage which may be produced at the output (or input)
of the converter. For example, an 8-bit D/A converter has 28 -1=255 equal intervals. Hence the smallest
change in output voltage is (1/255) of the full scale output range.
𝑉𝐹𝑆
Resolution = = 1 𝐿𝑆𝐵 𝑖𝑛𝑐𝑟𝑒𝑚𝑒𝑛𝑡
2𝑛 −1

Accuracy
There are several ways of specifying accuracy. The two most common are called full-scale error and
linearity error which are normally expressed as a percentage of the converter’s full-scale output (%F.S.)
Full-scale error is the maximum deviation of the DAC’s output from its expected (ideal) value, expressed
as a percentage of full scale. For example, assume that the DCA has an accuracy of ± 0.01% F.S. Since this
converter has a full-scale output of 9.375 V, this percentage converts to

± 0.01% × 9.375 V = ± 0.9375 mV

This means that the output of this DAC can, at any time, be off by as much as 0.9375mV from its expected
value.
Linearity error is the maximum deviation in step size from the ideal step size. For example, the DAC has
an expected step size of 0.625 V. If this converter has a linearity error of ± 0.01F.S,, this would mean that
the actual step size could be off by as much as 0.9375 mV.

Problem 7 A certain 8-bit DAC has a full-scale output of 2mA and a full-scale error of ± 0.5% F.S. What is
the range of possible outputs for an input of 10000000?
Solution: The step size is 2mA/255 = 7.84 µA. Since 10000000 = 12810, the ideal output should be 128 ×
7.84 µA. The error can be as much as
± 0.5% × 2mA = ± 10µA

Thus, the actual output can deviate by this amount from the ideal 1004µA , so the actual output can be
anywhere from 994 to 1014 µA.

Offset Error
Ideally, the output of a DAC will be zero volts when the binary input is all 0’s. In practice, however, there
will be a very small output voltage for this situation; this is called offset error. This offset error, if not
corrected, will be added to the expected DAC output for all input cases. Offset error can be negative as well
as positive.
Many DACs will have an external offset adjustment that allows you to zero the offset. This is usually
accomplished by applying all 0s to the DAC input and monitoring the output while an offset adjustment
potentiometer is adjusted until the output is as close to 0 V as required.

Settling Time
The operating speed of a DAC is usually specified by giving its settling time, which is the time required for
the DAC output to go from zero to full scale as the binary input is changed from all 0’s to all 1’s. Typical
values for settling time range from 50 ns to 10 μs.

Monotonicity
A DAC is monotonic if its output increases as the binary input is incremented from one value to the next.
Another way to describe this is that the staircase output will have no downward steps as the binary input is
incremented from zero to full scale.

DAC Applications
DACs are used whenever the output of a digital circuit has to provide an analog voltage or current to drive
an analog device. Some of the most common applications are described in the following paragraphs.

Control
The digital output from a computer can be converted to an analog control signal to adjust the speed of a
motor or the temperature of a furnace, to control almost any physical variable.

Automatic Testing
Computers can be programmed to generate the analog signals (through a DAC) needed to test analog
circuitry. The test circuit’s analog output response will normally be converted to a digital value by an ADC
and fed into the computer to be stored, displayed, and sometimes analyzed.

Signal Reconstruction
In many applications, an analog signal is digitized, meaning that successive points on the signal are converted
to their digital equivalent and stored in memory. This conversion is performed by an analog-to-digital
converter (ADC). A DAC can then be used to convert the stored digitized data back to analog-one point at a
time-thereby reconstructing the original signal. This combination of digitizing and reconstruction is used in
digital storage oscilloscopes, audio compact disk systems, and digital audio and video recording.

Exercise
Multiple choice questions
a) Resolution of DAC is equal to the weight of
i) LSB
ii) MSB
iii) full scale output
iv) 1 volt.
b) When the binary input is all 0.s, ideally the output of a DAC will be?
i) Zero volt
ii) Full scale output voltage
iii) 1 volt
iv) One step voltage.
Questions for short answers
a) Define full scale error and offset error.
b) What is the advantage of R/2R ladder DAC over the DAC that
uses binary weighted resistors?
c) An 8-bit DAC has an output of 3.92 mA for an input of 01100010.
What are the DAC’s resolution and full-scale output?
d) What is the percentage resolution of an 8-bit DAC?
e) How many different output voltages can a 12-bit DAC produce?
f) Define full-scale error.
g) What is settling time?
h) Describe offset error and its effect on a DAC output.
Analytical questions
a) Describe the operation of a DAC.
b) What is the advantage of R/2R ladder DACs over those that use binary weighted resistors?
c) Discuss some of the DAC applications.

12.0 Analog-to-Digital Conversion

An analog-to-digital converter takes an analog input voltage and after a certain amount of time produces a
digital output code which represents the analog input. The A/D conversion process is generally more complex
and time-consuming than the D/A process. The techniques that are used provide and insight into what factors
determine an ADCs performance.

Several important types of ADC utilize a DAC as part of their circuitry. Figure 12.0 is a general block
diagram for this class of ADC. The timing for the operation is provided by the input clock signal. The control
unit contains the logic circuitry for generating the proper sequence of operations. The START COMMAND,
initiates the conversion process. The op-amp compactor has two analog inputs and a digital output that
switches states, depending on which analog input is greater.

The basic operation of ADCs of this type consists of the following steps:
1. The START COMMAND pulse initiates the operation.
2. At a rate determined by the clock, the control unit continually modifies the binary number that is
 stored in the register.
3. The binary number in the register is converted to an analog voltage, VAX, by the DAC.

Fig 12.0 Basic diagram of ADC

4. The comparator compares VAX with the analog input VA. As long as VAX < VA1 the comparator output
stays HIGH. When VAX exceeds VA by at least an amount = VT (threshold voltage), the comparator output
goes LOW and stops the process of modifying the register number. At this point, V AX is a close
approximation to VA. The digital number in the register, which is the digital equivalent of V AX, is also
the approximate digital equivalent of VA1 within the resolution and
accuracy of the system.
5. The control logic activates the end-of-conversion signal, EOC, when the conversion is complete.

12.1 Digital-Ramp ADC

One of the simplest versions of the general ADC of Fig. 12.1 uses a binary counter as the register and allows
the clock to increment the counter one step at a time until VAX _ VA. It is called a digital-ramp ADC because
the wave form at VAX is a step-by-step ramp (actually a staircase) like the one shown in Fig. 10. It is also
referred to as a counter-type ADC. Fig. 10 is the diagram for a digital-ramp ADC. It contains a counter, a
DAC, an analog comparator, and a control AND gate. The comparator output serves as the active-LOW end-
of-conversion signal (EOC). If we assume that VA, the analog voltage to be converted, is positive, the
operation proceeds as follows:

1. A START pulse is applied to reset the counter to zero. The HIGH at START also inhibits clock pulse
form passing through the AND gate into the counter.
2. With all 0’s at its input, the DAC’s output will be VAX = 0V.
3. Since VA > VAX, the comparator output, EOC, will be HIGH.
4. When START returns LOW, the AND gate is enabled and clock pulses get through to the counter.
5. As the counter advances, the DAC output, VAX, increases one step at a time as shown in Fig. 12.1
6. This continues unit VAX reaches a step that exceeds VA by an amount equal to or greater than VT
(typically 10 to 100 μV). At this point, EOC will go LOW and inhibit the flow of pulses into the counter
and the counter will stop counting.
 7. The conversion process is now complete as signaled by the HIGH-to-LOW transition at EOC, and the
contents of the counter are the digital representation of VA.
8. The counter will hold the digital value until the next START pulse initiates a new conversion

Fig. 12.1 Digital-ramp ADC.

Problem 8: Assume the following values for the ADC clock frequency = 1 MHz; V T = 0.1 mV; DAC has
F.S. output = 10.23 V and a 10-bit input. Determine the following values.
a. The digital equivalent obtained for VA = 3.728 V.
b. The conversion time.
c. The resolution of this converter.

Solution:
a. The DAC has a 10-bit input and a 10.23-V F.S. output. Thus, the number of total possible steps is 210
- 1 = 1023, and so the step size is;

10.23𝑉
= 10𝑚𝑉
1023

This means that VAX increases in steps of 10 mV as the counter counts up from zero. Since V A = 3.728 V
and VT = 0.1 mV, VAX has to reach 3.7281 V or more before the comparator switches LOW. This will
require.
3 7281V
= 372 81 = 373 steps
10𝑚𝑉

At the end of the conversion, then, the counter will hold the binary equivalent of 373, which is 0101110101.
This is the desired digital equivalent of VA = 3.728 V, as produced by this ADC.
 b. Three hundred seventy-three steps (373) were required to complete the conversion. Thus, 373 clock
pulses occurred at the rate of one per microsecond. This gives a total conversion time of 373 μs.
c. The resolution of this converter is equal to step size of the DAC, which is 10mV. In percent it is;

1
𝑥 100 ≈ 0.1%
1023

Problem 9
For the same ADC of problem 8 determine the approximate range of analog input voltages that will produce
the same digital result of 01011101012 = 37310.

Solution
Table 12 shows the ideal DAC output voltage, VAX, for several of the steps on and around the 373rd. If VA is
slightly smaller than 3.72 V (by an amount < VT),

Table 12 The Ideal DAC Output Voltage

Steps VAX (V)
371 3.71
372 3.72
373 3.73
374 3.74
375 3.75

Then EOC won’t go LOW when VAX reaches the 3.72-V step, but will go LOW on the 3.73-V step. If VA is
slightly smaller than 3.73 V (by an amount < VT), then EOC won’t go LOW until VAX reaches the 3.74-V
step. Thus, as long as VA is between approximately 3.72 V and 3.73-V, EOC won’t go LOW until VAX
reaches the 3.73-V step. The exact range of VA values is;

3.72 V - VT to 3.73 V – VT

but since VT is so small, we can simply say that the range is approximately 3.72 V to 3.73 V - a range equal
to 10 mV, the DAC’s resolution.

12.2 A/D Resolution and Accuracy

Resolution of the ADC is equal to the resolution of the DAC that it contains. The DAC output voltage V AX
is a staircase waveform that goes up in discrete steps until it exceeds VA. Thus, VAX is an approximation to
the value of VA, and the best we can expect is that V AX is within 10 mV of VA if the resolution (step size) is
10 mV. We can think of the resolution as being a built-in error that is often referred to as quantization error.
This quantization error, can be reduced by increasing the number of bits in the counter and DAC.

Problem 10
A certain 8-bit ADC has a full-scale input of 2.55 V (i.e., VA = 2.55 V produces a digital output of 11111111).
It has a specified error of 0.1% F.S. Determine the maximum amount by which the VAX output can differ
from the analog input.
Solution
The step size is 2.55 V/ (28 - 1), which is exactly 10 mV. This means that even if the DAC has no inaccuracies,
the VAX output could be off by as much as 10 mV because VAX. can change only in 10-mV steps; this is
the quantization error. The specified error of 0.1% F.S. is 0.1% × 2.55 V =
2.55 mV. This means that the VAX value can be off by as much as 2.55 mV because of component
inaccuracies. Thus, the total possible error could be as much as 10 mV + 2.55 mV =
12.55 mV.

12.3 Conversion Time, TC

The conversion time is the time interval between the end of the START pulse and the activation of the EOC
output. The counter starts counting from zero and counts up until V AX exceeds VA, at which point EOC goes
LOW to end the conversion process. It should be clear that the value of conversion time, to, depends on V A.
A larger value will require more steps before the staircase voltage exceeds VA.

The maximum conversion time will occur when V A is just below full scale so that VAX has to go to the last
step to activate EOC. For an N-bit converter this will be

tc (max) = 2N - 1 clock cycles

Sometimes, average conversion time is specified; it is half of the maximum conversion time.

𝑡𝑐(𝑚𝑎𝑥)
𝑡𝑐 ≈ 2𝑁−1 𝐶𝐿𝑂𝐶𝐾 𝐶𝑌𝐶𝐿𝐸𝑆
2

The major disadvantage of the digital-ramp method is that conversion time essentially doubles
for each bit that is added to the counter, so that resolution can be improved only at the cost of a longer tc.
Applications, however, the relative simplicity of the digital-ramp converter is an advantage over the more
complex, higher-speed ADCs.

12.4 Applications
Almost any measurable quantity present as a voltage can be digitized by an A/D converter and displayed.
A/D converters are the heart of digital voltmeters and digital MultiMate’s. Analog voice signals are converted
to digital form for transmission over long distances. At their destination they are reconverted to analog. In
digital audio record- the analog audio signal produced by a microphone is digitized (using an ADC), then
stored on some medium such as magnetic tape, magnetic disk or optical disk. Later the stored data are played
back by sending them to a DAC to reconstruct the analog signal, which is fed to the amplifier and speaker
system to produce the recorded sound.

13.0 Design of Microprocessor

When designing a new microprocessor or microcontroller unit, there are a few general steps that can be
followed to make the process flow more logically. These few steps can be further sub-divided into smaller
tasks that can be tackled more easily. The general steps to designing a new microprocessor are:

• Determine the capabilities the new processor should have.

• Lay out the datapath to handle the necessary capabilities.
• Define the machine code instruction format (ISA).
• Construct the necessary logic to control the datapath.

13.1 Determine Processor Capability

First thing one should ask before design a new processor element is why designing it at all. What new thing
would the ne processor do that existing processor cannot do? Keep in mind that it is always less expensive
to use an existing chip than to design and manufacture a new one.
We also need to ask ourselves whether the machine will support a wide array of instructions, or if it will have
a limited set of instructions. More instructions make the design more difficult, but make programming and
using the chip easier. On the other hand, having fewer instructions is easier to design, but can be harder and
costlier to program.

13.1.1 Lay out the basic arithmetic operations you want your chip to have:

• Addition/Subtraction
• Multiplication
• Division
• Shifting and Rotating
• Logical Operations: AND, OR, XOR, NOR, NOT,
etc.

List other capabilities that your machine has:

• Unconditional jumps
• Conditional Jumps (and what conditions?)
• Stack operations (Push, pop)
Once we know what our chip is supposed to do, it is easier to lay out the framework for our data path

13.1.2 Design the data path

Right off the bat we need to determine what ALU architecture that our processor will use:
• Accumulator
• Stack
• Register
• A combination of the above 3 (Accumulator, Stack and Register)

This decision, more than any other, is going to have the largest effect on your final design. Do not proceed
in the design process until you have made this decision. Once you have your ALU architecture, you create
your memory element (stack or register file), and you can lay out your ALU.

13.1.3 Instruction Set Design

Picking a particular set of instructions is often more an art than a science.
Historically there have been different perspectives on what makes a "good" instruction set.
• The early CISC years focused on making instruction sets that expert assembly language
programmers enjoyed programming – code density was a common metric.

• The early RISC years focused on making instruction sets that ran a few benchmark programs in C,
when compiled with relatively primitive compilers, really, really fast -- "cycles per instruction", and
later "instructions per cycle" was recognized as an important part of achieving low "time to run the
benchmark".
• The rise of multitasking operating systems (and shared-memory parallel processors) lead to the
discovery of non-blocking synchronization and the instructions necessary to support it.
• CPUs dedicated to a single application (ASICs or FPGAs) led to the idea of customizing the CPU
for one particular application
• The rise of viruses and other malware led to the recognition of the Popek and Goldberg virtualization
requirements.
•

13.2 Build control Logic

Once we have our datapath and our ISA, we can start to construct the logic of our primary control unit. These
units are typically implemented as a finite state machine, and we can try to map the ISA to the control unit
in a logical way.
Design the address path: Most processors have a very simple address path -- address bits come from the
PC or some other programmer-visible register, or directly from some instruction, and they are directly applied
to the address bus.
Many general-purpose processors have a more complex address path: user-level programs run as if they have
a simple address path, but the physical address applied to the address bus is significantly different than the
programmer-visible address. This enables virtual memory, memory protection, and other desirable features.

13.3 Programming Environment

Microcontrollers were originally programmed only in assembly language, but various high – level
programming languages, such as C, Python and JavaScript, are now also in common use to target
microcontrollers and embedded systems. Compilers for general purpose languages will typically have some
restrictions as well as enhancements to better support the unique characteristics of microcontrollers. Some
microcontrollers have environments to aid developing certain types of applications. Microcontroller vendors
often make tools freely available to make it easier to adopt their hardware.
Microcontrollers with specialty hardware may require their own non-standard dialects of C, such as SDCC
for the 8051, which prevent using standard tools (such as code libraries or static analysis tools) even for code
unrelated to hardware features. Interpreters may also contain nonstandard features, such as MicroPython,
although a fork, CircuitPython, has looked to move hardware dependencies to libraries and have the language
adhere to a more CPython standard.
Interpreter firmware is also available for some microcontrollers. For example, BASIC on the early
microcontrollers Intel 8052. BASIC and FORTH on the Zilog Z8 as well as some modern devices. Typically,
these interpreters support interactive programming (writing part of a program while it is already active).
Simulators are available for some microcontrollers. These allow a developer to analyze what the behavior of
the microcontroller and their program should be if they were using the actual part. A simulator will show the
internal processor state and also that of the outputs, as well as allowing input signals to be generated. While
on the one hand most simulators will be limited from being unable to simulate much other hardware in a
system, they can exercise conditions that may otherwise be hard to reproduce at will in the physical
implementation, and can be the quickest way to debug and analyze problems.
Recent microcontrollers are often integrated with on-chip debug circuitry that when accessed by an in-circuit
emulator (ICE) via JTAG (Industrial standard for verify designs and testing printed circuit board after
manufacture), allow debugging of the firmware with a debugger. A real-time ICE may allow viewing and/or
manipulating of internal states while running. A tracing ICE can record executed program and MCU states
before/after a trigger point.

13.4 Construction method of Microprocessor

The methodology of a system follows a definite pattern. The pattern followed to construct a system is not
restricted to a definite mode but rather, it is dependent on the designer’s choice of method. The approach
enables the designer to organize the different stages of the system and the components to be used in order to
achieve the desired aim.
Generally, there are two types of construction method which are normally employed by every designer. They
cannot be used together in one design but can be chosen alternatively. These methods includes - Top-down
design method and Down-top design method

Bottom-Up Method is a system design approach where the parts of a system are defined in details. Once
these parts are designed and developed, then these parts or components are linked together to prepare a bigger
component. This technique is repeated until the complete system is built. The advantage of Bottom-Up
technique is in making decisions at very low level and to decide the re-usability of components.
Top-Down Method is a system design approach where the design starts from the system as a whole. The
complete system is then divided into smaller sub-applications with more details.
Each part again goes through the top-down approach till the complete system is designed with all the minute
details. Top-Down approach is also termed as breaking a bigger problem into smaller problems and solving
them individually in recursive manner.
13.5 Difference between Bottom-Up Model and Top-Down Method
The following are the important differences between Bottom-Up Method and Top-Down Method

Ke Bottom-Up Method Top-Down Method

y

The focus is on identifying and resolving The focus is on breaking the bigger
Focus smallest problems and then integrating problem into smaller one and then
them together to solve the bigger problem. repeats the process with each problem.

It is mainly used by object oriented It is followed by structural programming

Language
programming languages like Java, C++ languages like C, Fortran etc.
etc.

It is better suited as it ensures minimum It has high ratio of redundancy as the

Redundancy data redundancy and focus is on re- size of project increases.
usability.

Have high interactivity between various Has tight coupling issues and low
Interaction
modules. interactivity between various modules.

Approach It is based on composition approach. It is based on decomposition approach.

Sometimes it is difficult to identify It may not be possible to break the

Issues
overall functionality of system in initial problem into set of smaller problems.
stages.

13.6 Testing of Microprocessors Control Systems

Traditional hardware self-test (resulted to functional testing which is a type of testing that seeks to establish
whether each application feature works as per the software or processor requirements) or built-in self-test
moves the testing task from external resources (ATE) to internal hardware, synthesized to generate test
patterns and evaluate test responses of the circuit under test. Hardware self-test achieves at-speed testing,
reducing the overall test costs of the microprocessor. Recent applications of hardware-based commercial
Logic built in self- test techniques in large industrial designs and microprocessors reveal that extensive and
manual design changes have to be performed in order to make the design built in self-test ready. These
include changes to prevent the design from getting to an unknown state that will corrupt the compressed
response and extensive test point insertion that is necessary to achieve acceptable fault coverage in random
pattern resistance circuits. However, these changes increase the circuit area and degrade its performance.
Therefore, Logic built in self-test has limited applicability to high-performance and power-optimized
embedded processors.

However, software based self-testing (SBST) approaches can be grouped together under the term software-
based self-testing (SBST) and various SBST techniques has seen as effective alternative to hardware self-
test for embedded processors. SBST has a nonintrusive nature since it utilizes existing processor resources
and instructions to perform self-testing. Therefore, SBST can potentially provide sufficient testing quality
without impact on performance, area, or power consumption during normal operation.

Fig. 13.0 Software-based self-testing concept outline

Self-test routines and data are downloaded into instruction and data memories, respectively, from a low-
speed, low-cost external mechanism. Subsequently, these self-test routines are executed at the processor
actual speed (at-speed testing) and test responses are stored back in the on-chip RAM. These test responses
may be in a compacted (self-test signatures) or uncompact form and can be unloaded by the low-cost external
ATE during manufacturing testing. Since today’s microprocessors have a reasonable amount of on-chip
cache, execution from the on-chip cache is considered a further improvement when targeting low-cost testers,
provided that a cache-loader mechanism exists to load the test program and unload the test response. As an
alternative, self-test routines may be executed from an on-chip ROM dedicated to this task when periodic
online testing is performed for the device.

Exercise
Multiple choice question
a) The number of total steps of a 9-bit ADC is,
i) 255
ii) 256
iii) 511
iv) 512.
Questions for short answers
a) What do you know about quantization error?
b) Define conversion time.
c) What is the major disadvantage of the digital ramp type ADC?
d) What is the function of the comparator in the ADC?
e) Where is the approximate digital equivalent of VA when the
conversion is complete?
g) What is the function of the EOC signal?
Analytical question
a) Draw digital ramp ADC and write down its operation.
Applications
b) A 10-bit DAC has a step size of 10 mV. Determine the full-scale output voltage and the percentage
resolution.