Rajasthan Technical University

8E4094
B.Tech. VIII Semester (Main/Back) Examination- 2013
Electronics and communication

8EC4.3 Microcontroller and Embedded Systems

Unit – I
Question 1
a) How can you differentiate 8051 microcontroller and 8085/8086 microprocessor? State
the various modes for timer in 8051 microcontroller.

The differentiation of microcontroller and microprocessor is given below:

Microprocessor (8051) Microcontroller (8085 or 8086)

Microprocessor is complete functional Microcontroller is complete functional
CPU i.e. it contains ALU, registers, microcomputer i.e. it contains the circuitry of
stack pointer, program counter, microprocessor and in addition it has built in
instruction decode and control unit and memory (ROM, RAM), I/O circuits and
interrupt processing circuits. peripherals necessary for an application.
Microprocessor instruction sets are data Microcontrollers have instruction sets that are
processing intensive, means powerful related to the control of inputs and outputs,
addressing modes and many instructions means they have many bit handling
to move data between memory and CPU instructions along with byte processing
to handle large volumes of data. instructions.
Microprocessor based products are Microcontroller based products are primarily
primarily designed to interact with designed to interact with machines; once a
humans and are more flexible to design system is designed they are less flexible.
Access times for external memory and Access times for on-chip memory and
I/O devices are more, resulting in a I/O devices are less, resulting in a faster
slower system. system.
Microprocessor based systems require Microcontroller based systems require less
support devices and are usually bulkier, external hardware, reducing PCB size and
costly, less reliable and consume more hence are compact, cheaper, more reliable and
power. consume less power.
Software protection is not possible Software protection is possible because of on-
because of the requirement of external chip code memory.
code memory.
The various modes for timer in the 8051 microcontroller are listed below:

Mode 0: 13 bit timer:

The description of timer mode 0 is given after mode 1
Mode 1: 16 bit timer/counter
In timer mode 1 the timer behaves as a 16 bit timer. Timer can be configured in mode 1 by
setting mode bits M1M0 in TMOD register as "01".Timer registers TLX and THX behaves as
eight bit up counters and collectively they form 16 bit up counter, allowing any value between
0000H to FFFFH to be loaded in these registers. In effect timer clock is divided by 256
(maximum) by TLX register and further it is divided by 256 (maximum) by THX register.

Mode 0: 13 bit timer

Timer mode 0 is similar to mode 1 except that it is 13 bit mode (8 bits of THX + lower 5 bits of
TLX). The timer mode 0 is kept in the 8051 only to maintain compatibility with previous version
of the microcontroller, the 8048 (MCS 48 family). It is rarely used in the 8051 based systems.

The timer clock pulses are given to TLX (only lower 5 bits are used in a mode 0) register. The
TLX register will work as 5 bit up counter i.e. the contents of TLX will be incremented by 1
after every timer clock pulse. The TLX register will divide (at maximum) the timer clock
frequency by 32 based on initial value present in it (the timer registers can be preloaded with any
value as per requirement). The output pulse from TLX is given to THX register, which will
further divide (at maximum) the clock pulse by 256. Therefore THX and TLX (lower 5 bits)
collectively behave as a 13 bit up counter. When the count in this 13 bit counter reaches
maximum value i.e. 8191 (1FFFH), the contents of the counter will roll back to 0000 and it will
set the timer overflow flag (TFX) and also generate the timer interrupt.

Mode 2; 8 bit auto reload

The timer mode 2 is an 8 bit timer with auto reload capability. The initial value loaded in THX
register is copied in to TLX register when timer is either started or every time TLX overflow
from FFH to 00H. The value in THX register remains unchanged. Mode 2 offers a simple way to
reduce the effect of overhead and automatically reloads the timer register when it overflows.
Mode 3; split timer mode

In mode 0, 1and 2 both timers may operate independently. But if mode 3 is selected for timer 0,
they can not operate independently.
Timer 0 in mode 3 behaves as two completely separate 8 bit timers, TL0 is an 8 bit interval
timer/event counter controlled by timer 0 control bits (C/ , GATE, TR0, TF0 and ) and
TH0 is only 8 bit interval timer controlled by timer 1 control bits TR1 and TF1 and therefore
controls the timer 1 interrupt. Timer mode 3 is also referred as split timer mode
Refer topic 14.4 “TIMER CIRCUITS AS AN INTERVAL TIMER” for more
details on the modes of the timer.

b) Draw the pin diagram of 8051 microcontroller explain the role of each pin in brief.

Alternate Alternate
function 8X51/52 function
P1.0 1 40 VCC
P1.1 2 39 P0.0 AD0
P1.2 3 38 P0.1 AD1
P1.3 4 37 P0.2 AD2
P1.4 5 36 P0.3 AD3
P1.5 6 35 P0.4 AD4
P1.6 7 34 P0.5 AD5
P1.7 8 33 P0.6 AD6
RST 9 32 P0.7 AD7
RXD P3.0 10 31 EA VPP
TXD P3.1 11 30 ALE PROG
INT0 P3.2 12 29 PSEN
INT1 P3.3 13 28 P2.7 A15
T0 P3.4 14 27 P2.6 A14
T1 P3.5 15 26 P2.5 A13
WR P3.6 16 25 P2.4 A12
RD P3.7 17 24 P2.3 A11
XTAL 2 18 23 P2.2 A10
XTAL 1 19 22 P2.1 A9
GND 20 21 P2.2 A8

VCC: Power supply pin

The 8051 operates at D.C. power supply of +5 V with respect to ground. The +5 V is to be
connected to pin VCC (Pin 40).
VSS: Ground
Pin 20 is the ground. The supply is connected with respect to ground pin.
XTAL1 and XTAL2: Oscillator pins
The 8051 has an internal (on-chip) oscillator circuit (partial circuit) which generates the clock
pulses which synchronizes all internal operations. The external resonant circuit is connected with
this on-chip oscillator circuit to make a complete oscillator. Normally quartz crystal and
capacitors are connected with XTAL 1 (pin19) and XTAL2 (pin18)

ALE/ : Address latch enable

When connecting the 8051 to external memory, port P0 provides both address and data i.e.
address and data are time multiplexed using P0 to save pins of the microcontroller. The ALE
(Address latch enable, Pin 30) is used for demultiplexing the address and data. ALE pulse
(ALE=1) indicates that the address is present on P0 and is used to enable external latch (normally
74LS373) which will store (and demultiplex) the address present on P0. Interfacing of external
latch and use of ALE is discussed in more detail in next section.

RST: Reset

Reset (Pin 9) is an active high input. When high pulse is applied to this pin, the microcontroller
will reset and terminates all activities and contents of all registers will be lost and default values
will be automatically loaded in to SFRs

: Program store enable

(Pin 29) is the active low output control signal used to activate (enable) external
ROM/EPROM/EEPROM. Thus, this signal acts as the read strobe (or output enable) to external
program memory

/ VPP: External access

Many members of the 8051 family have on-chip ROM. (Pin 31) is used for selection of on-
chip or off-chip ROM, =1 will tell the 8051 to read a program code from on-chip (internal)
ROM and is grounded ( =0) when a program code is totally contained in an external ROM
only. However, when = 1, any reference to program address which is outside the address
range of on-chip memory will automatically access external memory.

Port 0
Port 0 (P0) is an 8 bit open drain bidirectional I/O port, it occupies 8 pins (Pin 32-39). Since all
pins are open drain, to use P0 as an input or output, the external pull-up resistor of 10KΩ (value
greater than 1.42KΩ) must be connected with each pin

Port 1
Port 1 (P1) is an 8 bit bidirectional I/O port, (Pin 1-8) with internal pull-up resistors. When 1 is
written to port 1 latch, it is pulled high by internal pull-ups and can be used as an input.P1
receives low order address bytes during on-chip flash memory programming and program
verification process.
Port 2
Like P1, port 2 (P2) is also an 8 bit bidirectional I/O port, (Pin 21-28) with internal pull-up
resistors. Port 2 also act as a higher order address bus (A8-A15) while accessing external program
memory as well as access to external data memory that uses 16 bit address ( MOVX A,@DPTR
or MOVX @DPTR,A)
Port 3
As P1 and P2, Port 3 (P3) can act as 8 bit bidirectional I/O port, (Pin 10-17) with internal pull-up
resistors. Although it can be used as I/O port, it is more commonly used for alternate functions.
P3 provides special signals as external interrupt inputs, transmit (TXD) and receive (RXD) for
serial communication, timers external inputs (T0 and T1) and read, write signals.

Refer topic “11.2 THE 8051 PIN DESCRIPTION” for more details on 8051 pin
description.

OR
Question 1
a) Describe the architecture of 8051 microcontroller with help of a neat diagram.

The architectural block diagram of the 8051 is shown in the following figure; it shows
organization of all hardware components and data path connections between them. It includes 8
bit ALU along with Boolean processing capabilities, program and data memory, four 8 bit I/O
ports, two timers/counters, UART, timing and control circuits and oscillator circuit.
 PORT0 PORT2
DRIVERS DRIVERS

PORT 0 PORT 2 EPROM/

RAM
LATCH LATCH ROM

PROGRAM
ADDR.
REGISTER

ACC STACK POINTER

BUFFER
PCON SCON TMOD TCON

T2CON TL0 TH0 TH1

TMP2 TMP1
B TL1 TH2 TL2 RCAP2L PC
REGISTER INCREMENTER
RCAP2Z SBUF IE IP

ALU
INTERRUPT, SERIAL PORT AND
TIMER BLOCK PROGRAM
COUNTER
PSW
INSTRUCTION

ALE
REGISTOR

TIMING DPTR
AND
CONTROL
RST
PORT3
PORT1 LATCH
DRIVERS

OSC
PORT3
PORT1 DRIVER
DRIVERS

XTAL1 XTAL2 P3.0-P3.7

P1.0-P1.7

Figure: Block diagram of the 8051 microcontroller

ALU
Arithmetic and logic unit performs all arithmetic (addition, subtraction, multiplication and
division) and logical (AND, OR, NOT, EXCLUSIVE-OR and rotating) operations on 8 bit data
i.e. the 8051 has 8 bit ALU. The ALU also updates information about the nature of the result in
the flag register (PSW).
Memory
The 8051 family has separate on-chip program and data memory. The program instructions are
stored in a program memory (ROM/EPROM/EEPROM/Flash based on a faily member). The
amount and type of on-chip program memory is the key factor that differentiate all the members
of the family, for example, 80C51 has 4Kbytes of on-chip ROM, whereas 80C52 has 8Kbyte
(ROM) , 87C51 has 4Kbytes (EPROM) and 87C52 has 8Kbytes(EEPROM) of on-chip program
memory. Total program memory (including on-chip ROM) that can be connected with the 8051
is 64Kbytes. Similarly, data memory can be on-chip or off-chip. Internal data memory (RAM) in
80C51 is 128 bytes and in 80C52 is 256 bytes. There are also on-chip RAM locations which are
used to program and control various on-chip hardware peripherals and features of the 8051.They
are known as Special Function Registers (SFRs). These memories are discussed in detail in the
next section.
Peripherals
The 8051 has two 16 bit timers (8052 has three timers) that are used for timing and counting
applications. It has full duplex serial port (UART) to handle serial data transmission and
reception.
Timing and control unit
This unit generates all timing and control signals necessary for the execution of instructions and
synchronizes all internal activities with the clock.
Oscillator
The 8051 has an internal (on-chip) oscillator circuit (partial circuit) which generates the clock
pulses by which all internal operations are synchronized. The external resonant circuit is
connected with this internal on-chip oscillator circuit to make a complete oscillator. Normally
quartz crystal is used to make oscillator functional. Typically 12 MHz (or 11.0592MHz to
support standard baud rates for serial port) crystal is used.

Refer topic “2.1 THE 8051 ARCHITECTURE” and topic “2.2

POGRAMMING MODEL OF THE 8051” for more details on architecture of
the 8051.

b) Explain serial communication mode of 8051 microcontroller.

The 8051 has a built in UART, thus, the 8051 chip is capable of handling asynchronous
transmission and reception of serial data. The 8051 has two pins TXD (P3.1) and RXD (P3.0) for
transmission and reception of serial data respectively. The UART hardware is more commonly
referred as serial port.
Serial port of the 8051 is controlled by two registers: SBUF and SCON.

SBUF (serial data buffer)

It is an 8 bit register used for serial data transmission and reception. A data byte must be written
to SBUF for transmission through TXD pin. Same way, it also holds byte of data received from
RXD pin.
SCON - Serial control register

SCON is the control and status register programmed to configure bits contained in one serial
“word”, baud rate and synchronization clock source. It also contains status bits that indicate
whether data is transmitted completely, and any new data is received.

MODES OF OPERATION
UART can be configured to operate in one of the four operating modes selected by SM0 and
SM1 bits in the SCON register as discussed in previous section.

Mode 0 – 8 bit shift register mode

In a mode 0, data are transmitted and received through the RXD pin, and the TXD pin outputs
the shift clock and this is used to synchronize data transmission/reception. On transmit, the least
significant bit (LSB bit) is sent/received first. The operation of serial port in mode 0 is shown in
the following figure.

Figure: UART mode 0 operation

Mode 0 has a fixed baud rate which is 1/12 of the oscillator frequency.

Mode 1- Standard 8 bit UART mode

UART is designed for mainly for this mode and frame format of this mode is compatible with
COM port of PCs. This mode transmits 10 bits through TXD pin and receives through RXD pin
as follows: a START bit (always 0), 8 data bits (LSB first) and a STOP bit (always 1).
Programmer can set its transmission/reception rate using Timer 1.
Transmission: Data transmission begins by writing data to the SBUF register. The START and
STOP bits are added by hardware to form a 10 bit frame, then, 10 bit parallel to serial conversion
is performed and one bit (LSB first) at a time is transmitted through TXD pin, once complete
frame is transmitted, TI flag is set automatically by serial port hardware to indicate end of the
data transmission. We need to monitor TI flag to conform that SBUF register is not overloaded.
Reception: The data reception begins when REN=1 and high to low transition (start bit) is
detected on RXD pin. The received byte is loaded in to SBUF register (the START and STOP
bits are separated by UART hardware once complete frame is received) and stop bit in to RB8
(SCON bit 2) only if following two conditions are met.

i. RI=0, showing that previous data byte is read by a program

ii. Either SM2=0 or stop bit =1, Normally SM2 =0 and character will be accepted
irrespective of status of stop bit. A program may check RB8 to ensure that stop bit
is correct, if required.

If these two conditions are not met, received character is ignored and RI is not set and receiver
circuit waits for next start bit.

Timer1 is used to determine and generate baud rate for mode 1. Timer 1 is usually configured in
mode 2 as an auto reload 8 bit timer.

Mode 2- Multiprocessor communication

This mode transmits 11 bits through TXD pin and receives through RXD pin as follows: a
START bit (always 0), 8 data bits (LSB first), a programmable 9th data bit and a STOP bit
(always 1).When transmitting, the 9th data bit is the TB8 bit of the SCON register. When
receiving, the 9th data bit is stored into the RB8 bit of the SCON register.
Mode 2 has a fixed baud rate which is 1/64 of the oscillator frequency when SMOD = 0, and
1/32 of the oscillator frequency when SMOD = 1.

Mode 3

Mode 3 is the same as Mode 2 in all respects except the baud rate. The baud rate in Mode 3 is
variable and generated using timer 1 similar to mode1.

Refer topic “15.5 MODES OF OPERATION” for more details on serial

communication modes.

Unit-II
Question 2
a) Define and explain the addressing modes of 8051 microcontroller.

The way by which source or destination (usually source) operands are specified in an instructions
is called addressing mode.
The addressing modes of the 8051 are listed as follows:

1. Immediate addressing
2. Register addressing
3. Direct addressing
4. Indirect addressing
 Register indirect addressing
 Indexed addressing

1. Immediate addressing mode

The data (constant) is specified as a part of instruction in a program memory. The data is
available immediately as a part of instruction itself, therefore immediate addressing is very fast.
However, since the data is fixed, at run time it is not flexible. The instructions using an
immediate operand have an 8 bit or 16 bit number following the op-code. For example,

MOV A, #data // load 8 bit immediate data in to Accumulator

MOV A, #55H // A= 55H

MOV Rn,#data // load 8 bit immediate data into Rn

MOV R3, #0FFH // R3= FFH

MOV DPTR, #data16 // load 16-bit number into DPTR

MOV DPTR, #2000H // DPTR=2000H

2. Register addressing mode

In register addressing mode, the operands are specified by register names. Register A and R0 to
R7 may be named as a part of the instruction mnemonic. The advantage of register addressing
mode is that it occupies only one byte memory, and is fast because only on-chip registers are
accessed i.e. instruction takes only one machine cycle for execution. For example,

MOV A, Rn // copy contents of register Rn to Accumulator

MOV A, R2 // If R2=10H →A=10H

MOV Rn, A // copy contents of Accumulator to register Rn

MOV R1, A // If A=20H →R1=20H

3. Direct addressing mode

The data is accessed directly from the memory address specified as one of the operand i.e. one of
the operand is an 8-bit address for internal RAM location. Internal RAM includes 128 byte of
RAM from (00H-7FH) and any special function register. It is more flexible compared to
immediate and register addressing because the value to be accessed from address may be
variable. These are 2 byte instructions (3 bytes when source and destination are both direct
addresses). The address refers to either byte location or a specific bit in a bit addressable byte.
For example,

MOV A, direct // copy data from (contents of) address direct in to A

MOV A, 10H // If address 10H contains data 50H i.e (10H)=50H→ A=50H

MOV direct, A // copy data from A to address direct

MOV 10H, A // If A=44H→ (10H)= 44H

MOV Rn, direct // copy data from address direct in to register Rn

MOV R5, 80H // If (80H)= FFH→R5= FFH

MOV direct, Rn // copy data from Rn to address direct

MOV 50H, R3 // R3=10H →(50H)= 10H

MOV direct, #data // load 8 bit immediate data in to address direct

MOV 0A0H, #20H // (A0H) = 20H

MOV direct1, direct2 // copy data from address direct2 to address direct1
MOV 50H, 83H // If (83H)=10H→ (50H)=10H

4. Indirect addressing mode

The data is specified indirectly in an instruction i.e. address of the data (rather than data itself) is
specified as one of the operand. Here, the register holds the address that contains the data i.e. the
number in the register is treated as an pointer to address. Indirect addressing mode is the most
flexible and useful in array operations. There are two types of indirect addressing in the 8051

Register indirect addressing mode: The register indirect addressing uses only register R0 or R1
to hold address of the data in internal RAM, these two registers are also referred to as pointer
registers or simply pointers. The symbol @ is used along with R0 or R1 to indicate indirect
addressing. For example,
MOV @Ri, #data // load constant value in to address contained in Ri
MOV @R0, #30H // If R0=40H, → (40H)=30H

MOV @Ri, direct // copy data form address direct to address Ri

MOV @R1, 10H // If (10H)=50H, R1=15H→ (15H)=50H

MOV direct, @Ri // copy data from address in Ri to address direct

MOV 10H, @R1 // If R1=50H, (50H)=15H→ (10H)=15H

MOV @Ri, A // copy data from A to address in Ri

MOV @R0, A // If A=50H, R0=15H→ (15H)=50H
MOV A, @Ri // copy data from address in Ri to A
MOV A, @R1 // If R1=50H, (50H)=15H→ A=15H

Indexed addressing mode: Two registers are used to form the address of the data. The contents
of either DPTR or PC are used as a base address and the A is used as index (or offset) address.
The final address is formed by adding these two registers. It results in a forward reference of 0 to
255 bytes from the base address. They are used to access only program memory (internal as well
as external)
Indexed addressing is used to access data tables (lookup tables) from the program memory and
implementing jump tables. They are also suitable for multidimensional array operations.
The instructions are:
MOVC A, @A+PC // copy data (or code) byte from program memory address formed by
//addition of contents of A and PC into A

MOVC A, @A+DPTR// copy data (or code) byte from program memory address formed by
// addition of contents of A and DPTR into A

Refer topic “4.2 ADDRESSING MODES” for more details and examples of
the addressing modes.

b) Write a program of 8051 microcontroller to find the sum of 10 numbers stored is an

array. Draw the flow chart to specify the steps of the design flow.

Assume that the array of 10 numbers is stored at internal RAM address 20H onwards

ORG 0000H
CLR C
CLR A
MOV R4, #00H // clear R4H to store upper byte of result
MOV R0, # 20H // load address of label START in the R0
MOV R2, # 10 // N numbers
NEXT: ADD A, @R0 // add array elements with A
JC AHEAD
SJMP SKIP
AHEAD: INC R4 // if C=1, increase upper byte of result
SKIP: INC R0 // next array element
DJNZ R2, NEXT // check all numbers are added
MOV R5, A // store lower byte of result in R5
HERE: SJMP HERE
 END

OR
Question 2
a) Explain the following instruction giving the proper format and explain of each.

DAA
Function: Decimal-adjust Accumulator after Addition
It is used after addition of BCD numbers (packed BCD) to convert (adjust) the result in to BCD
form.
ADD or ADDC instruction may have been used to perform the addition. The result is adjusted in
following conditions.
i) Lower nibble of A is greater than 9 after addition
ii) AC=1 after addition
iii) Upper nibble of A is greater than 9 after addition
iv) C=1 after addition

Example:
i) When lower nibble greater than 9 after addition
28 BCD 0010 1000
+ 12 BCD 0001 0010
40 BCD 0011 1010 3A; lower nibble is greater than 9(Invalid BCD)
+ 0000 0110 add 6 to lower nibble (DA A will do it)
0100 0000 40 BCD, desired result

MOV A, #28H // A=28H

ADD A, #12H // A=3AH (Invalid BCD)
DA A // A=40 (Desired BCD result)

ii) When AC=1 after addition,

28 BCD 0010 1000
+ 19 BCD 0001 1010
47 BCD 0100 0001 41; AC is 1 after addition(Invalid result)
+ 0000 0110 add 6 to lower nibble (DA A will do it)
0100 0111 47 BCD, desired result

MOV A, #28H // A=28H

ADD A, #19H // A=41H (Invalid result)
DA A // A=47H (Desired BCD result)

SWAP
Function: Swap nibbles within Accumulator
It swaps the nibbles of Accumulator i.e. it interchange the upper nibble with lower nibble. This
operation is equivalent to 4 bit rotation in either left or right direction. The operation of swap
instruction is illustrated in figure given below,

CALL & RET

Call instruction is used to jump on subroutine and at last statement, RET for return to the return
address.

There are two types of CALL instruction in the 8051: ACALL and LCALL
ACALL: It calls subroutine located at the specified address within 2Kbyte page with respect to
PC. The instruction automatically saves address of the next instruction (address of instruction
itself +2) onto the stack (low byte first) and increments the stack pointer by two. The new value of
PC (destination address) is obtained by combining the five bits of the PC (PC15 through PC11),
opcode bits 7 through 5, and the second byte of the instruction. The program execution is then
transferred to new value of PC.

Format
ACALL addr 11 or Label // SP=SP+1;(SP)=PCL; SP=SP+1; (SP)=PCH; PC10-0= addr 11
Bytes: 2 Cycles: 2
LCALL:
It calls subroutine located at the specified address within entire 64K program memory. The
instruction automatically saves address of the next instruction (address of instruction itself +3)
onto the stack (low byte first) and increments the stack pointer by two. The new value of PC
(destination address) is obtained by loading second and third bytes of the LCALL instruction in
to PC lower byte and PC higher byte respectively. The program execution is then transferred to
new value of PC. Refer topic 7.3 for more details.
Flags affected: None
LCALL addr 16 or Label // SP=SP+1;(SP)=PCL; SP=SP+1; (SP)=PCH; PC= addr 16
Bytes: 3 Cycles: 2
RET:
It is used to return to main program from subroutine which was called by ACALL or LCALL
instruction. It pops (retrieves) two bytes from top of stack (return address) in to PC and SP is
decremented by two. The program execution continues at the return address, usually the
instruction immediately following an ACALL or LCALL.
Flags affected: None
RET // PCH=(SP); SP=SP-1; PCL=(SP);SP=SP-1 Bytes: 1 Cycles: 2

Rotate instruction
Rotate operations are useful for monitoring bits of a data byte without using logical test. The
status of bits may be used in decision making process for certain applications.
The 8051 has four different rotate instructions as described in the following section.
Rotate accumulator left by one bit
RL A // rotate A one bit position to the left, bit D0 to D1, bit D1 to D2, …, bit D6 to D7 and bit
D7 to D0 as illustrated in the following figure.

Figure: RL A instruction
Rotate accumulator right by one bit
RR A // rotate A one bit position to the right, bit D0 to D7, bit D7 to D6, …, bit D2 to D1 and
bit D1 to D0 as illustrated in the following figure.

Figure: RR A instruction
Rotate accumulator left through carry by one bit
RLC A // rotate A one bit position to the left through carry flag, bit D0 to D1, bit D1 to
D2, …, bit D6 to D7, bit D7 to CY and CY to D0 as illustrated in the following
figure.

Figure: RLC A instruction

Rotate accumulator right through carry by one bit
RRC A // rotate A one bit position to the right through carry flag, bit D0 to CY, CY to D7,
bit D7 to D6, …, bit D2 to D1 and bit D1 to D0 as illustrated in the following
figure.

Figure: RRC A instruction

b) Write a program of 8051 microcontroller and draw the flow chart to count the number
of zeros in a number.

ORG 0000h
MOV 3FH,#0FFH // Number Stored in 3FH
MOV A,3FH
CLR C
MOV R1,#8
AGAIN: RLC A
JC COUNT
INC R0
COUNT: DJNZ R1,AGAIN
HERE: SJMP HERE
END
Unit-III
Question 3
a) Describe the interrupt used in 8051 microcontroller give their priority and addresses.

Five interrupts are available in the 8051.Three of them are internal interrupts i.e. they are
generated because of internal operation of the 8051. They are timer 0 (TF0), timer1 (TF1) and
serial port (TI or RI) interrupts. Remaining two are external interrupts and i.e. they
are invoked by external signals given to pins and . The bar over INT0 and INT1
indicate that they are active low interrupt inputs. The external interrupts and are also
referred as IE0 and IE1 respectively. For each interrupt source there is a fixed location in a
program memory that contains its interrupt service routine (ISR). This part of memory which
stores the ISRs is called the interrupt vector table. It is shown in the following Table.
Table: Interrupt vector table of the 8051

Interrupt source Interrupt Interrupt Interrupt

vector type flag clearing
 External interrupt 0 ( ) 0003H External Auto*
Timer 0 interrupt (TF0) 000BH Internal Auto
External interrupt 1 ( ) 0013H External Auto*
Timer 1 interrupt (TF1) 001BH Internal Auto
Serial port interrupt (TI or RI) 0023H Internal By program
* For edge triggered external interrupts only.
When any interrupt is generated (or asserted), it forces the microcontroller to jump to fixed
address in vector table. For example when INT0 is asserted, microcontroller will automatically
jump to memory address 0003H, similarly for timer1 interrupt, it will jump to address 001BH in
interrupt vector table. Since program execution is transferred to fixed location corresponding to
each interrupt source, the interrupts in the 8051 are also referred as vectored interrupts.

Interrupt source Priority

External interrupt 0 ( ) Highest
Timer interrupt 0 (TF0)
External interrupt 1( )
Timer interrupt 1(TF1)
Serial port Interrupt (RI or TI) Lowest

b) Draw the format of timer control register (TCON) and describe it.
TCON register

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

MSB LSB

Bit Symbol Description

7 ( TCON.7) TF1 Timer 1 overflow flag; Set to 1(by hardware) when timer 1
overflows; Cleared to 0 automatically when controller vectors to
interrupt service routine at address 001BH.
6 ( TCON.6) TR1 Timer 1 run control bit; set to 1 by a program to start
timer/counter 1; Cleared to 0 to stop timer/counter 1.
5 ( TCON.5) TF0 Timer 0 overflow flag; Set to1 (by hardware) when timer 0
overflows; Cleared to 0 automatically when controller vectors to
interrupt service routine at address 000BH
4 ( TCON.4) TR0 Timer 0 run control bit; Set to 1 by a program to start
timer/counter 0; Cleared to 0 to stop timer/counter 0.
3 ( TCON.3) IE1 External interrupt 1 edge flag; Set by hardware when external
interrupt is detected on pin; Cleared by hardware when
controller vectors to interrupt service routine at address 0013H
only when interrupt is configured as an edge triggered interrupt
(see IT1 bit below)
2 ( TCON.2) IT1 External Interrupt 1 signal type control bit; set to 1 by a program
to configure interrupt 1 as a edge triggered (falling edge); cleared
to 0 to configure it as level triggered (low level)
1 ( TCON.1) IE0 External interrupt 0 edge flag; Set by hardware when external
interrupt is detected on pin; Cleared by hardware when
controller vectors to interrupt service routine at address 0003H
only when interrupt is configured as an edge triggered interrupt
(see IT0 bit below)
0 ( TCON.0) IT0 External Interrupt 0 signal type control bit; set to 1 by a program
to configure interrupt 0 as a edge triggered (falling edge); cleared
to 0 to configure it as level triggered (low level)

OR
Question 3
a) 8051 microcontroller is most suitable for real time operation. Justify this statement.

The 8051 is suitable for real time operations because of the following features:

Four register banks- R0 to R3

These register banks provides faster and easier way for context switching and retrieving while
handling the interrupt service routines and subroutines. To speed up the process of context
saving (or switching), switch the register bank, which relieves the program form saving the
registers R0 to R7. This is one of the major reason for providing register banks in the 8051.

When the instructions uses register addressing modes (R0-R7), the instructions executes faster
because the access time of these registers is less (registers are present within the 8051)

Flexible and powerful interrupt structure

Five interrupts are available in the 8051.Three of them are internal interrupts i.e. they are
generated because of internal operation of the 8051. They are timer 0 (TF0), timer1 (TF1) and
serial port (TI or RI) interrupts. Remaining two are external interrupts and i.e. they
are invoked by external signals given to pins and . The bar over INT0 and INT1
indicate that they are active low interrupt inputs. The external interrupts and are also
referred as IE0 and IE1 respectively. For each interrupt source there is a fixed location in a
program memory that contains its interrupt service routine (ISR). This part of memory which
stores the ISRs is called the interrupt vector table

The interrupt provides the following advantages that helps in real time operation:

 The time of microcontroller is efficiently used as there is no wastage of time in

continuous and unnecessary monitoring.

 Priorities can be given to different devices as per their importance and higher priority
device may be programmed to interrupt lower priority devices.

 It makes system faster because more important activities are handled immediately.

 More number of devices can be served (though, only one device at a time)

Bit addressability
The 8051 has unique and powerful feature of single bit addressability and single bit operations.
It contains a complete Boolean (single bit) processor and its instruction set is optimized for the
single-bit operations. It supports SET, CLEAR, COMPEMENT, AND and OR single bit
operations. This feature makes the 8051 one of the most obvious choice for real-time machine
control applications.
Bit processing operations provide the following advantages that will help in real time operation.

 Faster execution of a program.

 Less memory required by a program.

b) Explain Timer/Counter of 8051 microcontroller in detail.

TIMERS IN THE 8051

The 8051 has two 16 bit timers: Timer 0 and Timer 1, which can be programmed independently.
Each timer can be configured either as interval timer or as an event counter in various operating
modes. Timer 0 has two 8 bit registers, namely TL0 (lower byte) and TH0 (higher byte),
collectively used as a 16 bit register. Similarly timer 1 has TL1 and TH1 registers.

The timer mode control (TMOD) register is used to configure both timers in to various operating
modes and the timer control (TCON) register is used to control start/stop operations and also has
the overflow status flags of both timers in it.
TMOD (Timer mode control) register
TMOD is 8 bit special function register dedicated to both timers. The lower 4 bits configure the
timer 0 and upper 4 bits configure the timer 1. The bit assignment of the TMOD is shown in the
following Table.
Table: TMOD register

Timer 1 Timer 0
GATE C/ M1 M0 GATE C/ M1 M0
MSB LSB

Bit Symbol Description

7/3 Gate Start/stop control using hardware or software. When Gate=0, start/stop of
timer is controlled only by TR1/0 bits; While Gate=1, it is controlled by
TR 1/0 as well as signal on pin
6/2 C/ C/ =0 configures timer as a interval timer (or time delay generator),
C/ =1 will configure timer as event counter
5/1 M1 Mode select bit 1
4/0 M0 Mode select bit 0
M1 M0
0 0 Mode 0;13 bit timer
0 1 Mode 1; 16 bit timer/counter
1 0 Mode 2; 8 bit auto reload
1 1 Mode 3; split timer mode, TL0 as 8 bit timer/counter and
TH0 as 8 bit timer controlled by control bits of timer 0 and
timer 1 respectively. Timer 1 operation timer/counter
stopped.

TCON register: Refer Table 14.2 for details

Timers can be configured to work as an interval timer and event counter. They can be operated in
four modes.

Mode 0: 13 bit timer:

Mode 1: 16 bit timer/counter
Mode 2: 8 bit auto reload
Mode 3: split timer mode

The timer (as interval timer) mode 1 is discussed below:

In timer mode 1 the timer behaves as a 16 bit timer. Timer can be configured in mode 1 by
setting mode bits M1M0 in TMOD register as "01".Timer registers TLX and THX behaves as
eight bit up counters and collectively they form 16 bit up counter, allowing any value between
0000H to FFFFH to be loaded in these registers. In effect timer clock is divided by 256
(maximum) by TLX register and further it is divided by 256 (maximum) by THX register. The
operation of timer mode 1 is shown in the following figure.
As shown in the figure, the internal oscillator is the clock source for the timer operation (clock
source is selected by C/ = 0). The oscillator signal is divided internally by 12, therefore the rate
of timer clock is one pulse per machine cycle. Once timer is started by making TR0/1 =1, the
timer clock pulses are given to TLX (TL0 for timer 0 and TL1 for timer 1) register. The TLX
register will work as 8 bit up counter i.e. the contents of TLX will be incremented by 1 after
every clock pulse. The TLX register will divide (at maximum) the timer clock frequency by 256
based on initial value present in it (the timer registers can be preloaded with any value as per
requirement). The output pulse from TLX is given to THX register, which will further divide (at
maximum) the clock pulse by 256. Therefore THX and TLX collectively behave as a 16 bit up
counter. When the count in this 16 bit counter reaches maximum value i.e. 65535, the contents of
the counter will roll back to 0000 and it will set timer overflow flag (TFX) and also generate a
timer interrupt.

Figure: Timer mode 1 operation

Operation of timer in mode 1
The exact value to be loaded in TLX and THX registers depend on amount of time delay
required and crystal frequency. It is discussed in the next topic, once the 16 bit value is loaded,
timer can be started by instruction "SETB TR0" for T0 and SETB TR1 for T1 (or their
equivalent instructions, see example 14.3. Upon starting the timer, it starts to count up at every
timer clock pulse, and continues until it reaches maximum value FFFFH, and on the next pulse it
rolls over to 0000H.This event of roll over from FFFFH to 0000H is popularly referred as "timer
overflow". This timer overflow set TF (Timer overflow) flag to 1 and interrupt of timer is
generated (if enabled) indicating that specified time interval is elapsed or required time delay is
completed.
The timer overflow flag can be monitored using software or it may generate interrupt when TF
flag is raised to inform the microcontroller core that the timer has completed its work and
required action has to be taken. The timer should be stopped by instruction CLR TRX (or
equivalent instructions, see example 14.3) when it overflows. It should be noted that both timers
have their own timer overflow flag, TF0 for timer0 and TF1 for timer 1.
To repeat the process of time measurement or delay generation, TLX and THX must be reloaded
with original value and TFX flag must be cleared to 0 and timer is started again by setting TRX
bit.
Timer as event Counter

The major difference between interval timer and event counter is source of the clock pulse, when
timers are used as an event counters, pin T0/T1 (P3.4/P3.5) are basically used to provide external
pulses for timer 0/1, therefore external pulses will increment the timer registers TLX and THX.
The timer can be configured as an event counter by setting C/ = 1 in TMOD register. The other
difference between interval timer and event counter is that counter is normally started with initial
value of “0000” so TLX and THX normally initialized with value 00H. The operation of event
counter is illustrated in the following figure.

Figure: Event counter operation

As shown in the figure, the pulses on external pin T0 (or T1 for timer 1) are selected as clock
source for the timer operation by setting C/ = 1 in TMOD register. The timer registers are
normally initialized with value 0000 and the count will increment by 1 when pulse on pin T0/1 is
applied, therefore, the circuit will count the number of pulses (events) applied externally to the
timer pins. The count in timer registers at any time will represent the number of pulses applied
(or external events occurred) till that time.

Unit-IV
Question 4
a) Interface external program memory with 8051 microcontroller and explain how the
data is transmitted.
The 8051 has 16 address lines, therefore it has 64Kbytes of program memory address space.
As discussed in the topic 21.4.2, of the microcontroller is normally connected with
of program memory (ROM) to access code bytes. is generated either when program
memory is accessed by ‘MOVC’ instructions or during program byte fetches. It may also be
connected with (chip enable) of memory chip if only one ROM chip is present in a
system. Interfacing of 16 Kbyte ROM is shown in figure 21.10. Since the chip capacity is
 16K bytes, address range will be from 0000H to 3FFFH. It will require 14 (214=16K) address
lines.

__ _____
EA PSEN
___
OE
___
CE *
A8-A13 A8-A13
6

ALE
27128
(16K x 8)
EPROM
74LS373
AD7-AD0 A7-A0
Latch A7-A0

D7-D0
8 D7-D0

* CE may be permanently grounded when

there is only one memory chip

Interfacing of 16K x 8 EPROM with the 8051

should be generated using address decoder circuit when there is more than one ROM
chips present in a system.
Note that A14 and A15 are not connected. These pins are not used and left unconnected,
because there is no requirement of address decoder since there is only one ROM chip
connected at address 0000H to 3FFFH. The disadvantage of this is that each memory
location will have four addresses. is connected to ground because only external code
memory is used. 74LS373 is 8 bit latch used to demultiplex lower address and data bus. ALE
signal is used to enable the latch when address is present on the lower address/data (AD7-
AD) bus.

b) Interface 4-digit 7-segment LED to 8051 microcontroller and write the assembly
language program to display 1234 on it.
 ORG 0000H

:1234 = 06H,5BH,4FH,66H

REPEAT: MOV A, #06H ; display ‘1’ first

MOV P0, A ; send "1” code to Port 0
SETB P2.0 ; enable 7-seg
ACALL DELAY
CLR P2.0

MOV A, #5BH ; display ‘2’

MOV P0, A ; send "2" code to Port 0
SETB P2.1 ; enable 7-seg
ACALL DELAY
CLR P2.1

MOV A, #4FH ; display ‘3’

MOV P0, A ; send "3" code to Port 0
SETB P2.2 ; enable 7-seg
ACALL DELAY
CLR P2.2

MOV A, #66H ; display ‘4 ‘

MOV P0, A ; send "4" code to Port 0
SETB P2.3 ; enable 7-seg
ACALL DELAY
CLR P2.3
 SJMP REPEAT

DELAY: MOV R5,#10 ; delay

THERE2: MOV R6,#255
THERE1: NOP
DJNZ R6,THERE1
DJNZ R5,THERE2
RET
END

OR
Question 4
a) Draw and explain the interfacing of ADC 0804 to 8051 microcontroller.

The interfacing diagram of the ADC 080X with the 8051 is shown in figure 19.2. Power on reset
and clock circuit of the 89C51 is not shown for simplicity. Port 2 of microcontroller is
configured as an input and connected with digital output (D7-D0) pins of ADC. Control signals
are connected with port 1 pins as shown in figure. VIN (-) of ADC is grounded, therefore
effective analog input voltage is voltage applied at Vin (+) pin. Here input voltage is applied
through potentiometer (by varying the value of resistor the input voltage can be varied between 0
to 5 V). In real life, input voltage is applied from transducer and signal conditioning circuit. Self
clocking is (internal oscillator) is used by connecting R and C as shown in figure 19.2, for the
values used, clock frequency is 606 KHz and conversion time is 110us. Note that VREF/2 pin is
open, therefore, analog input range is 0 to 5 V.
Interfacing ADC 080X with 8051

Handshaking process between microcontroller and ADC 0804 chip

The steps to develop the program of data conversion is understood by following steps,

 The conversion is going to start by these steps: make and simultaneously low, the
ADC will remain in a reset state until the and inputs remain low. Conversion will
start when one (or both) of these inputs make a low to high transition.

 Monitor the ‘end of conversion’ ( ) pin until it becomes 0, when it is 0, it indicates that
conversion is completed.

 To read data from ADC, make and low, this will output data on D7 –D0 pins, read this
data using appropriate instruction (read port to which digital output is connected). When
is made low, will become high automatically. Remember that the port should be
configured as an input.

b) Draw and explain the parallel I/O ports interface.

Refer topic 13.1 The 8051 ports for the detailed discussion on Parallel I/O ports interface.