LBS MCA CRASH COURSE 2025

Computer Architecture:
Foundations and Structure

This presentation covers

digital logic,
computer block structure,
I/O communication,
and interrupts.

Understanding these concepts boosts

computer performance and
efficiency.
 What is Computer Architecture?

It is the design and structure of the components of a computer

Describes how the CPU, memory, input/output devices interact

Helps understand how software and hardware work together
Like the "blueprint" for building and running a computer

Computer Architecture decides the instruction set, data types, memory addressing
—it’s what the programmer sees.

Computer Organization is about the physical circuits and components like

the ALU, buses, and control units that execute those instructions.”

“In short:
Architecture = What the computer does.
Organization = How the computer does it.”
 Basics of Digital Logic

Computers use binary digits (0 and 1) to store and process data

Digital logic circuits are used to perform logical operations

Basic components:

Logic Gates: Perform simple logical operations

Combinational Circuits: Output depends only on current inputs

Sequential Circuits: Output depends on current and past inputs (memory involved)
 NOT Gate
In a NOT gate, the output of a NOT gate attains state 1 if and only if the input does not attain state 1
The Boolean expression is Y=A’
.
A NOT A

0 1

1 0

OR Gate
In an OR gate, the output of an OR gate attains state 1 if one or more inputs attain state 1
.The Boolean expression of the OR gate is Y = A + B

A B A OR B
0 0 0
0 1 1
1 0 1
1 1 1

AND Gate
In the AND gate, the output of an AND gate attains state 1 if and only if all the inputs are in state 1.
The Boolean expression of AND gate is Y = A.B
A B A AND B

0 0 0

0 1 0

1 0 0

1 1 1
 NOR Gate
This gate is the combination of OR and NOT gates.
The Boolean expression of the NOR gate is

A B A NOR B

0 0 1

0 1 0

1 0 0

1 1 0

NAND Gate
This basic logic gate is the combination of AND and NOT gates.
The Boolean expression of the NAND gate is

A B A NAND B

0 0 1

0 1 1

1 0 1

1 1 0
 🔧 Universal Gates: Why They Are
Called "Universal"

Universal gates are logic gates that can

be used to construct any other logic
gate (AND, OR, NOT, XOR, etc.).
The two universal gates are NAND and
NOR.
They are called universal because a
complete digital system can be built XOR gate using NOR gate
using only NAND or only NOR gates.
These gates form a functionally
complete set, meaning they can
replicate the behavior of all other basic
gates.
📌 Example: You can create a NOT gate
using a single NAND gate by connecting
both its inputs together.
 Exclusive-OR gate (XOR Gate)
In an XOR gate, the output of a two-input XOR gate attains state 1 if one adds only input and attains state 1
The Boolean expression of the XOR gate is.

A B A XOR B

0 0 0

0 1 1

1 0 1

1 1 0

Exclusive-NOR Gate (XNOR Gate)

In the XNOR gate, the output is in state 1 when both inputs are the same, that is, both 0 or both 1
The Boolean expression of the XNOR gate.

A B A XNOR B

0 0 1

0 1 0

1 0 0

1 1 1
 Combinational and Sequential Circuits
Before diving into circuit types, let's understand how we got here:
🔹 From Logic Gates to Digital Circuits
Basic logic gates (AND, OR, NOT) are the building blocks of all digital systems.
Just like alphabets form words, gates are combined to form logic expressions.
By combining gates in different ways, we build circuits that can make decisions
or store information.

These combinations give rise to two main categories of digital circuits:

🔸 Combinational Circuits:
Output depends only on current inputs
No memory element
Examples:
Adders, Subtractors,
Multiplexers, Demultiplexers,
Encoders, Decoders
🔸 Sequential Circuits:
Output depends on current input + previous states
(i.e., they have memory)
Use flip-flops as storage elements
Examples:
Latches, Flip-Flops,
Counters,
Shift Registers,
Finite State Machines
🔍 Comparison Table: Combinational vs Sequential Circuits
Feature Combinational Circuits Sequential Circuits
Memory No Yes

Output depends on Current inputs Current inputs + previous state

Feedback path No Yes

Basic components Logic gates Logic gates + flip-flops

Clock requirement Not required Required

Examples Adder, Encoder, Decoder Counter, Shift Register, FSM

Application focus Logic calculation Timing, state-based operations

 FLIP FLOP

These are basic memory elements used in sequential circuits

They store one bit of data
and require a clock signal for their operation,
making their operations slower compared to purely combinational logic.

The flip flop is a circuit that maintains a state until directed by input to change the state.
A basic flip-flop can be constructed using 4 NAND or 4 NOR gates, popularly known as-
basic digital memory circuit.

TYPE OF FLIP-FLOPs

SR flip-flop
JK flip-flop
D flip flop
T flip-flop
 🔸 Encoder, Decoder, Multiplexer, Demultiplexer
These are key combinational circuits used in digital systems:

✅ Definitions:
Encoder: Converts 2ⁿ input lines into n-bit output.
Decoder: Converts n-bit input to 2ⁿ output lines.
Multiplexer (MUX): Selects one of many inputs and forwards it to a single output line.
Demultiplexer (DEMUX): Takes a single input and routes it to one of many outputs.

🔍 Comparison Table:
Feature Encoder Decoder Multiplexer (MUX) Demultiplexer (DEMUX)
Binary input → single high Select 1 input among Send input to selected
Purpose Input → binary output
output many output

Input Lines 2ⁿ n bits Multiple One

Output Lines n bits 2ⁿ One Multiple

Control Lines No No Yes (Selection) Yes (Selection)

Example Keyboard Encoder 7-segment Display Decode 8-to-1 Multiplexer 1-to-8 Demultiplexer
Multiplexer & Demultiplexer
.
 Block Structure of a Computer
Main Components:

Input Unit – Devices that send data to the computer (keyboard, mouse)

Central Processing Unit (CPU) – The brain of the computer

ALU (Arithmetic Logic Unit): Performs calculations
Control Unit: Manages the execution of instructions
Registers: Small, fast memory for temporary data

Output Unit – Devices that show results (monitor, printer)

Memory Unit – Stores data and instructions (RAM/ROM)

Primary memory
Secondary memory
Memory Hierarchy

Registers: Fastest, smallest (inside

CPU)

Cache Memory: Small but faster

than RAM

RAM (Main Memory): Holds active

data/programs

Hard Drive/SSD: Permanent storage

Processor and I/O Communication
CPU and I/O devices need to exchange data

Communication Methods:
Programmed I/O
CPU controls and checks I/O device status
Slows down CPU (polling)
Interrupt-Driven I/O
I/O device interrupts CPU only when needed
CPU can do other tasks in the meantime
DMA (Direct Memory Access)
Device transfers data directly to memory
CPU is not involved in data transfer
 What is an Interrupt?
An interrupt is a signal that temporarily stops CPU's current activity
CPU saves current state, handles the interrupt (e.g., keyboard press), then resumes
Like raising your hand in class – temporarily getting attention

Types of Interrupts
Hardware Interrupts
Caused by external devices (keyboard, mouse, timer)
Maskable
Can be disabled (masked) by software (e.g., INTR in 8086)
Non-maskable
Cannot be disabled;
used for critical tasks like power failure
Software Interrupts
Generated by programs (errors, system calls)
Normal
Exception
Interrupt Vector Table:
List of memory addresses of interrupt service routines
For example let us take a task that involves two activities :

1. Perform some computation

2. Print the result
Repeat the above two steps several times in theprogram,
let the program contain 2 routines COMPUTE and PRINT routine.

Method #1 : The COMPUTE routine passes N lines to the PRINT routine and the PRINT routine then
prints the N lines one by one on a printer. All this time the COMPUTE routine keeps on waiting and
does not do anything useful.

Method #2 : • The COMPUTE routine passes N lines to the PRINT routine. The PRINT routine then sends
one line to the printer and instead of printing that line it execute itself and passes the control to the
COMPUTE routine . The COMPUTE routine continuous it activity, once the line has been printed the
printers sends an interrupt to the processor of the computer. At this point the COMPUTE routine is
suspended and the PRINT routine is activated and the PRINT routine send second line to the printer so
that the printer can keep on printing the lines and the process continues.
 INTERRUPT SERVICE ROUTINE AND IT’S WORKING
The routine that gets executed when an interrupt request is made is called as interrupt service routine.

Step 1: When the interrupt occurs the

processor is currently executing i’th
instruction and the program counter will be
currently pointing to (i + 1)th instruction.
Step 2: When the interrupt occurs the
program counter value is stored on the
processes stack.
Step 3: The program counter is now loaded
with the address of interrupt service
routine.
Step 4: Once the interrupt service routine is
completed the address on the processes
stack is pop and place back in the program
counter.
Step 5: Execution resumes from(i + 1)th line
of COMPUTE routine
 ✅ Interrupts: Overview
Interrupts break the normal sequence of instruction
execution.
When an interrupt occurs, the CPU diverts execution to a
special routine called the ISR (Interrupt Service Routine).
After ISR execution, control returns to the main program.
CPUs with the ability to handle multiple devices interrupting
simultaneously are said to support multiple interrupt
processing.
 🔄 Direct Memory Access (DMA) – Summary
DMA allows high-speed data transfer between I/O device and memory without CPU involvement.
A DMA Controller (DMAC) handles the data transfer:
Sends memory addresses and control signals
Increments address for block transfer
Processor initiates DMA by giving:
Starting address
Number of words
Direction of transfer
After completion, DMAC sends an interrupt to inform the processor.
During DMA, the CPU can run another program.
OS manages the switching between programs and DMA operations.
🧠 8086 Interrupt Pins:
NMI (Non-Maskable Interrupt): Cannot be disabled; high priority; associated with type 2 interrupt
INTR (Interrupt Request): Can be disabled using Interrupt Flag (IF); lower priority
INTA (Interrupt Acknowledge): Signal sent by processor in response to INTR

NMI Actions:
Completes current instruction
Pushes flags, CS, and IP onto stack
Loads new IP from address 000AH, resets IF and TF
INTR Actions:
Completes current instruction
Activates INTA and receives interrupt type
Pushes flags, CS, IP
Loads IP from Type × 4, CS from next word
Resets IF and TF

📌 Note:
If IF = 0 → No INTR interrupt is served
If IF = 1 → CPU ready to respond
After handling an INTR, IF is reset
To serve future INTRs, IF must be re-enabled
 🔹 Software Interrupts in 8086
Generated by executing INT instruction in program (e.g., INT 21H)
256 software interrupts: INT 00H to INT FFH
2-byte instruction
ISR addresses are stored from 0000H to 03FFH

Type Purpose
0 Division by zero
1 Single-step debug
2 NMI – power failure
3 Breakpoint
4 Overflow interrupt
5-31 Reserved for advanced use

🔹 ISR (Interrupt Service Routine)

Each interrupt must have a corresponding ISR
Address of ISR stored in Interrupt Vector Table (IVT)
IVT contains 256 vectors (4 bytes each = CS:IP)
IVT located at 0000H to 03FFH (first 1024 bytes)
 🔹 8259 – Programmable Interrupt Controller (PIC)
Increases number of interrupts a processor can handle
Developed by Intel, also known as priority interrupt controller
Does not handle the ISR itself – just forwards the interrupt
Can manage 8 interrupts (with cascading, up to 64)
Can mask/unmask individual interrupts

Feature Meaning

Handles 8 interrupts Can connect to 8 different I/O devices

Cascading (up to 64) Can be connected with other PICs to manage 64 devices

Priority-based Decides which interrupt is more important

Mask/unmask interrupts Can enable or disable (mask) individual interrupts

Doesn’t run the ISR Just sends the signal to CPU — CPU handles the rest
 🔹 Definitions (8085/8086)
Vectored Interrupt: ISR address is fixed and known to processor
Non-Vectored Interrupt: ISR address is given by the device

🔹 8085/8086 Interrupts
8085 has 5 interrupts: TRAP, RST7.5, RST6.5, RST5.5, INTR
TRAP is non-maskable, others are maskable
INTR is non-vectored (ISR address given by device)
Others are vectored (ISR address known to processor)

Interrupt Type Priority Maskable? Vectored?

TRAP Non-maskable Highest ❌ No ✅ Yes
RST 7.5 Maskable High ✅ Yes ✅ Yes
RST 6.5 Maskable Medium ✅ Yes ✅ Yes
RST 5.5 Maskable Low ✅ Yes ✅ Yes
INTR Non-vectored Lowest ✅ Yes ❌ No
 ✅ 8085 Microprocessor – At a Glance
Developed by Intel in 1977
It’s an 8-bit microprocessor — meaning it can handle 8 bits of data at a time
Built using NMOS technology
Comes in a 40-pin Dual Inline Package (DIP)

Feature What It Means in Simple Words

8-bit Data Bus It can move 8 bits of data in or out at a time

16-bit Address Bus Can access up to 64 KB of memory (2¹⁶ = 65,536)

16-bit Program Counter (PC) Keeps track of the address of the next instruction to execute

16-bit Stack Pointer (SP) Points to the top of the stack in memory (used for temporary storage)

6 General Registers Named B, C, D, E, H, L — used to store values temporarily

Accumulator (A) An 8-bit register used in math, logic, and I/O operations

Temporary Register Used internally during operations (not directly accessible)

Flag Register Holds results of operations — like carry, zero, negative, etc.

Instruction Register & Decoder Loads instructions from memory and figures out what to do
 ✅ 8086 Microprocessor – At a Glance
Developed by Intel in 1978
It’s a 16-bit microprocessor – can process 16 bits of data at a time
Made using HMOS technology
Comes in a 40-pin DIP package
Contains 29,000+ transistors
Maximum clock speed: 5 MHz

Mode Use Case Explanation

Minimum Mode For single-processor systems Used when only one CPU is present
Maximum Mode For multiprocessor systems Used when multiple CPUs share the system

Feature What It Means

16-bit ALU Performs arithmetic and logic operations on 16-bit data
16-bit Internal/External Buses Can carry 16 bits of data inside and outside the chip
General Purpose Registers AX, BX, CX, DX – used for storing data and intermediate results
Special Registers Segment Registers (CS, DS, SS, ES) – manage memory segmentation
Pointers & Index Registers SP, BP, SI, DI – used for stack handling and memory operations
 🔹 8237 / 8257 – DMA Controller
Allows data transfer between memory and I/O without 🔹 8253 / 8254 – Timer / Counter
CPU Solves timing control issues in microprocessor systems
Used for high-speed data transfer Contains 3 independent 16-bit counters
Uses control signals: Applications:
HOLD: Request DMA action Time delay generation
HLDA: Acknowledge DMA action Event counting
HOLD has higher priority than INTR or NMI Baud rate generation
RESET has the highest priority
8237: Sends memory/I/O control signals
8257: 4-channel DMA controller Feature 8253 8254
Technology NMOS HMOS
🔹 8255 – Programmable Peripheral Interface Clock 0–2.6 MHz 0–10 MHz
Has 3 8-bit bidirectional I/O ports (A, B, C)
Read-back Not available Available
Used for parallel data transfer with slow peripherals
Works with ADC, DAC, LCD, keyboards, 7-segment displays, etc.
Can operate in various I/O modes (simple I/O, interrupt I/O)

Feature What It Means in Simple Terms

3 ports: A, B, C (8-bit each) You get 3 input/output ports, each 8 bits wide

Bidirectional Data can go in or out from any port

Programmable You can set which ports are used for input or output

Works in different I/O modes - Simple input/output- Interrupt-driven I/O for faster response
 Instruction Cycle Overview
1. Fetch instruction from memory
2. Decode the instruction
3. Execute the instruction using ALU or
control unit
4. Store the result (if needed)

Interrupts can occur between steps

Chip No. Category Function Summary

8051 Microcontroller 8-bit MCU with built-in timers, serial port, I/O ports, and interrupts
8156 Timer + I/O Has a timer and 2 I/O ports
8251 Serial Communication USART — for serial data transmission
8253 Timer/Counter 3 independent counters
8255 I/O Interface Connects CPU with keyboard, LEDs, LCD, etc. (24 I/O pins)
8257 DMA Controller Direct Memory Access: memory ↔ I/O transfer
8259 Interrupt Controller Handles multiple interrupts
8279 Keyboard/Display Control Manages keyboard matrix and 7-segment display
LBS MCA CRASH COURSE 2025

Thank You! 😊