A Course in

Digital logic and

design
CS102

Prepared by
Prof. Safwat Ahmed Aly

2023
 Chapter (1)

Logic Gates
Introduction

The individual memory cells used in computers are bistable in

operation (pendulous between 1 and 0) and capable of storing a
single binary bit. Therefore, it is most practical to use the
binary number system that uses only two basic symbols 0
and 1 to represent numbers. Binary logic is used to describe, in
mathematical way, the manipulation and processing of binary
information. Binary logic consists of binary variables and
logic operations. The binary variables are letters of the
alphabet such as X, A, D . . . etc. Each variable has two
possible values, 0 or 1. The basic logic operations are the three
operations OR, AND, and NOT.

Gates
A gate is represented by an electronic circuit which operates
on one or more input signals to perform the logic operation
and produce an output signal. Some types of gates like OR,
AND, NOT, NOR, NAND gates. All gates have a block diagram
symbol.
The lines connected to each symbol are the inputs on the left
and the output on the right of it.

Truth table
A truth table is a two-dimensional array where there is
one column for each input and one column for each output (a
circuit may have more than one output). Since we are
dealing with binary values, each input can be either 0 or
1.The number of truth table possibilities are 2n where n is
the number of input variable. For example, if n=2 the
number of possibilities are 22=4.
The values in the output column are determined from
applying the corresponding input values to the functional
operator. For example, in the following truth table:

2
 X Y F=(X.Y)
0 0 0
0 1 0
1 0 0
1 1 1

A logic gate is an electronic circuit/device which makes the logical

decisions. To arrive at this decisions, the most common logic gates used
are OR, AND, NOT, NAND, and NOR gates. The NAND and NOR gates
are called universal gates. The exclusive-OR gate is another logic gate
which can be constructed using AND, OR and NOT gate.

Logic gates have one or more inputs and only one output. The
output is active only for certain input combinations. Logic gates are the
building blocks of any digital circuit. Logic gates are also called switches.
With the advent of integrated circuits, switches have been replaced by
TTL (Transistor Transistor Logic) circuits.

Gates Types
AND OR
NOT NAND
NOR BUF
XOR XNOR

AND Gate
The AND gate performs logical multiplication, commonly known as
AND function. The AND gate has two or more inputs and single output.
The output of AND gate is HIGH only when all its inputs are HIGH (i.e.
even if one input is LOW, Output will be LOW). The AND-gate is a
device whose output is logic (1) if both of the inputs are logic (1). It
performs logical multiplication. It composed of two or more inputs

3
and single output. The logical AND function of two variables is
represented either by writing dot between the two variables or by
writing the adjacent letters without dot. For example, X . Y = Z or XY =
Z is read "X AND Y is equal to Z". This AND gate symbol and its
truth table are shown in figure below respectively, with two inputs
marked A and B and one output marked X.

Three Input AND Gate

Since we have already seen how a AND gate works and I will just list the
truth table of a 3 input AND gate. The figure below shows its symbol and
truth table.

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Truth Table

X Y Z F=X.Y.Z
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1

OR Gate
The OR gate performs logical addition, commonly known as OR
function. The OR gate has two or more inputs and single output. The
output of OR gate is HIGH only when any one of its inputs are HIGH
(i.e. even if one input is HIGH, Output will be HIGH).
If A and B are two inputs, then output X can be represented
mathematically asX = A+B. Here plus sign (+) denotes the OR operation.
Truth table and symbol of the OR gate is shown in the figure below.

Three Input OR gate

The figure below shows the truth table of a 3-input OR gate and its

5
symbol.

Truth Table
X Y Z F=X+Y+Z
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
NOT Gate
The NOT gate performs the basic logical function called inversion or
complementation. NOT gate is also called inverter. The purpose of this
gate is to convert one logic level into the opposite logic level. It has one
input and one output. When a HIGH level is applied to an inverter, a
LOW level appears on its output and vice versa.
If A is the input, then output X can be represented mathematically
as X= Ā, (-) denotes the NOT (inversion) operation. Truth table and
NOT gate symbol is shown in the figure below.
Symbol

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NAND Gate
NAND gate is a cascade of AND gate and NOT gate, as shown in the
figure below. It has two or more inputs and only one output. The output
of NAND gate is HIGH when any one of its input is LOW (i.e. even if
one input is LOW, Output will be HIGH).

NAND From AND and NOT

If A and B are two inputs, then output X can be represented
mathematically as X = (A.B)', Here dot (.) denotes the AND operation
and (') denotes inversion. Truth table and symbol of the NAND gate is
shown in the figure below.
Symbol

Truth Table
A B F=(A.B)'
0 0 1
0 1 1
1 0 1
1 1 0

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NOR Gate (inverter)
The NOR gate (NOT–OR) is equivalent of an inverted OR function and
will yield a low output (0) if either or both inputs are high (1).
Symbolically the NOR gate is represented by the OR gate symbol
followed by a bubble to represent the complemented output signal.
The NOR gate is a universal building block of a digital logic
because it may be used to implement any logic function. The truth table
and NOR gate can be represented by the symbol shown in fig below.

From the three basic logic gates (AND, OR, and NOT gates), the most
powerful computer circuit can be made. Furthermore, these basic
gates are built using transistors, the fundamental building blocks for
all digital logic circuits. Transistors are just electronic binary
switches that can be turned on or off. The on and off states of
transistors are used to represent the two binary values 1 and 0.

Exclusive-OR ( XOR) Gate

An Exclusive-OR (XOR) gate is gate with two or three or more inputs
and one output. The output of a two-input XOR gate assumes a HIGH
state if one and only one input assumes a HIGH state. This is equivalent
to saying that the output is HIGH if either input X or input Y is HIGH

8
exclusively, and LOW when both are 1 or 0 simultaneously. In general,
an XOR gate gives an output value of 1 when there are an odd number of
1's on the inputs to the gate.
If X and Y are two inputs, then output F can be represented
mathematically as F = X Y, Here denotes the XOR operation. X Y
and is equivalent to X.Y' + X'.Y. Truth table and symbol of the XOR gate
is shown in the figure below.
XOR From Simple gates

Symbol

Truth Table
X Y F=(X Y)
0 0 0
0 1 1
1 0 1
1 1 0

9
Example
Draw the truth table for a three –input XOR gate with input A , B, and C.
For a 3-input XOR gate with inputs , and the truth table is given
by

0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

Exclusive-NOR (XNOR) Gate

An Exclusive-NOR (XNOR) gate is gate with two or three or more inputs
and one output. The output of a two-input XNOR gate assumes a HIGH
state if all the inputs assumes same state. This is equivalent to saying that
the output is HIGH if both input X and input Y is HIGH exclusively or
same as input X and input Y is LOW exclusively, and LOW when both
are not same. In general, an XNOR gate gives an output value of 1 when
there are an even number of 1's on the inputs to the gate.
If X and Y are two inputs, then output F can be represented
mathematically as F = X Y, Here denotes the XNOR operation. X Y
and is equivalent to X.Y + X'.Y'. Truth table and symbol of the XNOR
gate is shown in the figure below.

01
Symbol

Truth Table

X Y F=(X Y)'
0 0 1
0 1 0
1 0 0
1 1 1

Example
Draw the truth table for a three –input XOR gate with input A, B, and C?
For a 3-input XNOR gate with inputs , and the truth table is
given by

0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0

00
Example: Prove that
Solution

Example :

02
Question
What would the output pulse train at the output, Y, look like if the input
at C is always 1?

Answer
The gate in the circuit is a NAND gate and so gives 0 at the output when
all the inputs are 1 and gives 1 at the output otherwise. Therefore the
output will be:
a=0;b=1;c=1;d=0;e=1;f=0;g=1

Precedence of operations
Thus in the expression AB+A‟B‟, the variables in the second term are
complemented before being ANDed together. That term is then ORed
with the ANDed combination of A and B (the AB term)

Draw the circuit diagrams for the following

– f(a,b,c)=(a‟+b)c

03
 – f(a,b,c)=a‟b+c

Problem
Draw the logical diagrams for the following Boolean expressions:
(a) Y=A‟B‟+B(A+C).

(b) Y=BC+AC‟.

04
 (c) Y=A+CD.

(d) Y=(A+B)(C‟+D).

Universal Gates
Universal gates are the ones which can be used for implementing any gate
like AND, OR and NOT, or any combination of these basic gates; NAND
and NOR gates are universal gates. But there are some rules that need to
be followed when implementing NAND or NOR based gates.
To facilitate the conversion to NAND and NOR logic, we have two new
graphic symbols for these gates.
NAND Gate

NOR Gate
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Realization of logic function using NAND gates
Any logic function can be implemented using NAND gates. To achieve
this, first the logic function has to be written in Sum of Product (SOP)
form. Once logic function is converted to SOP, then is very easy to
implement using NAND gate. In other words any logic circuit with AND
gates in first level and OR gates in second level can be converted into a
NAND-NAND gate circuit.
Consider the following SOP expression
F = W.X.Y + X.Y.Z + Y.Z.W

The above expression can be implemented with three AND gates in first
stage and one OR gate in second stage as shown in figure.

If bubbles are introduced at AND gates output and OR gates inputs (the
same for NOR gates), the above circuit becomes as shown in figure.

06
Now replace OR gate with input bubble with the NAND gate. Now we
have circuit which is fully implemented with just NAND gates.

07
Implementing an Inverter Using only NAND Gate
The figure shows two ways in which a NAND gate can be used as an
inverter (NOT gate).
1. All NAND input pins connect to the input signal A gives an output A'.

2. One NAND input pin is connected to the input signal A while all other
input pins are connected to logic 1. The output will be A'.

Realization of logic function using NOR gates

Any logic function can be implemented using NOR gates. To achieve
this, first the logic function has to be written in Product of Sum (POS)
form. Once it is converted to POS, then it's very easy to implement using
NOR gate. In other words any logic circuit with OR gates in first level
and AND gates in second level can be converted into a NOR-NOR gate
circuit.
Consider the following POS expression:
F = (X+Y) . (Y+Z)

The above expression can be implemented with three OR gates in first

stage and one AND gate in second stage as shown in figure.

08
If bubble are introduced at the output of the OR gates and the inputs of
AND gate, the above circuit becomes as shown in figure.

Now replace AND gate with input bubble with the NOR gate. Now we
have circuit which is fully implemented with just NOR gates.

09
Implementing an Inverter Using only NOR Gate
The figure shows two ways in which a NOR gate can be used as an
inverter (NOT gate).

1. All NOR input pins connect to the input signal A gives an

output A'.

2. One NOR input pin is connected to the input signal A while all other
input pins are connected to logic 0. The output will be A'.

Equivalent Gates:
The shown figure summarizes important cases of gate equivalence. Note
that bubbles indicate a complement operation (inverter).

1- A NAND gate is equivalent to an inverted-input OR gate.

2- An AND gate is equivalent to an inverted-input NOR gate.

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3- NOR gate is equivalent to an inverted-input AND gate.

4- An OR gate is equivalent to an inverted-input NAND gate.

5- Two NOT gates in series are same as a buffer because they cancel each
other as A‟‟ = A.

We will show that SOP forms can be implemented using only NAND
gates, while POS forms can be implemented using only NOR gates. This
is best explained through examples.

Example 1
Implement the following SOP function using NAND gates only
F = XZ + Y’Z + X’YZ
Solution

20
By associating one of the inverters with the output of the first level AND
gate and the other with the input of the OR gate, it is clear that this
implementation is reducible to 2-level implementation where both levels
are NAND gates as shown in the figure.

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Example 2
Implement the following POS function using NOR gates only
F = (X+Z) (Y’+Z) (X’+Y+Z)
Solution

By associating one of the inverters with the output of the first level
OR gates and the other with the input of the AND gate, it is clear that this
implementation is reducible to 2-level implementation where both levels
are NOR gates as shown in Figure.

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Problems
1. Derive the truth table and draw the logic circuits which correspond to
the following expressions:
a) F= A'BC' + A'BC + AB'
b) F= XY'Z + X'Y'Z + XYZ
C) F= (A.B)' + (A'.B)
d) F= (A.B)'.(A'+B)
e) F= (A+B').(A+B)'
f) F= (A.B)'.(A'+B)+B'
g) F= AB + A'B' + A'B
h) F= A'BC+ A'BC' +AB'
k) F= XY'(Z+Y') + X'Z
l) F= [A(B+C') + A'B]C

2. Which the logic expression corresponds to the following logical

circuit:
(a)

(b)

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(c )

(d)

(e)

25
 Chapter (2)
Boolean Algebra
The most obvious way to simplify Boolean expressions is to
manipulate them in the same way as normal algebraic expressions are
manipulated. With regards to logic relations in digital forms, a set of rules
for symbolic manipulation is needed in order to solve for the unknowns.
A set of rules formulated by the English mathematician George
Boole describe certain propositions whose outcome would be either true
or false. With regard to digital logic, these rules are used to describe
circuits whose state can be either, 1 (true) or 0 (false). In order to fully
understand this, the relation between the AND gate, OR gate and NOT
gate operations should be appreciated. Boolean algebra: based on a set of
rules derived from a small number of basic assumptions i.e. Boolean
Postulates (axioms).
Boolean Postulates:
 P1: X = 0 or X = 1
 P2: 0.0=0
 P3: 1+1=1
 P4: 0+0=0
 P5: 1.1=1
 P6: 1.0=0.1=0
 P7: 1+0=0+1=1
Laws of Boolean Algebra
• 1a 0·0=0
• 1b 1+1=1
• 2a 1·1=1

26
 • 2b 0+0=0
• 3a 0·1=1·0=0
• 3b 1+0=0+1=1
• 4a If x=0 then x' =1
• 4b If x=1 then x'=0

Single-Variable theorems
• From the axioms are derived some rules for dealing with single
variables
• 5a x·0=0
• 5b x+1=1
• 6a x·1=x
• 6b x+0=x
• 7a x·x=x
• 7b x+x=x
• 8a x·x'=0
• 8b x+x'=1
• 9 x''=x
• Single-variable theorems can be proven by perfect induction. Substitute
the values x=0 and x=1 into the expressions and verify using the basic
axioms
Two & three variable properties
• 10a. x·y=y·x Commutative
• 10b. x+y=y+x
• 11a. x·(y·z)=(x·y)·z Associative
• 11b. x+(y+z)=(x+y)+z
• 12a. x·(y+z)=x·y+x·z Distributive
• 12b. x+y·z=(x+y)·(x+z)

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• 13a. x+x·y=x Absorption
• 13b. x·(x+y)=x edundance Law
• 14a. x·y+x·y‟=x Combining
• 14b. (x+y)·(x+y')=x
• 15a. (x·y)‟=x‟+y' DeMorgan‟s
• 15b. (x+y)'=x‟·y' Theorem
• 16a. x+x'‟·y=x+y
• 16b. x·(x'+y)=x·y
Consensus theorem

Note that every law has two expressions, (a) and (b). This is known as
duality. These are obtained by changing every AND(.) to OR(+), every
OR(+) to AND(.) and all 1's to 0's and vice-versa.
Prove (xy)'=x'+y' (DeMorgan’s Theorem)
X y xy (xy)' X' Y' X'+y'
0 0 0 1 1 1 1
0 1 0 1 1 0 1
1 0 0 1 0 1 1
1 1 1 0 0 0 0

Then (xy)' equivalent x'+y'

prove x+x'·y=x+y
X y X' y x+x' y x+y
0 0 0 0 0
0 1 1 1 1
1 0 0 1 1
1 1 0 1 1

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Then x+x'·y equivalent x+y
Algebraically:
x+x'·y = x.1 + x'·y ( using 6a )
= x( 1+y) + x'·y ( using 5b )
=x +xy + x'·y
= x + y(x + x' ) ( using 8b )
= x+y
Proof (algebraic manipulation)
• Prove
– (X+A)(X‟+A)(A+C)(A+D)X = AX
– (X+A)(X‟+A)(A+C)(A+D)X
– (X+A)(X‟+A)(A+CD)X (using 12b)
– (X+A)(X‟+A)(A+CD)X
– (A)(A+CD)X (using 14b)
– (A)(A+CD)X
– AX (using 13b)
Duality
• Axioms and single-variable theorems are expressed in pairs – Reflects
the importance of duality
• Given any logic expression, its dual is formed by replacing all + with ·,
and vice versa and replacing all 0s with 1s and vice versa
– f(a,b)=a+b dual of f(a,b)=a·b
– f(x)=x+0 dual of f(x)=x·1
• The dual of any true statement is also true
Duality principle:
• States that a Boolean equation remains valid if we take the dual of the
expressions on both sides of the equals sign.
• The dual can be found by interchanging the AND and OR operators

29
along with also interchanging the 0‟s and 1‟s.
• This is evident with the duals in the basic identities.
• For instance: DeMorgan‟s Law can be expressed in two forms

Inversion of a function
• If a function is defined as
– f(x1, x2)= x1+ x2
• Then the complement of f is
– f(x1, x2)= x1+ x2 = (x1+ x2)‟
• Similarily, if
– f(x1, x2)= x1 · x2
• Then the complement of f is
- f(x1, x2)= x1 · x2= (x1 · x2)‟

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Problem:
Reduce the following Boolean expressions to the less number of literals:
(a) A‟C‟ + ABC + AC‟
(b) (x‟y‟+z)‟ + z + xy + wz
(c) A‟B(D‟+C‟D) + B(A+A‟CD)
(d) (A‟+C)(A‟+C‟)(A+B+C‟D)

30
Solution:
(a) A‟C‟ + ABC + AC‟=
= A‟C‟ + AC‟ + ABC
= C‟(A‟+ A) + ABC
= C‟∙1 + ABC
= C‟ + ABC
= (C‟+ AB)(C‟+C) [distributive]
= AB + C‟

(b) (x‟y‟+z)‟ + z + xy + wz
= (x‟y‟+z)‟ + z + wz + xy
= (x‟y‟+z)‟ + z(1+ w) + xy
= (x‟y‟+z)‟ + z + xy
= (x + y)z‟ + z + xy [DeMorgan]
= (z + (x + y)) ∙ (z + z‟) + xy [distributive]
= (z + (x + y)) ∙ 1 + xy
= x + y + z + xy
=x+y+z [absorption]

(c) A‟B(D‟ + C‟D) + B(A+A‟CD)

= A‟BD‟ + A‟BC‟D + AB+ A‟BCD
= A‟BD(C+C‟)+ A‟BD‟+ AB
= A‟BD+ A‟BD‟+ AB
= A‟B(D+D‟)+ AB
= A‟B+ AB
= B(A‟+ A)
=B

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(d) (A‟+C)(A‟+C‟)(A+B+C‟D)
= (A‟+C)(A‟+C‟)(A+B+C‟D)
= (A‟ + CC‟)(A + B + C‟D)
= A‟(A + B + C‟D)
= A‟A + A‟B + A‟C‟D
= A‟B + A‟C‟D = A‟(B + C‟D)
Canonical Forms
The functionality of any logic circuit can be expressed in one of
two alternative and equivalent canonical forms. These canonical
forms consist of a Boolean algebraic expression. They are
generally developed from a truth table.

The minterm form

Known as the first canonical form, this a pure OR combination of
minterms (m) where a minterm is an AND function that includes each
variable once in its normal or complemented form. The first canonical
form is also known as the sum of products (SOP). The Sum of Products
form represents an expression as a sum of minterms.
F(X, Y, ...) = Σ m ( )
To derive the Sum of Products form from a truth table, OR together
all of the minterms which give a value of 1.

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The maxterm form
Known as the second canonical form, this a pure AND
combination of maxterms (M) where a maxterm is an OR
function that includes each variable once in its normal or
complemented form. The second canonical form is also known
as the product of sums (POS). The Product of Sums form
represents an expression as a product of maxterms.
F(X, Y, .......) = π M( )
To derive the Product of Sums form from a truth table, AND
together all of the maxterms which give a value of 0.
The construction of these forms is best illustrated by the examples below.

Example: The Minterm Form

Consider the truth table below for the output F from a combinatorial logic
circuit comprising three inputs, X, Y and Z

X Y Z F minterm Designation
0 0 0 1 X'.Y'.Z' mo
0 0 1 0 X'.Y'.Z m1
0 1 0 0 X'.Y.Z' m2
0 1 1 1 X'.Y.Z m3
1 0 0 0 X.Y'.Z' m4
1 0 1 0 X.Y'.Z m5
1 1 0 0 X.Y.Z' m6
1 1 1 0 X.Y.Z m7

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The first canonical form is developed from the output 1's in the truth
table. As can be seen, F is only 1 for the 1st and 4th rows of the truth
table. Therefore the minterm (AND function) expressions for these two
rows are formed and OR-ed together to give the minterm form for the
circuit as

F = X'.Y'.Z'+ X.Y'. Z'

F= m0 + m3 = Σ ( 0,3 )

The corresponding circuit would be implemented with AND-OR logic i.e.

with the outputs from one or more AND gates being OR-ed together to
give the final output.
Sum-of-minterms standard form expresses the Boolean or switching
expression in the form of a sum of products using minterms.
• For instance, the following Boolean expression using minterms

Example: The Maxterm Form

Consider the truth table below for the output Y from a combinatorial
logic circuit comprising three inputs, A, B and C

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 X Y Z F Maxterm Designation
0 0 0 0 X+Y+Z Mo
0 0 1 1 X+Y+Z' M1
0 1 0 1 X+Y'+Z M2
0 1 1 0 X+Y'+Z' M3
1 0 0 1 X'+Y+Z M4
1 0 1 1 X'+Y+Z' M5
1 1 0 1 X'+Y'+Z M6
1 1 1 1 X'+Y'+Z' M7
The second canonical form is developed from the output 0's in the
truth table. As can be seen, F is only 0 for the 1st and 4th rows of the
truth table. Developing the maxterm expression here is slightly more
complicated and there are two approaches.
In the first approach we first develop the minterm expression for
the output 0's (not 1's) in the truth table. For the truth table above this will
be given by
F' = (X.Y.Z) +(X.Y'.Z')
Then it is necessary to apply the rules of Boolean algebra for converting
minterm expressions to maxterm expressions as is described in the
Boolean Algebra. This leads to the final maxterm form for this truth table
of
F =( X+Y+Z) . (X+Y'+Z')
F= M1 .M4 = π ( 0,3 )
The second approach allows the maxterm form to be derived directly
from the output 0's in the truth table using the following rules.
 Take each line in the truth table where the output is 0 and
 Invert the variables (e.g. if X is 1 then write X' etc.)
 OR these variables together to form the maxterm
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  build the second canonical form from the AND of these maxterms
In the case of the truth table above it is possible to go directly to the final
maxterm form using this approach.
Summary to minters and maxterms
 Use the ones of the function to determine minters and zeros of the
function to determine maxterms form.
Minters and maxterms
X Y F(X,Y)
0 0 0
0 1 1
1 0 1
1 1 0
SOP
F(X,Y) = X'.Y'+ X.Y'
= Σ m (1,2).
POS
(i) F'(X,Y) = X'.Y' + X.Y
(ii) F(X,Y) = (X'.Y' + X.Y)'
= (X+Y) . (X'+Y')
= π M (0,3 ) = M0 +M3
= π ( 0,3 )
Problem
Convert the following to the other canonical form:
(a) F (x, y , z) = ∑ (1,3,7)
(b) F(A,B,C,D)= ∏ (0,1,2,3,4,6,12)
Solution:
(a) F (x, y, z) = ∑ (1,3,7) = ∏ (0,2,4,5,6)
F (x, y, z) =

37
 ( x  y  z)  ( x  y  z)  ( x  y  z)  ( x  y  z)  ( x  y  z)

(b) F (A,B,C,D) = ∏ (0,1,2,3,4,6,12)

= ∑ (5,7,8,9,10,11,13,14,15)
F(A,B,C,D)=
( ABCD)  ( ABCD)  ( ABC D)  ( ABCD)  ( ABC D)
 ( ABCD )  ( ABCD)  ( ABC D)  ( ABCD)

The "don't care" condition

It can easily be seen that for a logic gate with n inputs then the
corresponding truth table requires 2n rows or entries. For devices with 4
or more inputs, representing each input state in this way can be a lengthy
procedure. To simplify this representation of a logic function the concept
of the "dont care" condition is introduced.
Consider, for example the truth table for a three-input OR gate, it looks
like

+ +

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 1

38
This table can be simplified by writing

+ +

0 0 0 0

1 x x 1

x 1 x 1

x x 1 1

where x can equal 0 or 1.

Karnaugh Maps
Karnaugh maps provide a systematic method to obtain simplified
sum-of-products (SOPs) Boolean expressions. This is a compact way of
representing a truth table and is a technique that is used to simplify logic
expressions. It is ideally suited for four or less variables, becoming
cumbersome for five or more variables. Each square represents either a
minterm or maxterm. A K-map of n variables will have 2 squares. For a
Boolean expression, product terms are denoted by 1's, while sum terms
are denoted by 0's - but 0's are often left blank.
A K-map consists of a grid of squares, each square representing
one canonical minterm combination of the variables or their inverse. The
map is arranged so that squares representing minterms which differ by
only one variable are adjacent both vertically and horizontally. Therefore

39
 XY'Z' would be adjacent to X'Y'Z' and would also adjacent to XY'Z and
XYZ'.

Karnaugh Map Simplification Rules-

To minimize the given boolean function,

 We draw a K Map according to the number of variables it contains.
 We fill the K Map with 0‟s and 1‟s according to its function.
 Then, we minimize the function in accordance with the following
rules.

Rule-1:

 We can either group 0‟s with 0‟s or 1‟s with 1‟s but we can not
group 0‟s and 1‟s together.
 X representing don‟t care can be grouped with 0‟s as well as 1‟s

Rule-2:

 Groups may overlap each other.

Rule-3:

 We can only create a group whose number of cells can be

represented in the power of 2.
 In other words, a group can only contain 2n i.e. 1, 2, 4, 8, 16 and so
on number of cells.

41
 Example-

Rule-4:

 Groups can be only either horizontal or vertical.

 We can not create groups of diagonal or any other shape.

Rule-5:

 Each group should be as large as possible.

40
 Example-

Rule-6:

 Opposite grouping and corner grouping are allowed.

 The example of opposite grouping is shown illustrated in Rule-05.
 The example of corner grouping is shown below.

Example-

Rule-7:

 There should be as few groups as possible.

42
Minimization Technique
 Based on the Unifying Theorem: X + X' = 1
 The expression to be minimized should generally be in sum-of-
product form (If necessary, the conversion process is applied to
create the sum-of-product form).
 The function is mapped onto the K-map by marking a 1 in those
squares corresponding to the terms in the expression to be
simplified (The other squares may be filled with 0's).
 Pairs of 1's on the map which are adjacent are combined using the
theorem Y(X+X') = Y where Y is any Boolean expression (If two
pairs are also adjacent, then these can also be combined using the
same theorem).
 The minimization procedure consists of recognizing those pairs
and multiple pairs.
 ->These are circled indicating reduced terms.
o Groups which can be circled are those which have two (2 1)
1's, four (22) 1's, eight (23) 1's, and so on.
 ->Note that because squares on one edge of the map are considered
adjacent to those on the opposite edge, group can be formed with
these squares.
 ->Groups are allowed to overlap.
 The objective is to cover all the 1's on the map in the fewest
number of groups and to create the largest groups to do this.
 Once all possible groups have been formed, the corresponding
terms are identified.
 ->A group of two 1's eliminates one variable from the original
minterm.
 ->A group of four 1's eliminates two variables from the original
minterm.
43
  ->A group of eight 1's eliminates three variables from the original
minterm, and so on.
 The variables eliminated are those which are different in the
original minterms of the group.

2-Variable K-Map
In any K-Map, each square represents a minterm. Adjacent squares
always differ by just one literal (So that the unifying theorem may apply:
X + X' = 1). For the 2-variable case (e.g.: variables X, Y), the map can be
drawn as below. Two variable map is the one which has got only two
variables as input.

Equivalent labeling
K-map needs not follow the ordering as shown in the figure above. What
this means is that we can change the position of m0, m1, m2, m3 of the
above figure as shown in the two figures below.
Position assignment is the same as the default k-maps positions.
This is the one which we will be using throughout this tutorial.

44
This figure is with changed position of m0, m1, m2, m3.

The K-map for a function is specified by putting a '1' in the square

corresponding to a minterm, a '0' otherwise.

Example of two – variable

45
Example- Carry and Sum of a half adder
In this example we have the truth table as input, and we have two output
functions. Generally we may have n output functions for m input
variables. Since we have two output functions, we need to draw two k-
maps (i.e. one for each function). Truth table of 1 bit adder is shown
below. Draw the k-map for Carry and Sum as shown below.

x y Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Grouping/Circling K-maps
The power of K-maps is in minimizing the terms, K-maps can be
minimized with the help of grouping the terms to form single terms.
When forming groups of squares, observe/consider the following:
 Every square containing 1 must be considered at least once.

46
 A square containing 1 can be included in as many groups as
desired.
 A group must be as large as possible.
 If a square containing 1 cannot be placed in a group, then leave it
out to include in final expression.
 The number of squares in a group must be equal to 2, , i.e. 2,4,8,.
 The map is considered to be folded or spherical, therefore squares
at the end of a row or column are treated as adjacent squares.
 The simplified logic expression obtained from a K-map is not
always unique. Groupings can be made in different ways.
 Before drawing a K-map the logic expression must be in canonical
form.

47
 In the next few pages we will see some examples on grouping.
Example of invalid groups

Example - X'Y+XY
In this example we have the equation as input, and we have one output
function. Draw the k-map for function F with marking 1 for X'Y and
XY position. Now combine two 1's as shown in figure to form the
single term. As you can see X and X' get canceled and only Y
remains.
F=Y

Example - X'Y+XY+XY'
In this example we have the equation as input, and we have one output
function. Draw the k-map for function F with marking 1 for X'Y, XY
and XY position. Now combine two 1's as shown in figure to form the
two single terms.
F=X+Y

48
3-Variable K-Map
There are 8 minterms for 3 variables (X, Y, Z). Therefore, there are 8
cells in a 3-variable K-map. One important thing to note is that K-
maps follow the gray code sequence, not the binary one.

Using gray code arrangement ensures that minterms of adjacent cells

differ by only ONE literal. (Other arrangements which satisfy this
criterion may also be used.). Each cell in a 3-variable K-map has 3
adjacent neighbours. In general, each cell in an n-variable K-map has
n adjacent neighbours.

49
There is wrap-around in the K-map
 X'Y'Z' (m0) is adjacent to X'YZ' (m2)
 XY'Z' (m4) is adjacent to XYZ' (m6)

51
Examples of three–variable

50
Example
F = XYZ'+XYZ+X'YZ

F = XY + YZ
Example
F(X,Y,Z) = (1,3,4,5,6,7)

52
 F=X+Z
4-Variable K-Map
There are 16 cells in a 4-variable (W, X, Y, Z); K-map as shown in the
figure below.

There are 2 wrap-around: horizontal and vertical. Every cell thus has 4
neighbours. For example, the cell corresponding to minterm m0 has
neighbors m1, m2, m4 and m8.

53
Example
F(W,X,Y,Z) = (1,5,12,13)

F = WY'Z + W'Y'Z
Example
F(W,X,Y,Z) = (4, 5, 10, 11, 14, 15)

54
 F = W'XY' + WY

Examples of four–variable
1-Minimize the following boolean function-
F(A, B, C, D) = Σm(0, 1, 2, 5, 7, 8, 9, 10, 13, 15)
Solution-

 Since the given boolean expression has 4 variables, so we draw a 4

x 4 K Map.
 We fill the cells of K Map in accordance with the given boolean
function.
 Then, we form the groups in accordance with the above rules.

Then, we have-

55
 F(A, B, C, D) =BD + C‟D + B‟D‟
2-Minimize the following boolean function-

F(A, B, C, D) = Σm(0, 1, 3, 5, 7, 8, 9, 11, 13, 15)

Solution-

Since the given boolean expression has 4 variables, so we draw a 4

 x 4 K Map.
 We fill the cells of K Map in accordance with the given boolean
 function.
 Then, we form the groups in accordance with the above rules.

56
F(A, B, C, D) = D + B‟C‟
3-

57
4-Simplify the following Boolean Functions, using three variable maps:
(a) F(x,y,z)=Σ(0,2,6,7)

F= XY + X‟Z‟

(b) F(A,B,C)=Σ(0,2,3,4,6)

F= A‟B + C‟

(c) F(a,b,c)=Σ(0,1,2,3,7)

58
 F=A‟+BC

(d) F(x,y,z)= Σ(3,5,6,7)

F= XY + XZ+ YZ
Problems:
Simplify the following Boolean Functions.

(a) F(X,Y,Z)= Σ(2,3,6,7)

F=Y

(b) F(A,B,C,D)= Σ(4,6,7,15)

59
 F=BCD+A‟BD‟

(c) F(A,B,C,D)= Σ(3,7,11,13,14,15)

F=CD+ABD+ABC

(d) F(W,X,Y,Z)= Σ(2,3,12,13,14,15).

F= WX + W‟X‟Y

61
Problems:

Simplify the following expressions in (1) sum of products and (2)

products of sums:
a) AC  BD  ACD  ABCD
b)  A  B  D A  B  C A  B  DB  C  D

Solution:
a) AC  BD  ACD  ABCD

C C

0 1 1 0 0 1 1 0
0 0 1 0 0 0 1 0
B B

1 1 1 0 1 1 1 0
A A

1 1 1 0 1 1 1 0
D D

F‟=CD‟+A‟D‟+A‟BC‟
SOP= AC   CD  BD POS= C   D A  D A  B'C 

b) F=  A  B  D A  B  C A  B  DB  C  D

F‟=ABD+A‟BC+AB‟D+B‟CD

C
C

1 1 0 1
1 1 0 1
1 1 0 0
B 1 1 0 0
1 0 0 1 B
A 1 0 0 1
1 0 0 1 A
1 0 0 1
D
D

60
 F‟= AD+ CD + A‟BC
SOP= A' C' B' D  AD' POS=  A  DC   D A  B  C 

Problems:
1. Simplify the following Boolean functions to a minimum number of
literals:
(1) A +AB
(2) AB+AB'
(3) A'BC + AC
(4) A'B+ ABC' +ABC
(5) AB + A(CD + CD')
(6) (BC'+A'D).(AB'+CD')
(7) (X+Y)(X+Y')
(8) X+X'Y
(9) XY+ X'Z + YZ
(10) A'C' + AC'+ ABC
(11) AC + A'BC
(12) X(X'+Y)
(13) XY+XY'
(14) XYZ+X'Y+XYZ'
(15) ABC+A'B+ABC'
(16) XZ + X'YZ
(17) A+A'B+ A'B'
2. Simplify the following expression using Boolean algebra
F= XY'Z + X'Y'Z + XYZ
List the truth table and draw the logic diagram of the simple expression.

3. Using DeMorgan's theorem, show that:

(A+B)' . (A'+B')'=0
62
 Chapter (3)
Combinatorial Circuits

Logic circuits for digital system may be combinatorial or

sequential. Combinatorial circuits are those in which the output state
depends only on the present inputs. Combinatorial circuit consists of
logic gates whose outputs at any time are determined from the present
combination of inputs. Sequential circuits are those in which the output
state depends on the input states and on the previous states. Sequential
circuits employ storage elements in addition to logic gates. In other
words, Combinatorial circuits are memory less circuits while Sequential
circuits are memory circuits. A block diagram of a combinatorial circuit
is shown in figure

where n is input binary variables and m is output variables.

Programmable Logic Devices

Programmable Logic Devices PLDs are the integrated circuits. They
contain an array of AND gates & another array of OR gates. There are
three kinds of PLDs based on the type of arrayss, which has
programmable feature.

63
  Programmable Read Only Memory
 Programmable Array Logic
 Programmable Logic Array

The process of entering the information into these devices is known

as programming. Basically, users can program these devices or ICs
electrically in order to implement the Boolean functions based on the
requirement. Here, the term programming refers to hardware
programming but not software programming.

Programmable Read Only Memory PROM:

Read Only Memory ROMROM is a memory device, which stores the
binary information permanently. That means, we can‟t change that
stored information by any means later. If the ROM has programmable
feature, then it is called as Programmable ROM PROMPROM. The
user has the flexibility to program the binary information electrically
once by using PROM programmer.

PROM is a programmable logic device that has fixed AND array &
Programmable OR array. The block diagram of PROM is shown in the
following figure.

Here, the inputs of AND gates are not of programmable type. So, we
have to generate 2n product terms by using 2n AND gates having n inputs
each. We can implement these product terms by using nx2 n decoder. So,
this decoder generates „n‟ min terms.

64
Here, the inputs of OR gates are programmable. That means, we can
program any number of required product terms, since all the outputs of
AND gates are applied as inputs to each OR gate. Therefore, the outputs
of PROM will be in the form of sum of min terms.

Example

Let us implement the following Boolean functions using PROM.

A(X,Y,Z)=∑m(5,6,7)A(X,Y,Z)=∑m(5,6,7)
B(X,Y,Z)=∑m(3,5,6,7)
The given two functions are in sum of min terms form and each function
is having three variables X, Y & Z. So, we require a 3 to 8 decoder and
two programmable OR gates for producing these two functions. The
corresponding PROM is shown in the following figure.

Here, 3 to 8 decoder generates eight min terms. The two programmable

OR gates have the access of all these min terms. But, only the required
min terms are programmed in order to produce the respective Boolean
functions by each OR gate. The symbol „X‟ is used for programmable
connections.

65
Programmable Array Logic PAL

PAL is a programmable logic device that has Programmable AND array

& fixed OR array. The advantage of PAL is that we can generate only
the required product terms of Boolean function instead of generating all
the min terms by using programmable AND gates. The block
diagram of PAL is shown in the following figure.

Here, the inputs of AND gates are programmable. That means each
AND gate has both normal and complemented inputs of variables. So,
based on the requirement, we can program any of those inputs. So, we
can generate only the required product terms by using these AND
gates.

Here, the inputs of OR gates are not of programmable type. So, the
number of inputs to each OR gate will be of fixed type. Hence, apply
those required product terms to each OR gate as inputs. Therefore, the
outputs of PAL will be in the form of sum of products form.

Example

Let us implement the following Boolean functions using PAL.

A=XY+XZ′A=XY+XZ′
A=XY′+YZ′
The given two functions are in sum of products form. There are two
product terms present in each Boolean function. So, we require four
66
programmable AND gates & two fixed OR gates for producing those two
functions. The corresponding PAL is shown in the following figure.

The programmable AND gates have the access of both normal and
complemented inputs of variables. In the above figure, the inputs
X, X′X′, Y, Y′Y′, Z & Z′Z′, are available at the inputs of each AND gate.
So, program only the required literals in order to generate one product
term by each AND gate. The symbol „X‟ is used for programmable
connections.

Here, the inputs of OR gates are of fixed type. So, the necessary product
terms are connected to inputs of each OR gate. So that the OR gates
produce the respective Boolean functions. The symbol „.‟ is used for
fixed connections.

Programmable Logic Array PLA

PLA is a programmable logic device that has both Programmable AND

array & Programmable OR array. Hence, it is the most flexible PLD.
The block diagram of PLA is shown in the following figure.

67
Here, the inputs of AND gates are programmable. That means each
AND gate has both normal and complemented inputs of variables. So,
based on the requirement, we can program any of those inputs. So, we
can generate only the required product terms by using these AND
gates.

Here, the inputs of OR gates are also programmable. So, we can program
any number of required product terms, since all the outputs of AND
gates are applied as inputs to each OR gate. Therefore, the outputs of
PAL will be in the form of sum of products form.

Example

Let us implement the following Boolean functions using PLA.

A=XY+XZ′A=XY+XZ′
B=XY′+YZ+XZ′B=XY′+YZ+XZ′
The given two functions are in sum of products form. The number of
product terms present in the given Boolean functions A & B are two and
three respectively. One product term, Z′XZ′X is common in each
function.

So, we require four programmable AND gates & two programmable OR

gates for producing those two functions. The corresponding PLA is
shown in the following figure.

68
The programmable AND gates have the access of both normal and
complemented inputs of variables. In the above figure, the inputs
X, X′X′, Y, Y′Y′, Z & Z′Z′, are available at the inputs of each AND gate.
So, program only the required literals in order to generate one product
term by each AND gate.

All these product terms are available at the inputs of

each programmable OR gate. But, only program the required product
terms in order to produce the respective Boolean functions by each OR
gate. The symbol „X‟ is used for programmable connections

Addition and Subtraction using Logic Gates

Arithmetic circuits are the ones which perform arithmetic operations like
addition, subtraction, multiplication, division.
Half Adder (A.H)
The simple addition consists of four possible operations namely,
0+0=0, 0+1 =1, 1+0= 1, and 1 + 1 = 1 0
Adding two single-bit binary values X, Y produces a sum S bit and a
carry out C-out bit. This operation is called half addition and the circuit to
realize it is called a half adder.

69
Symbol

Truth Table
X Y SUM (S) CARRY ( C )
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
S (X,Y) = (1,2), C= (1,2) = XY
S = X'Y + XY' , C=XY (1)
S = X Y, C=XY (2)

Full Adder (F.H)

Full Adder is a combinational circuit that performs the addition of
three bits (two significant bits and previous carry).

71
 bits to be added, the third input represents the carry form the
previous position.

1 or when all three inputs are equal to 1.

output has a carry 1 if two or three inputs are equal to 1.

Truth Table
X Y CIN SUM (S) CARRY (Cout)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
SUM (X,Y,Z) = S = (1,2,4,7)
CARRY (X,Y,Z) = Cout = (3,5,6,7)

70
Subtractors
The subtraction of two binary numbers can be accomplished by taking the
complement of the subrahend and adding to the minuend.
That is, X – Y = X + 2's Complement of Y.
By this method, the subtraction operation becomes an addition operation.

72
Half Subtractor
The half-subtractor is a combinational circuit which is used to perform
subtraction of two bits. Cleary this circuit is performing binary
subtraction of Y from X (X-Y, recalling that in binary 0-1 = 1 borrow 1).
It has two inputs, X (minuend) and Y (subtrahend) and two outputs D
(difference) and B (borrow). Consider the circuit below:

A truth table for the circuit looks like:

X Y D (DIFF) B (BORROW)

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

D= (1,2,) = m1 + m2 = X'Y + XY' = X Y

B = m1 = X'Y
Full Subtractor
A full subtractor is a combinational circuit that performs subtraction of
two bits, one is minuend and other is subtrahend, taking into account
borrow of the previous adjacent lower minuend bit. This circuit has

73
three inputs and two outputs. The three inputs A, B and Bin,
denote the minuend, subtrahend, and previous borrow, respectively. The
two outputs, D and Bout represent the difference and output borrows,
respectively. Generally, the full subtractor is one of the most used and
essential combinational logic circuits. It is a basic electronic device,
used to perform subtraction of two binary numbers. Likewise, the full-
subtractor uses binary digits like 0, 1 for the subtraction

74
Binary addition

4 Bit Parallel Adder

In the block diagram, A0 and B0 represent the LSB of the four bit words
A and B. Hence Full Adder-0 is the lowest stage. Hence its Cin has been
permanently made 0. The rest of the connections are exactly same as
those of n-bit parallel adder is shown in fig. The four bit parallel adder is
a very common logic circuit.
The input carry to the adder is c0 and it ripples through the full adders to
the output carry c4. n -bit binary adder requires n full adders.

75
Block diagram

Binary Subtractor
To perform the subtraction, we can use the 2's complements, so the
subtraction can be converted to addition. 2's complement can be obtained
by talking the 1‟s complement and adding 1 to the LSD bit.
1) 1‟s complement can be implemented with inverters.
2) 1 can be added to the sum through the input carry.
The circuit for subtracting A-B consists of an adder with inverters
placed between each data input B and the corresponding input of
the full adder. The input carry C0 must be equal to 1
4 Bit Subtractor circuit

4 Bit Adder/subtractor circuit

The circuit for subtracting A - B consists of an adder with inverters
placed between each data input B and the corresponding input of the full
adder. The input carry C0 must be equal to 1 when subtraction is

76
performed. The operation thus performed becomes A, plus the 1‟s
complement of B, plus 1. This is equal to A plus the 2‟s complement of B

Decoders
A decoder is a device which does the reverse of an encoder. A decoder is
a multiple-input, multiple-output logic circuit that converts coded inputs
into coded outputs, where the input and output codes are different; e.g. n-
to-2n, BCD decoders. Enable inputs (E) must be on for the decoder to
function i.e. E=1 the decoder is on, E=0 the decoder is off. Decoding is
necessary in applications such as data multiplexing, 7 segment display
and memory address decoding.

Binary n-to-2n Decoders

A binary decoder has n inputs and 2n outputs. Only one output is active at
any one time, corresponding to the input value. Figure below shows a
representation of Binary n-to-2n decoder

77
Example : 2-to-4 Binary Decoder
A 2 to 4 decoder consists of two inputs and four outputs, truth table and
symbols of which is shown below.

Truth Table
X Y F0 F1 F2 F3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

It is clear that:
F0 = X' Y'
F1 = X' Y
F2 = X Y'
F3= X Y
Symbol

78
Example : 3-to-8 Binary Decoder
A 3 to 8 decoder consists of three inputs and eight outputs, truth table and
symbols of which is shown below.

Truth Table
X Y Z F0 F1 F2 F3 F4 F5 F6 F7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

Symbol

F0 = X' Y' Z', ………..

Exercises:
(a) Construct 3x8 decoder by using 2x4 decoders.
(b) Construct 4x16 decoder by using 3x8 decoders.

79
 (c) Construct 4x16 decoder by using 2x4 decoders.
(d) Construct 5x32 decoder by using 3x8 and 2x4 decoders.

Seven-Segment Decoder

A seven-segment decoder is indicator for representing decimal numbers.

Seven-segment decoder converting the Binary-coded-decimal (BCD).
Each segment of a seven-segment display is a small light-emitting diode
(LED) or liquid-crystal display (LCD), and - as is shown below - a
decimal number is indicated by lighting a particular combination of the
LED's or LCD's elements i.e. the decimal digits are displayed on the 7-
segment display as follows:

For example to display 1 , the segments b and c are to be on while other

segment are off. Truth Table to Decode Binary into 7-Segment

81
Decimal
Inputs Outputs
Number
DCBA a b c d e f g
0 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
2 0 0 1 0 1 1 0 1 1 0 1
3 0 0 1 1 1 1 1 1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1
5 0 1 0 1 1 0 1 1 0 1 1
6 0 1 1 0 1 0 1 1 1 1 1
7 0 1 1 1 1 1 1 0 0 0 0
8 1 0 0 0 1 1 1 1 1 1 1
9 1 0 0 1 1 1 1 1 0 1 1

The decoder output can be obtained as Boolean function of the inputs (A,
B, C and D).

For example, the K- map for the " a " output is shown.

a = A + C + BD + B'D'

80
For example prove:
g = A + B.C + C.D' + B'.C

Encoders
An encoder is a combinational circuit that performs the inverse operation
of a decoder. If a device output code has fewer bits than the input code
has, the device is usually called an encoder. e.g. 2n-to-n, priority
encoders.
The simplest encoder is a 2n-to-n binary encoder, where it has only
one of 2n inputs = 1 and the output is the n-bit binary number
corresponding to the active input.

The block diagram and truth table of a 4: 2encoder is as follows:

D0 D1 D2 D3 X Y
1 0 0 0 0 0
0 1 0 0 0 1

82
 0 0 1 0 1 0
0 0 0 1 1 1

X= D2 + D3 Y = D1 + D3

Multiplexer and Demultiplexer

A multiplexer is a circuit that accept many input but give only one

output. A demultiplexer function exactly in the reverse of a

multiplexer, that is a demultiplexer accepts only one input and

gives many outputs. Generally multiplexer and demultiplexer are

used together, because of the communication systems are bi

directional.

Mutliplexer:
Multiplexer means many into one. A multiplexer is a circuit used

to select and route any one of the several input signals to a signal

output. An simple example of an non electronic circuit of a

multiplexer is a single pole multiposition switch.

Multiposition switches are widely used in many electronics

circuits. However circuits that operate at high speed require the

multiplexer to be automatically selected. A mechanical

switchcannot perform this task satisfactorily. Therefore,

multiplexer used to perform high speed switching are constructed

of electronic components.

83
Multiplexer handle two type of data that is analog and

digital. For analog application, multiplexer are built of relays

and transistor switches. For digital application, they are built from

standard logic gates.

The multiplexer used for digital applications, also called digital

multiplexer, is a circuit with many input but only one output.

By applying control signals, we can steer any input to the output.

Few types of multiplexer are 2-to-1, 4-to-1, 8-to-1, 16-to-1

multiplexer.

Following figure shows the general idea of a multiplexer with n

input signal, m control signals and one output signal.

Understanding 4-to-1 Multiplexer:

The 4-to-1 multiplexer has 4 input bit, 2 control bits, and 1 output

bit. The four input bits are D0,D1,D2 and D3. only one of

84
this is transmitted to the output y. The output depends on

the value of AB which is the control input. The control input

determines which of the input data bit is transmitted to the output.

For instance, as shown in fig. when AB = 00, the upper

AND gate is enabled while all other AND gates are disabled.

Therefore, data bit D0 is transmitted to the output, giving Y = Do.

4 to 1 Multiplexer Circuit Diagram

If the control input is changed to AB =11, all gates are disabled

except the bottom AND gate. In this case, D3 is transmitted

to the output and Y = D3.

A multiplexer (MUX) is a combinational circuit that receives binary

information from one of 2n input data lines and directs it to a single
output line. The selection of a particular input data line for the output is
determined by n of selection inputs. A multiplexer of 2 n inputs has n
selection lines, which are used to select which input line to send to the
output.

85
Example : 2x1 MUX
A 2 to 1 line multiplexer is shown in figure, each 2 input lines I 0 to I1 is
applied to one input. The truth table for the 2:1 mux is given in the table
below.

Truth Table
S Y
0 I0
1 I1

Example : 4:1 MUX

A 4 to 1 line multiplexer is shown in figure below, each of 4 input lines
I0 to I3 is applied to one input of an AND gate. Selection lines S0 and S1
are decoded to select a particular AND gate. The truth table for the 4:1
mux is given in the table below.

86
Truth Table
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
Circuit

Larger Multiplexers
Larger multiplexers can be constructed from smaller ones. An 8-to-1
multiplexer can be constructed from smaller multiplexers as shown
below.

87
Example - 8-to-1 multiplexer from Smaller MUX
Truth Table
S2 S1 S0 F
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7

Circuit

Example - 16-to-1 multiplexer from 4:1 mux

88
 An example of 4-to-1 multiplexer is IC 74153 in which the
output is same as the input.
 Another example of 4-to-1 multiplexer is 45352 in which the
output is the compliment of the input.
 Example of 16-to-1 line multiplexer is IC74150.

Applications of Multiplexer:

Multiplexer are used in various fields where multiple data need to

be transmitted using a single line. Following are some of the

applications of multiplexers -

1. Communication system – Communication system is a set of

system that enable communication like transmission system,

relay and tributary station, and communication network. The

efficiency of communication system can be increased

considerably using multiplexer. Multiplexer allow the process of

89
transmitting different type of data such as audio, video at the

same time using a single transmission line.

Demultiplexer:

Demultiplexer means one to many. A demultiplexer is a circuit

with one input and many output. By applying control signal, we

can steer any input to the output. Few types of demultiplexer are

1-to 2, 1-to-4, 1-to-8 and 1-to 16 demultiplexer.

Following figure illustrate the general idea of a demultiplexer with

1 input signal, m control signals, and n output signals.

Understanding 1- to-4 Demultiplexer:

The 1-to-4 demultiplexer has 1 input bit, 2 control bit, and 4

output bits. An example of 1-to-4 demultiplexer is IC 74155. The

1-to-4 demultiplexer is shown in figure below-

91
1 to 4 Dempultiplexer Circuit Diagram
The input bit is labeled as Data D. This data bit is transmitted to

the data bit of the output lines. This depends on the value of AB,

the control input.

When AB = 01, the upper second AND gate is enabled while

other AND gates are disabled. Therefore, only data bit D is

transmitted to the output, giving Y1 = Data.

If D is low, Y1 is low. IF D is high,Y1 is high. The value of Y1

depends upon the value of D. All other outputs are in low state.

If the control input is changed to AB = 10, all the gates are

disabled except the third AND gate from the top. Then, D is

transmitted only to the Y2 output, and Y2 = Data.

Example of 1-to-16 demultiplexer is IC 74154 it has 1 input bit, 4

control bits and 16 output bit. Applications of Demultiplexer:

90
1. Demultiplexer is used to connect a single source to multiple

destinations. The main application area of demultiplexer is

communication system where multiplexer are used. Most of the

communication system are bidirectional i.e. they function in

both ways (transmitting and receiving signals). Hence, for most

of the applications, the multiplexer and demultiplexer work in

sync. Demultiplexer are also used for reconstruction of parallel

data and ALU circuits.

2.Communication System-Communication system use multiplexer

to carry multiple data like audio, video and other form of data

using a single line for transmission. This process make the

transmission easier. The demultiplexer receive the output

signals of the multiplexer and converts them back to the

original form of the data at the receiving end. The multiplexer

and demultiplexer work together to carry out the process of

transmission and reception of data in communication system.

3. ALU (Arithmetic Logic Unit) – In an ALU circuit, the output

of ALU can be stored in multiple registers or storage units

with the help of demultiplexer. The output of ALU is fed as

the data input to the demultiplexer. Each output of

demultiplexer is connected to multiple register which can be

stored in the registers.

92
4. Serial to parallel converter - A serial to parallel converter is

used for reconstructing parallel data from incoming serial data

stream. In this technique, serial data from the incoming

serial data stream is given as data input to the demultiplexer

at the regular intervals. A counter is attach to the control input of

the demultiplexer. This counter directs the data signal to the

output of the demultiplexer where these data signals are stored.

When all data signals have been stored, the output of the

demultiplexer can be retrieved and read out in parallel.

93
 Chapter 4
Synchronous sequential logic

Digital electronics is classified into combinational logic and sequential

logic. The main characteristic of combinational circuits is that the outputs
at a particular time t are determined by the inputs at the same time t. This
means that combinational circuits require no memory. However, in
practice, most digital systems contain combinational circuits along with
memory. These circuits are called “sequential.”
In sequential circuits, the present outputs depend on the present inputs
and the previous states stored in the memory elements. These states must
be fed back to the inputs in order to generate the present outputs. Thus, a
sequential circuit is specified by a time sequence of inputs, outputs and
internal states. A block diagram of sequential circuits is shown in figure.
It consists of combinational circuit to which memory elements are
connected to form a feedback path.

There are two types of sequential circuits. Their classification depends on

the timing of their signals:
 Synchronous sequential circuits

94
  Asynchronous sequential circuits

Asynchronous sequential circuit

This is a system whose outputs depend upon the order in which its input
variables change and can be affected at any instant of time. Because of
the feedback among logic gates, the system may, at times, become
unstable. Consequently they are not often used.

Synchronous sequential circuits

This type of system uses storage elements called flip-flops that are
employed to change their binary value only at discrete instants of time.
Synchronous sequential circuits use logic gates and flip-flop storage
devices. Sequential circuits have a clock signal as one of their inputs. All
state transitions in such circuits occur only when the clock value is either
0 or 1 or happen at the rising or falling edges of the clock depending on
the type of memory elements used in the circuit. Synchronization is
achieved by a timing device called a clock pulse generator. Clock pulses
are distributed throughout the system in such a way that the flip-flops are
affected only with the arrival of the synchronization pulse. Synchronous
sequential circuits that use clock pulses in the inputs are called clocked-
sequential circuits. They are stable and their timing can easily be broken
down into independent discrete steps, each of which is considered
separately.

95
A clock signal is a periodic square wave that indefinitely switches from 0
to 1 and from 1 to 0 at fixed intervals. Clock cycle time or clock period:
the time interval between two consecutive rising or falling edges of the
clock.
Clock Frequency = 1 / clock cycle time (measured in cycles per second
or Hz)

Example: Clock cycle time = 10ns clock frequency = 108 Hz

Flip-Flops
The memory elements in a sequential circuit are called flip-flops. A
flip-flop circuit has two outputs, one for the normal value and one for the
complement value of the stored bit. Binary information can enter a flip-
flop in a variety of ways and gives rise to different types of flip-flops.
Flip-flops are synchronous bistable devices. The term synchronous means
the output changes state only when the clock input is triggered. That is,
changes in the output occur in synchronization with the clock.
Flip-flop is a kind of multivibrator. There are three types of
multivibrators:
1. Monostable multivibrator (also called one-shot) has only one
stable state. It produces a single pulse in response to a
triggering input.
2. Bistable multivibrator exhibits two stable states. It is able to
retain the two SET and RESET states indefinitely. It is
commonly used as a basic building block for counters,
registers and memories.

96
 3. Astable multivibrator has no stable state at all. It is used
primarily as an oscillator to generate periodic pulse
waveforms for timing purposes.

Basic Flip-Flop Circuit

A flip-flop circuit can be constructed from two NAND gates or two
NOR gates. These flip-flops are shown below. Each flip-flop has two
outputs, Q and Q', and two inputs, set and reset. This type of flip-flop is
referred to as an SR flip-flop or SR latch. The flip-flop has two useful
states. When Q=1 and Q'=0, it is in the set state (or 1-state). When Q=0
and Q'=1, it is in the clear (Reset) state (or 0-state). The outputs Q and Q'
are complements of each other and are referred to as the normal and
complement outputs, respectively. The binary state of the flip-flop is
taken to be the value of the normal output. To analyze the SR flip flop,
note that a NOR gate generates an output 1 when all inputs are 0; on the
other hand, the output of a NOR gate is 0 if any input is 1.
When a 1 is applied to both the set and reset inputs of the NOR
flip-flop, both Q and Q' outputs go to 0. This condition violates the fact
that both outputs are complements of each other. In normal operation this
condition must be avoided by making sure that 1's are not applied to both
inputs simultaneously. This undesirable situation is indicated by a invalid
(indeterminate) in the truth table.

97
 S R Q(t) Q' (t)
0 0 Q (no change) Q'
0 1 0 Reset state=Clear to 0 1
1 0 1 Set state 0

1 1 0 (invalid)= indeterminate 0 (invalid)

where Q(t) = present state.

The waveform below shows the operation of NOR gates based RS flip
flop.

It is possible to construct the RS flip flop using NAND gates. The only
difference is that NAND is NOR gate dual form . So in this case the R =
0 and S = 0, both outputs go to 1and the case becomes the invalid case.
This condition should be avoided in normal operation. The circuit and
Truth table of RS flip flop using NAND is shown below.

98
 S R Q(t) Q' (t)
0 0 1 1 (invalid)
0 1 1 0
1 0 0 1
1 1 Q Q' (no change)

Clocked SR Flip-Flop
The clocked SR flip-flop shown in shown blow consists of a basic NOR
flip-flop and two AND gates. The outputs of the two AND gates remain
at 0 as long as the clock pulse (or CP) is 0, regardless of the S and R input
values. When the clock pulse goes to 1, information from the S and R
inputs passes through to the basic flip-flop. With both S=1 and R=1, the
occurrence of a clock pulse causes both outputs to momentarily go to 0.
When the pulse is removed, the state of the flip-flop is indeterminate, ie.,
either state may result, depending on whether the set or reset input of the
flip-flop remains a 1 longer than the transition to 0 at the end of the pulse.

99
 S R Q(t) Q(t+1)
0 0 0 0
0 1 0 0
1 0 0 1
1 1 0 indeterminate
0 0 1 1
0 1 1 0
1 0 1 1
1 1 1 indeterminate
where Q(t) = present state, Q(t+1) = next state.

D Flip-Flop
The D flip-flop is a modification of the clocked SR flip-flop. The clocked
SR flip-flop seen earlier contains ambiguous state; to eliminate this
condition we can ensure that S and R are never equal. This is done by
connecting S and R together with an inverter. Thus we have D flip flop
with the only one input which called D or Data input. Delay flip-flop or
delay latch is another name used. The D input is sampled during the
occurrence of a clock pulse. If it is 1, the flip-flop is switched to the set
state (unless it was already set). If it is 0, the flip-flop switches to the
clear state. Below is the truth table and circuit of D latch.

symbol

011
 D Q(t) Q(t+1)
0 0 0
1 0 1
0 1 0
1 1 1

Truth table in simple form

D Q(t+1
0 0 Clear to 0 = Reset
1 1 Set to 1

JK Flip-Flop
A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate
state of the SR type is defined in the JK type. Inputs J and K behave like
inputs S and R to set and clear the flip-flop (note that in a JK flip-flop, the
letter J is for set and the letter K is for clear). When logic 1 inputs are
applied to both J and K simultaneously, the flip-flop switches to its
complement state, ie., if Q=1, it switches to Q=0 and vice versa. Instead
of the indeterminate condition, the JK flip flop has a complement
condition Q(t+1) = Q'(t).
A clocked JK flip-flop is shown blow. Output Q is ANDed with K
and CP inputs so that the flip-flop is cleared during a clock pulse only if

010
Q was previously 1. Similarly, ouput Q' is ANDed with J and CP inputs
so that the flip-flop is set with a clock pulse only if Q' was previously 1.
Note that because of the feedback connection in the JK flip-flop, a
CP signal which remains a 1 (while J=K=1) after the outputs have been
complemented once will cause repeated and continuous transitions of the
outputs. To avoid this, the clock pulses must have a time duration less
than the propagation delay through the flip-flop. The restriction on the
pulse width can be eliminated with a master-slave or edge-triggered
construction. The same reasoning also applies to the T flip-flop presented
next.

symbol

J K Q(t) Q(t+1)
0 0 0 0
0 1 0 0
1 0 0 1
1 1 0 1
0 0 1 1
0 1 1 0
1 0 1 1
1 1 1 0

012
Truth table in simple form
J K Q(t+1)
0 0 Q(t) no change
0 1 0 Clear to 0=Reset state
1 0 1 Set to 1
1 1 Q'(t) complement
Note: Complement= toggle= invert the previous output= change output to
complement state.

T Flip-Flop
The T flip-flop is a single input version of the JK flip-flop. As shown in
figurer, the T flip-flop is obtained from the JK type if both inputs are tied
together. The output of the T flip-flop "toggles" with each clock pulse i.e.
when input is held HIGH, output toggles .

T Q(t) Q(t+1)
0 0 0
1 0 1
0 1 1
1 1 0

013
Truth table in simple form
T Q(t+1)
0 Q(t) no change
1 Q'(t) complement

Triggering of Flip-flops
The state of a flip-flop is changed by a momentary change in the input
signal. This change is called a trigger and the transition it causes is said to
trigger the flip-flop. Clocked flip-flops are triggered by pulses.
The feedback path between the combinational circuit and memory
elements in sequential circuits can produce instability if the outputs of the
memory elements (flip-flops) are changing while the outputs of the
combinational circuit that go to the flip-flop inputs are being sampled by
the clock pulse. A way to solve the feedback timing problem is to make
the flip-flop sensitive to the pulse transition rather than the pulse duration.
The clock pulse goes through two signal transitions: from 0 to 1 and the
return from 1 to 0. As shown in figure the positive transition is defined as
the positive edge and the negative transition as the negative edge.

If the flip-flop is made to respond to the positive (or negative) edge

transition only, instead of the entire pulse duration, then the multiple-
transition problem can be eliminated.

014
Master-Slave Flip-Flop
A master-slave flip-flop is constructed from two separate flip-flops. One
circuit serves as a master and the other as a slave i.e. master is positively
clocked and slave is negatively clocked. The logic diagram of an SR flip-
flop is shown below. The master flip-flop is enabled on the positive edge
of the clock pulse CP and the slave flip-flop is disabled by the inverter.
The information at the external R and S inputs is transmitted to the master
flip-flop. When the pulse returns to 0, the master flip-flop is disabled and
the slave flip-flop is enabled. The slave flip-flop then goes to the same
state as the master flip-flop.

The timing relationship is shown in figure 10 and is assumed that the flip-
flop is in the clear state prior to the occurrence of the clock pulse. The
output state of the master-slave flip-flop occurs on the negative transition
of the clock pulse. Some master-slave flip-flops change output state on
the positive transition of the clock pulse by having an additional inverter
between the CP terminal and the input of the master.

015
Summery :

016
 Chapter 5
Counters and Registers
Counter is an instrument, the main purpose of which is to count the
number of pulses received in a given time interval.
Counters can be classified into two broad categories according to
the way they are clocked:
1. Synchronous counter: All flip-flops in a synchronous counter
receive the same clock pulse and so change state simultaneously.
2. Asynchronous (Ripple) Counters - the first flip-flop is clocked by
the external clock pulse. Flip-flops transitions ripple through from
one flip-flop to the next in sequence until all flip-flops reach a new
stable value (state).

Ripple Counters
A Ripple Counter consists of two flip flop is shown on the figure. The
external clock is connected to the clock input of the first flip-flop (FF0)
only. So, FF0 changes state at the falling edge of each clock pulse, but
FF1 changes only when triggered by the falling edge of the Q output of
FF0. Because of the inherent propagation delay through a flip-flop, the
transition of the input clock pulse and a transition of the Q output of FF0
can never occur at exactly the same time. Therefore, the flip-flops cannot
be triggered simultaneously, producing an asynchronous operation.
Usually, all the CLEAR inputs are connected together, so that a single
pulse can clear all the flip-flops before counting starts. The 2-bit ripple
counter circuit above has four different states, each one corresponding to
a count value. Similarly, a counter with n flip-flops can have 2 to the

017
power n states =2n. The number of states in a counter is known as its
mod (modulo) number. Thus a 2-bit counter is a mod-4 counter.

The following is a three-bit asynchronous binary counter and its

timing diagram for one cycle. It works exactly the same way as a two-bit
asynchronous binary counter mentioned above, except it has eight states
due to the third flip-flop.

018
 Shift registers
Shift registers are a type of sequential logic circuit, mainly for storage of
digital data. They are a group of flip-flops connected in a chain so that
the output from one flip-flop becomes the input of the next flip-
flop. Most of the registers possess no characteristic internal sequence of
states. All the flip-flops are driven by a common clock, and all are set or
reset simultaneously. The basic types of shift registers are :

 Serial In - Serial Out

 Serial In - Parallel Out
 Parallel In - Serial Out
 Parallel In - Parallel Out
 bidirectional shift registers.

Serial In - Serial Out Shift Registers

A basic four-bit shift register can be constructed using four D flip-flops,
as shown below. The operation of the circuit is as follows. The register
is first cleared, forcing all four outputs to zero. The input data is then
applied sequentially to the D input of the first flip-flop on the left
(FF0). During each clock pulse, one bit is transmitted from left to
right. Assume a data word to be 1001. The least significant bit of the
data has to be shifted through the register from FF0 to FF3.

019
 FF0 FF1 FF2 FF3
0 0 0 0
1 0 0 0
0 1 0 0
0 0 1 0
1 0 0 1

Example
If a four bit number (1011) is applied to the input of the first flip-flop.
After four clock pulses this number will be at the output of the flip-flop.
In this manner, a four bit number can be stored in the register. After four

001
more clock pulses, this data will be shifted out of the

register.

Serial In - Parallel Out Shift Registers

A construction of a four-bit serial in - parallel out register is shown
below.

000
Data is fed into the SERIAL IN/PARALLEL OUT shift register bit by bit,
in the same way as for the SISO shift register. However the four bits are all
shifted out simultaneously, in parallel, as one word.

Parallel In - Serial Out Shift Registers

A four-bit parallel in - serial out shift register is shown below. The
circuit uses D flip-flops and NAND gates for entering data (ie writing) to
the register.

D0, D1, D2 and D3 are the parallel inputs, where D0 is the most
significant bit and D3 is the least significant bit. To write data in, the
mode control line is taken to LOW and the data is clocked in. The data
can be shifted when the mode control line is HIGH as SHIFT is active
high. The register performs right shift operation on the application of a
clock pulse, as shown in the animation below.

002
With the PARALLEL IN/SERIAL OUT shift register, four bits
are shifted into the register simultaneously, in parallel. They are then
clocked out, one after the other, in serial form.

Parallel In - Parallel Out Shift Registers

For parallel in - parallel out shift registers, all data bits appear on the
parallel outputs immediately following the simultaneous entry of the data
bits. The following circuit is a four-bit parallel in - parallel out shift
register constructed by D flip-flops.

The D's are the parallel inputs and the Q's are the parallel outputs. Once
the register is clocked, all the data at the D inputs appear at the
corresponding Q outputs simultaneously.

003
The shift register is loaded with four bits simultaneously, in parallel. They
are also clocked out simultaneously, in parallel.

Bidirectional Shift Registers

A bidirectional, or reversible, shift register is one in which the data can be
shift either left or right.

Shift Register Counters

A special form of counter - the shift register counter Serial In - Serial Out
Shift Registers

Ring Counters
A ring counter is basically shift register in which the output of the most
significant stage is fed back to the input of the least significant stage. The
following is a 4-bit ring counter constructed from D flip-flops. The
output of each stage is shifted into the next stage on the positive edge of a
clock pulse. If the CLEAR signal is high, all the flip-flops except the first
one FF0 are reset to 0. FF0 is preset to 1 instead.

004
Since the count sequence has 4 distinct states, the counter can be
considered as a mod-4 counter. Only 4 of the maximum 16 states are
used, making ring counters very inefficient in terms of state usage. But
the major advantage of a ring counter over a binary counter is that it is
self-decoding. No extra decoding circuit is needed to determine what
state the counter is in.

Memory unit
–a collection of cells capable of storing a large quantity of binary
information and to which binary information is transferred for
storage from which information is available when needed for
processing together with associated circuits needed to transfer
information in and out of the device
• write operation: storing new information into memory
• read operation: transferring the stored information out of the
memory
• Two major types

005
–RAM (Random-access memory): Read + Write
• accept new information for storage to be available later for use
–ROM (Read-only memory): perform only read operation
Programmable Logic Device
•Programmable logic device (PLD)
–an integrated circuit with internal logic gates
• hundreds to millions of gates interconnected through hundreds to
thousands of internal paths
–connected through electronic paths that behave similar to fuse
• In the original state, all the fuses are intact
–programming the device
• blowing those fuse along the paths that must be removed in
order to obtain particular configuration of the desired logic
function
•Types
–Read-only Memory (ROM)
–programmable logic array (PLA)
–programmable array logic (PAL)
–field-programmable gate array (FPGA)

006
 Chapter (6)
Number Systems

Many number systems are in use in digital technology. The most common
are the decimal, binary, octal, and hexadecimal systems. The decimal
system is clearly the most familiar to us because it is a tool that we use
every day. Examining some of its characteristics will help us to better
understand the other systems. In the next few pages we shall introduce
four numerical representation systems that are used in the digital system.
There are other systems, which we will look at briefly.
 Decimal
 Binary
 Octal
 Hexadecimal

Decimal System
The decimal system is composed of 10 numerals or symbols. These 10
symbols are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9. Using these symbols as digits of a
number, we can express any quantity. The decimal system is also called
the base-10 system because it has 10 digits.
103 102 101 100 10-1 10-2 10-3
=1000 =100 =10 =1 . =0.1 =0.01 =0.001
Most Least
Decimal
Significant Significant
point
Digit Digit

007
Even though the decimal system has only 10 symbols, any number of any
magnitude can be expressed by using our system of positional weighting.

Decimal Examples
 3.1410
 5210
 102410
 6400010

Binary System
In the binary system, there are only two symbols or possible digit values,
0 and 1. This base-2 system can be used to represent any quantity that can
be represented in decimal or other base system.

23 22 21 20 2-1 2-2 2-3

=8 =4 =2 =1 . =0.5 =0.25 =0.125
Least
Most Significant
Binary point Significant
Digit
Digit

Binary Counting
The Binary counting sequence is shown in the table:
23 22 21 20 Decimal
0 0 0 0 0
0 0 0 1 1

008
 0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9
1 0 1 0 10
1 0 1 1 11
1 1 0 0 12
1 1 0 1 13
1 1 1 0 14
1 1 1 1 15

Octal System
The octal number system has a base of eight, meaning that it has eight
possible digits: 0,1,2,3,4,5,6,7.
83 82 81 80 8-1 8-2 8-3
=512 =64 =8 =1 . =1/8 =1/64 =1/512
Least
Most Significant
Octal point Significant
Digit
Digit

009
Octal to Decimal Conversion
 2378 = 2 x (82) + 3 x (81) + 7 x (80) = 15910
 24.68 = 2 x (81) + 4 x (80) + 6 x (8-1) = 20.7510
 11.18 = 1 x (81) + 1 x (80) + 1 x (8-1) = 9.12510
 12.38 = 1 x (81) + 2 x (80) + 3 x (8-1) = 10.37510
Hexadecimal System
The hexadecimal system uses base 16. Thus, it has 16 possible digit
symbols. It uses the digits 0 through 9 plus the letters A, B, C, D, E, and
F as the 16 digit symbols.

163 162 161 160 16-1 16-2 16-3

=4096 =256 =16 =1 . =1/16 =1/256 =1/4096
Most Hexa Least
Significant Decimal Significant
Digit point Digit

Hexadecimal to Decimal Conversion

 24.616 = 2 x (161) + 4 x (160) + 6 x (16-1) = 36.37510
 11.116 = 1 x (161) + 1 x (160) + 1 x (16-1) = 17.062510
 12.316 = 1 x (161) + 2 x (160) + 3 x (16-1) = 18.187510

Code Conversion
Converting from one code form to another code form is called code
conversion, like converting from binary to decimal or converting from
hexadecimal to decimal.

021
Binary-To-Decimal Conversion
Any binary number can be converted to its decimal equivalent simply by
summing together the weights of the various positions in the binary
number which contain a 1.

Binary Decimal
110112
24+23+01+21+20 =16+8+0+2+1
Result 2710

and

Binary Decimal
101101012
27+06+25+24+03+22+01+20 =128+0+32+16+0+4+0+1
Result 18110

You should have noticed that the method is to find the weights (i.e.,
powers of 2) for each bit position that contains a 1, and then to add them
up.
Example
110100 = 1x25 + 1x24 + 0x23 + 1x22 + 0x21 + 0x20
= 32 + 16 + 0 + 4 +0 +0 +52
The same approach applies to non-integral numbers.
Example
110.101 = 1x22 + 1x21+0x20+1x2-1+0x2-2 + 1x2-3
= 4 + 2 + 0 + 0.5 + 0 + 0.125 = 6.625

020
Decimal-To-Binary Conversion
There are 2 methods:
 Reverse of Binary-To-Decimal Method
 Repeat Division

Reverse of Binary-To-Decimal Method

Decimal Binary
4510 =32 + 0 + 8 + 4 +0 + 1
=25+0+23+22+0+20
Result =1011012

Repeat Division-Convert decimal to binary

This method uses repeated division by 2.

Convert 2510 to binary

Answer
Division Remainder Binary
25/2 = 12+ remainder of 1 1 (Least Significant Bit)
12/2 = 6 + remainder of 0 0
6/2 = 3 + remainder of 0 0
3/2 = 1 + remainder of 1 1
1/2 = 0 + remainder of 1 1 (Most Significant Bit)
Result 2510 = 110012

022
Convert 57.4801dec to its binary equivalent to 14-bit accuracy.
Answer
As the decimal number has both an integer and a fractional part the
problem has to be done in two steps
First take the integer part i.e. 57 and repeatedly divide by 2 noting
the remainders of each division.

57 / 2 = 28 remainder 1 lsb

28 / 2 = 14 remainder 0

14 / 2 = 7 remainder 0

7 / 2 = 3 remainder 1

3 / 2 = 1 remainder 1

1 / 2 = 0 remainder 1 msb

The binary equivalent of 57dec is therefore given by the remainders

ordered from most significant bit (msb) to least significant bit (lsb) and is
hence 1110001
The fractional part is given by repeatedly multiplying by 2 and
storing the carries (when the result of the multiplication exceeds 1) until
the required bit accuracy is reached.

.4801 x 2 = .9602 + 0

.9602 x 2 = .9204 + 1

.9204 x 2 = .8408 + 1

.8408 x 2 = .6816 + 1

.6816 x 2 = .3632 + 1

.3632 x 2 = .7264 + 0

.7264 x 2 = .4528 + 1

023
and so
57.4801dec = 111001.0111101

Binary-To-Octal / Octal-To-Binary Conversion

Octal Digit 0 1 2 3 4 5 6 7
Binary
000 001 010 011 100 101 110 111
Equivalent

Each Octal digit is represented by three binary digits.

Example:
100 111 0102 = (100) (111) (010)2 = 4 7 28

Repeat Division-Convert decimal to octal

This method uses repeated division by 8.

Example: Convert 17710 to octal and binary

Division Result Binary
177/8 = 22+ remainder of 1 1 (Least Significant Bit)
22/ 8 = 2 + remainder of 6 6
2/8 = 0 + remainder of 2 2 (Most Significant Bit)
Result 17710 = 2618
Binary = 0101100012

024
Hexadecimal to Decimal/Decimal to Hexadecimal Conversion
Example:
2AF16 = 2 x (162) + 10 x (161) + 15 x (160) = 68710

Repeat Division- Convert decimal to hexadecimal

This method uses repeated division by 16.
Example: convert 37810 to hexadecimal and binary:

Division Result Hexadecimal

378/16 = 23+ remainder of 10 A (Least Significant Bit)23
23/16 = 1 + remainder of 7 7
1/16 = 0 + remainder of 1 1 (Most Significant Bit)
Result 37810 = 17A16
Binary = 0001 0111 10102

Binary-To-Hexadecimal Hexadecimal-To-BinaryConversion
Hexadecimal Digit 0 1 2 3 4 5 6 7
Binary Equivalent 0000 0001 0010 0011 0100 0101 0110 0111
Hexadecimal Digit 8 9 A B C D E F
Binary Equivalent 1000 1001 1010 1011 1100 1101 1110 1111
Each Hexadecimal digit is represented by four bits of binary digit.
Example:
1011 0010 11112 = (1011) (0010) (1111)2 = B 2 F16
Example:
Convert the binary number 1101101101101 to its hexadecimal
equivalent.

025
Answer:
The binary number 1101101101101 has 13 digits. First extend this to a
multiple of 4 (i.e. 16) by adding three leading 0s to the number, i.e.
11011011001101 becomes 0001101101101101
Next break the binary number up into nibbles (4-bit groups) and convert
each nibble to its hexadecimal equivalent.

Binary 0001 1011 0110 1101

Hexadecimal 1 B 6 D

hence
1101101101101 = 1B6Dhex

Octal-To-Hexadecimal Hexadecimal-To-Octal Conversion

 Convert Octal (Hexadecimal) to Binary first.
 Regroup the binary number by three bits per group starting from
LSB if Octal is required.
 Regroup the binary number by four bits per group starting from
LSB if Hexadecimal is required.

Example:
Convert 5A816 to Octal.
Hexadecimal Binary/Octal
5A816 = 0101 1010 1000 (Binary)
= 010 110 101 000 (Binary)
Result = 2 6 5 0 (Octal)

026
Binary Addition
Binary addition is completely straightforward and is done in the same
way as standard decimal addition remembering that, in binary terms "one
plus one equals zero carry one". This is also true for fractional binary
numbers as illustrated below.
Binary Decimal Binary Decimal Binary Decimal

101 5 1001.1 9.5 110.1101 6.8125

+110 +6 1100.1 +12.5 +100.1010 +4.6250

____ __ _______ ____ _________ _______

1011 11 10110.0 22.0 1011.0111 11.4375

Binary Subtraction
Binary subtraction usually takes place by complementing i.e. subtraction
is via the addition of negative numbers. This technique requires the use of
the so-called ones (1's) complement and twos (2's) complement of a
binary number.
The 1's complement of a binary number is formed simply by
complementing each digit in turn. The 2's complement of a binary
number is formed by adding 1 to the least significant bit of the 1's
complement (Note in the case of fractional binary numbers this is not the
same as adding 1 to the 1's complement number - see below).
Decimal Binary 1's Complement 2's Complement

5 00000101 11111010 11111011

27 00011011 11100100 11100101

76 01001100 10110011 10110100

4.625 0100.1010 1011.0101 1011.0110

027
Note that in order to correctly express the 1's complement and 2's
complement binary numbers a fixed length format must be chosen (8-bit
in the case above) and leading zeroes must be included when writing the
original pure binary format number.
Finally, in order to represent a negative binary number the MSB
becomes a sign bit i.e. if the MSB=1 then the number is negative, if the
MSB=0 then the number is positive, and so, e.g. 00010011 = +19 and
10010011 = -19. This is called true magnitude format.

In order to perform binary subtraction the rules are as follows:

 When the sum to be performed is A-B then the number to be
subtracted (B) is converted to its 2's complement form and then
added to A using standard binary addition.
 If, after the addition, the sign bit = 1 then a further 2 steps must be
performed :
o first take the 2's complement of the result;
o then make the sign bit of the new number equal to 1;
o interpret the result in true magnitude format.
 For sums of the form -A-B then take the 2's complement of A, add
it to the 2's complement of B and then proceed as above;
 Sums of the form -A-(-B) can be converted to B-A before
proceeding as above.
EXAMPLE
Perform the following sums using binary numbers:
1. 75-42
2. -75-42
3. -75-(-42)

028
Answer:
First we choose to use 8-bit true magnitude format. In this format:
+75 = 01001011 ; + 42 = 00101010

1. 01001011 +75 in true magnitude format

+11010110 2's complement of +42
________
00100001 this is +33 in true magnitude format

2. 10110101 2's complement of +75

+11010110 2's complement of +42
________
10001011 sign bit is 1 so perform 2's complement
01110101 2's complement of last line
11110101 replace sign bit
________
11110101 -117 in true magnitude format

3. -75-(-42) = -75+42 = 42-75 and so

00101010 +42 in true magnitude format
+10110101 2's complement of +75
________
11011111 sign bit is 1 so perform 2's complement
00100001 2's complement of last line
10100001 replace sign bit
________
10100001 -33 in true magnitude format

029
Binary Multiplication and Binary Division
Binary multiplication and binary division are both most easily done by
long multiplication and division methods as often taught for standard
decimal numbers.
In both cases all numbers must be in true magnitude format but
with sign bits removed. For multiplication each partial product is
calculated and then all partial products are summed using standard binary
addition. For division it proceeds like decimal division. Finally the sign
of the product or quotient is determined by summing all sign bits and
retaining the LSB only of the resultant sum.

References
 M. Morris Mano, "Digital Design" Third Edition.
 M. RAFIQUZZAMAN " Fundamentals of Digital Logic and
Microcomputer Design" Fifth Edition.
 Mark Balch " COMPLETE DIGITAL DESIGN".
 http://www.electronicshub.org/multiplexer-and dempltiplexer
 https://www.tutorialspoint.com/digital_circuits/digital_circuits_pr
ogrammable_logic_devices.htm
 https://www.philadelphia.edu.jo/academics/qhamarsheh/uploads/L
ecture%2012%20Binary%20Adder-Subtractor.pdf
 https://faculty.ksu.edu.sa/sites/default/files/unit-5-
combinational_circuit-1.pdf

031