INTEGRATION, the VLSI journal 78 (2021) 11–24

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Integration

journal homepage: www.elsevier.com/locate/vlsi

An ant colony based mapping o quantum circuits to nearest

neighbor architectures
Anirban Bhattacharjee a, Chandan Bandyopadhyay c, *, Angshu Mukherjee a, Robert Wille b,
Rol Drechsler c, Hazur Rahaman a
a
Indian Institute of Engineering Science and Technology Shibpur, 711103, India
b
Institute for Integrated Circuits, Johannes Kepler University Linz, A-4040, Linz, Austria
c
Institute of Computer Science, University of Bremen & Cyber-Physical Systems, DFKI GmbH, 28358, Bremen, Germany

A R T I C L E I N F O A B S T R A C T

Keywords: Although this decade is witnessing tremendous advancements in abrication technologies or quantum circuits,
Quantum circuit this industry is acing several design challenges and technological constraints. Nearest Neighbor (NN) enorce-
Quantum gate ment is one such design constraint that demands the physical qubits to be adjacent. In the last couple o years,
Nearest neighbor(NN)
this domain has made progress starting rom designing advanced algorithms to improved synthesis methodol-
SWAP gate
ogies, even though developing ecient design solutions remains an active area o research.
Here, we propose such a synthesis technique that eciently transorms quantum circuits to NN designs. To
nd the NN solution, we have taken help o an ant colony algorithm which completes the circuit conversion in
two phases: in the rst phase, it nds the global qubit ordering or the input circuit and, in the second phase, a
heuristic driven look-ahead scheme is executed or local reordering o gates. The proposed algorithm is rst tted
into a 1D design and, later, mapped to 2D and 3D congurations. The combination o such heuristic and the
meta-heuristic schemes has resulted promising solutions in the transormation o quantum circuits to NN-
compliant architectures. We have tested our algorithm over a wide spectrum o benchmarks and comparisons
with state-o-the-art design approaches showed considerable improvements.

1. Introduction (like the CNOT constraint in IBM QX architecture [5] or the Nearest
Neighbor restriction [6], which demands the control and target qubits o
The era o computation has rapidly expanded and is reaching new implementing gates to be adjacent) which need to addressed and such
statures beyond the capabilities o the conventional computing para- restrictions have originated as dierent quantum circuit implementing
digm. The emergence o quantum computing has added a new dimen- architectures demand its own set o constraints to be satised. For
sion to this rapidly growing computing world. By exploiting quantum example, in ault-tolerant representation o quantum circuits, imple-
mechanical properties, quantum computing not only provides quantum menting quantum error correction [7] codes like surace code [8] or
parallelism and enormous speed-up in computation but it also promises Steane codes [9] demand nearest neighbor (NN) architectures, as the
to solve complex problems like prime actorization [1], database search qubits not satisying NN constraint are aected by the quantum noise
[2], or solving large sets o linear equations [3] or which no such e- leading to high volume o computational errors [10]. To reduce such
cient classical algorithms exist [4]. errors requires the qubits to interact with its adjacent neighbors as
In the last couple o years, this eld has witnessed tremendous ad- suggested experimentally. In this regard, NN qubit interaction has
vancements in the development o quantum hardware to abrication become a severe design limitation or some o the quantum technologies
technologies. Now, this emerging eld is gradually entering to the like ion-trap [11], nuclear magnetic resonance [12], quantum dots [13]
design automation realm as well where the necessity o developing and superconducting qubits [14].
advanced quantum algorithms and also addressing the technological The standard process o achieving such NN realization is by intro-
constraints is observed. Even it is seen that there exist many obstructions ducing SWAP gates [15] into given circuit that interchanges the states o

* Corresponding author.
E-mail addresses: [email protected] (A. Bhattacharjee), [email protected] (C. Bandyopadhyay), [email protected]
(A. Mukherjee), [email protected] (R. Wille), [email protected] (R. Drechsler), [email protected] (H. Rahaman).

https://doi.org/10.1016/j.vlsi.2020.12.002
Received 21 April 2020; Received in revised orm 3 November 2020; Accepted 11 December 2020
Available online 8 January 2021
0167-9260/© 2021 Elsevier B.V. All rights reserved.
A. Bhattacharjee et al. Integration 78 (2021) 11–24

the qubits and brings non-adjacent interacting qubits into adjacent po- ormulated. In Re. [24], a novel look-ahead scheme has been shown,
sitions. While making any gate NN-compliant, it might be required to where the eect o good heuristics on local optimization has been
insert one or more SWAPs until interacting qubits become adjacent. explored and substantial reduction in SWAP overhead was observed in
Following such an approach in turn causes overhead as it increases the the experimental ndings. To make a tradeo between scalability and
depth and latency in the resulting NN realization. Reducing such SWAP SWAP requirement, in Re. [31], rst qubits are rearranged using a
gate count is considered a prime objective and in last ew years several global reordering approach and then have executed a local reordering
investigations on ecient NN transormation policies are reported strategy or ecient placement o SWAPs in required positions. In
where dierent design strategies and topological layouts like Linear Re. [31], the authors have shown the way o representing NN archi-
Nearest Neighbor (LNN) architecture, 2D and 3D based designs are tectures in 3D and nD platorms. Although several works on 2D-, 3D-,
considered. In the ollowing we are reviewing some o the synthesis and recently in nD-based representation is shown, the involved mapping
works on NN design fow. turns complex once the underlying topology changes to higher
dimension.
1.1. Related works
1.2. Problem formulation
The problem o LNN transormation o quantum circuits has been
considered in Re. [6], where various optimization approaches like We already have discussed that quantum circuit implementing
template matching, reordering schemes (global, local) are presented. technologies like NMR, IoN Trap demand NN constraint enorcement in
Advancing the previous design fow, in Re. [16], a dierent NN con- implementing circuits, so, in one direction we need NN transormation
version technique has been proposed which urther reduces the algorithms but we also need to turn them ecient so that the design cost
complexity o the resulting circuit both in terms o overhead and time. is reduced.
Improving the NN representation using circuit decomposition approach Aiming to develop an ecient NN conversion model or quantum
is introduced in Re. [17], where rst the circuit is partitioned into circuits, here we show an improved synthesis workfow to transorm
sub-circuits and, then, LNN solutions or each sub-circuit is obtained by non–NN–based designs to NN-based structures with minimal number o
ormulating the synthesis problem into a MINLA (Minimum Linear SWAP gates. Here, we also explore the eects o dierent topological
Arrangement (MINLA). This is considered as the graph layout based representations in making NN-compliant designs in dierent dimensions
problem, which deals with the placement o vertices such that a path (1D, 2D and 3D). In our synthesis algorithm, we have used both global
(sequence o edges) with minimum weight is obtained. Reduction o and local reordering schemes to improve the solutions.
SWAP overhead by mapping quantum circuits into a lattice structures In the global reordering phase, we use ant colony algorithm and
has been developed in Re. [18], where a complete logic design fow or mapped this search algorithm to a low cost based graph traversal
LNN transormation is presented. Applications o graph-partitioning problem by changing the objective unction, where we have integrated
algorithms in obtaining ecient NN architectures have been devel- roulette-wheel strategy to avoid getting stuck at local optima. For better
oped in Re. [19]. Although the above stated synthesis techniques solutions, we have used improved heuristics and tuned unction’s pa-
improve the design overhead by reducing SWAP usage, they do not rameters accordingly in the searching technique.
ensure optimality in SWAP utilization. Towards addressing this issue, in Further to improve the results (in terms o SWAP utilization) that we
Res. [20,21] and in Re. [22], exact approaches are developed to nd obtained rom global reordering phase, next we execute a window based
optimal solutions but such synthesis schemes scale or small benchmarks look-ahead policy where we have experimented with dierent look-
only. To enable NN transormation or larger circuits with sub-optimal ahead criteria and window size to explore the impact o such parame-
solutions space, a look-ahead based heuristic approach has been devel- ters over NN cost. For nding the useulness o both the ordering ap-
oped in Re. [23]. Approaches similar to Re. [23], with improved proaches, we have tested this joint transormation ramework over 1D-,
look-ahead strategies, are given in Res. [24,25], where dierent win- 2D- and 3D based designs. In the experimental ndings, we have wit-
dowing criteria are undertaken to improve the solution space. nessed that our scheme has resulted improved solutions compared to
In addition to the 1D representation, quantum circuits can also be some state-o-the-art NN works.
mapped into higher dimensional architectures like 2D, 3D where qubits The rest o the paper is structured as ollows. Section II provides an
interactions increase as the number o adjacent neighbors increase. Like overview about the undamentals o quantum computing along with
the dierent 1D-based transormation schemes, ecient design algo- nearest neighbor realization o quantum circuit. Discussion o NN
rithms or 2D and 3D representations also have been reported. Such a transormation methodology based on the proposed model is outlined in
work is reported in Re. [26], where mixed integer programming is used section III. Experimental ndings and analysis over our design technique
to nd the nal NN ordering in 2D architecture and this work has shown is summarized in section IV. Finally, concluding remarks with uture
some promising results compared to some well-known 1D works. Like scope o our design model are outlined in section V.
1D-based optimal strategies, an exact approach or 2D based NN opti-
mization has been proposed in Re. [27] and this approach has shown 2. Background
very promising results or smaller circuits leading to optimal solutions
but cannot be scaled or large benchmark circuits. 2.1. Quantum computing
Although exact approaches provide optimal solutions, they lack in
processing large circuits due the high computational time. So, as an A qubit is the basic quantum inormation unit used on quantum
alternative, researchers start ocusing on heuristic and meta-heuristic computers. Unlike the classical bit that has only two states, qubits can
approaches, which retain a trade-o between level o scalability and occur in several states and such states can be expressed as a linear
optimality. Such an approach has been reported in Re. [28], where an combination o basis states |0 and |1. It can be represented in the orm o
intelligent qubit mapping based NN scheme or 2D representation is a state vector |ξ〉
developed which not only determines improved structures and produces
|ξ〉 = α|0〉 + β|1〉 (1)
ast results but also scales well or large circuits. The cost-eective
representation o NN based designs by placing the qubits using where α and β in the above expression represent complex numbers
HS-based meta-heuristic scheme ollowed by a local reordering indicating probability amplitude values o basis states |0 and |1 pro-
approach has been developed in Re. [29]. Similar to work [29], an vided the condition |α|2 + |β|2 = 1 is satised. Thus, or any general n-
improved solution based on 2D transormation technique has been qubit system there exist 2n computational basis states which can occur
developed in Re. [30], where an ecient heuristic mapping strategy is simultaneously. These quantum states cannot be detected directly as

12
A. Bhattacharjee et al. Integration 78 (2021) 11–24

Fig. 1. (a): SWAP gate and its decomposed representation. B): Transer matrix or SWAP gate.

Fig. 2. (a): non NN representation with NN Cost = 3. (b): NN-compliant representation or Fig. 2(a).

measurement causes it to collapse into one o the basis states (|0 or |1). c) controlled-V (CV) gate – It is a two qubit quantum gate considered as
Quantum gates operate on qubits and a cascade o such gates orm a the square root o NOT gate (V = √ (NOT)). The operation o this
quantum circuit. The quantum gates are represented by unitary matrices gate can be described by the ollowing transormation matrix
and when a set o quantum gates with certain unctionalities is grouped  
together then it orms a gate library. NCV [32], NCVW [33], Cliord + T 1 0 0 0
 
[34] are some o the well-known gate libraries used in dierent logic 0 1
 0 0  
level representations, or example, when basic representation is required 
 1+i 1i 

then NCV library is used, or more decomposed representation NCVW is CV =  
0 0 2 2 
 
used and or deriving ault-tolerant designs Cliord + T is used. In this  
 0 0 1i 1+i 
work, we will limit our discussion to NCV circuit representation only.
Three elementary quantum gates NOT, controlled-NOT (CNOT) and 2 2
controlled-V/V† constitute NCV library. All o these gates perorm
dierent unitary transormation operations and have distinct properties d) controlled-V† (CV†) – This gate perorms an inverse operation o
which are discussed next. controlled–V gate (V† = V1) and holds the property VV† = I. This
gate can be represented as
a) NOT (X) gate – This is a single input quantum gate perorms the
 
inversion operation o qubit. The unitary matrix representation or 1 0 0 0
this gate is as ollows: 
0 1 0 0 

   
 
0 1  1i 1+i 
X= CV † =  
1 0 0 0 2 2 
 
 
 0 0 1+i 1i 
b) CNOT gate – It is a two-input quantum gate which complements the 2 2
target bit value depending on the state o the control input. I the
control input is at state |1 then the target bit is complemented
otherwise let unchanged and this operation can be represented 2.2. Nearest neighbor quantum circuits
using the unitary matrix
  Physical limitations o quantum technologies demand quantum gates
1 0 0 0 to act only on qubits placed at adjacent positions and this condition is
0 1 0 0
CNOT =  reerred as the Nearest Neighbor criteria. To achieve such design
0 0 0 1
0 0 1 0 constraint, a specially designated gate called SWAP is placed beore
those gates whose qubits are non-adjacent. SWAP is a two-input quan-
tum gate consisting o a cascade o three CNOT gates with control and
target inputs placed at alternate lines. The structure o SWAP gate and its

13
A. Bhattacharjee et al. Integration 78 (2021) 11–24

Fig. 3. (a): Global reordered circuit o Fig. 2(a). (b): NN circuit o Fig. 3(a). (c): NN circuit obtained using local reordering scheme o Fig. 3(a).

reordering scheme is represented in Fig. 3(c).

Example 3. Now consider a situation where instead o applying the
reordering schemes individually over Fig. 2(a), both ordering schemes
are executed together. First, global reordering policy is applied on the
given circuit where the initial qubit order q1q2q3q4 is changed to
q3q4q2q1. Next, we apply local reordering policy over the resulting cir-
cuit. The nal NN-compliant circuit obtained using such combined
strategy is shown in Fig. 4. By investigating Fig. 3(b) and (c), it is
observed that only two SWAP gates are needed to realize the NN ar-
chitecture i global and local reordering policies are executed separately.
However, the application o both these reordering reduces the SWAP
Fig. 4. NN-compliant circuit using global with local. cost to one.

composition is depicted in Fig. 1(a) while its matrix representation is 3. Proposed method
shown in Fig. 1(b)
Example 1. Consider a quantum circuit shown in Fig. 2(a) containing Here, we propose a synthesis workfow or ecient transormation o
ve gates acting over qubits q1, q2, q3 and q4. This given circuit repre- quantum circuits to NN-based designs. Our approach is driven by a
sentation does not ulll the nearest neighbor condition as the second heuristic method, where both reordering schemes are implemented
and ourth quantum gates operate on non-adjacent qubits. The corre- jointly and the mappings are perormed on 1D, 2D and 3D platorms.
sponding NN representation is realized by adding SWAP gate beore gate We have tted our objective unction into an ant colony based search
g3 and g5. But ater bringing the qubits at adjacent positions, additional problem that nds linear qubit sequence or the input circuit. For higher
SWAPs are again inserted to restore the original qubit positions and the dimensional representations (2D and 3D), we use an additional mapping
nal design is obtained in Fig. 2(b). unction or projecting this linear qubit ordering into higher topological
The resulting NN circuit obtained using this naive approach requires structures. Finally, dierent variants o local reordering schemes are
six SWAP gates. However, more improved realizations are possible with executed by exploiting the possible paths between non-adjacent inter-
the help o global [6] and local reordering policies [23]. acting qubits and by changing the look-ahead criteria. Next, we present
In global reordering, initially the original qubit positions are altered our synthesis workfow.
and then SWAP gates are inserted. But as it changes the circuit unc-
tionality, again reverse SWAPs are added to restore the original qubit 3.1. Global reordering
ordering. But in local reordering, the original qubit ordering is not
changed. It adds SWAPs only beore the gates with non-adjacent qubits The main objective o this phase is to nd best possible input qubit
and uses the resultant qubit positions or the remaining gates in the order or the circuit. Here, rst we model the objective unction o ant
circuit. colony algorithm to a graph problem and subsequently map qubit
Example 2. For the circuit shown in Fig. 2(a), instead o directly interaction to the traversal cost o the graph. In our approach, we have
applying SWAP gates using naive method, consider that the initial qubit integrated roulette-wheel strategy to expand search spaces and to avoid
order q1q2q3q4 has been changed to q2q1q4q3. The reordered circuit and getting stuck at local optima. To improve results, we have tuned some
its corresponding NN implementation are depicted in Fig. 3(a) and Fig. 3 parameters in the algorithm and continue searching until the solution
(b), respectively. Similarly, the resulting NN circuit obtained using local saturates.
This global reordering process is done in three phases 1) Circuit

14
A. Bhattacharjee et al. Integration 78 (2021) 11–24

Fig. 5. (a): Input Benchmark (4gt11_84). (b): Block representation o circuit in Fig. 5(a).

3.1.2. Phase II: mapping partitioned circuit to a complete graph based

solution
In this phase, a complete graph is constructed or the blocked circuit
representation, where the vertices o the graph represent qubits o the
given circuit and the edges refect interaction between qubits. The ver-
tex or node weight o the graph indicates the amount o interaction that
particular qubit makes in the block partitioned circuit. For this purpose,
circuit specications along with block actors computed in the previous
phase are used here. Calculation o node weight (Nqj) or any qubit qj
using block actor value BF(Bi) is as ollows
3
∑   
Nqj = I qj , i * BF (Bi ) (4)
i=1

where I(qj,i) represents the total interaction o qubit qj in block Bi.

Similarly, edge weights (Eab) between any two qubits qa and qb in the
graph is estimated using the ollowing expression
3
∑
Eab = (1/tab )i (5)
i=1

where tab represents the time at which gates with input qubits qa and qb
Fig. 6. (a): Graphical representation or benchmark circuit 4gt11_84. Fig. 6 (a):
interact. Eqn.(6) determines the summation o edge weights between the
Pheromone matrix representation. (c): Visibility matrix or Fig. 6(b).
qubits (qa, qb) by considering the reciprocal o the timestamp values o
these qubits interacting within each block segment.
partitioning 2) Graphical representation o partitioned circuit and 3)
For better apprehension o circuit partitioning and graph represen-
employing a probabilistic method or nal qubit sequence.
tation phases, consider the ollowing example.

3.1.1. Phase I: circuit partitioning Example 4. Consider benchmark circuit 4gt11_84 shown in Fig. 5(a)
In this phase, any input circuit is partitioned into three block seg- containing seven quantum gates acting between ve qubit lines q1, q2,
ments as B1, B2 and B3. To compute the size o each block (number o q3, q4 and q5. By ollowing the criteria mentioned in Eqn. (2), the circuit
gates in each block) the ollowing expression is used as is partitioned into three blocks B1, B2, B3, where B1 = 3, B2=3 and B3=1.
The block actor values or the corresponding partitioned segments are
Bi = N/3 for i = 1 to 3 (2)
computed as BF(B1)=(1/(1+2+3)1)=(1/6)1=0.1666, BF(B2)= 0.00443,
BF(B3)= 0.002911 using Eqn. (3).
where the symbols N and Bi represent the total gate count and the ith
Next, using the previously computed values, we orm a complete
block number, respectively. I the above expression does not satisy the
graph in Fig. 6(a), where the node weights and the edge weights in the
divisibility condition (N modulo 3 = = 0), then we allocate equal
graph are computed using the expressions given in Eqn. (4) and Eqn. (5).
number o gates in rst two blocks B1 and B2 while assign the remaining
For example, the node weight (Nq5) or node q5, is computed as
gates to block B3.
Nq1=0*0.1666
Furthermore, each o these blocks have been assigned an index value
+1*0.00443+1*0.002911=0+0.00443+0.002911=0.007341. The
which is estimated as
edge weight between nodes q1 and q5 is estimated as E15 = (1/6)2+ (1/
( )i
1 7)3=0.0277+0.00291=0.03061. We assign node weight and edge
BF (Bi ) =  (3) weight to 0, i no connection originates rom that particular qubit line
j∈Bi tj
and such a situation can be seen or the vertex q4, where its all the
where the notations BF(Bi) and tj represent block actor or block Bi connecting edges are assigned 0 as it does not serve either as control or
and time at which gate gj appears in Bi respectively. The above mathe- target or any o the gates present in the circuit. By ollowing the same
matical expression (in Eqn. (3)) estimates the block actor (BF) or each procedure, we compute the associated values or rest o the nodes and
block Bi by considering the timestamp o each gate contained within edges where the complete graph is shown in Fig. 6(a).
each block and then add them up. The block actor value indicates the The graph obtained at the end o this phase will be used as an input to
priority o each block in the given circuit (or example block B1 holds a meta-heuristic algorithm in the next phase to nd a global qubit
higher priority than block B3). ordering or the circuit.

15
A. Bhattacharjee et al. Integration 78 (2021) 11–24

Table 1 contents o pheromone matrix τ are initially populated with 1 or all the
Qmap values or qubit mappings. connected vertices. Next, we compute the visibility matrix S (see Fig. 6
Map Rank (c)) rom Eqn. (7) by considering all node and edge weights rom graph
o Fig. 6(a).
q5q1q2q3q4 1
q2q1q3q5q4 2 Using the transition rule expressed in Eqn. (6), each ant k visits all
q3q1q2q5q4 3 the nodes in the graph at least once. As a result, each ant develops their
q1q2q3q5q4 4 path independently which leads to a linear qubit order. For m number o
q4q1q2q3q5 5 ants, m qubit sequence are derived and then recorded in π. Now each o
these path/qubit mapping solutions π(p) is evaluated using a heuristic
3.1.3. Phase III: solving the graph problem using ant colony algorithm cost unction (Qmap), which is dened as
The purpose behind implementing this phase is to generate an ∑
Qmap(π (p)) = Eab *Dab (p) (8)
appropriate qubit ordering or the entire circuit. Here, the previously g(a,b)∈C
generated graph is explored using a biologically inspired optimization
method called ant colony algorithm [35], which attempts to nd an where g(a, b) denotes gates acting on qubits a,b in circuit C and Dab(p)
optimal path in the graph based on the behavior o ants. To discover the represents the distance separating qubits a and b or a given path p in set
best path, pheromone trails are used by ants or exchanging such π. This distance metric is evaluated as
inormation.
Dab = |xa – xb |  1 (9)
This ant colony optimization (ACO) allows a specic number o ants
to move around graph and nds the possible shortest paths between the The expression as mentioned in Eqn. (9) is applicable only to 1D
graph nodes. During their traversal, the two metrics - pheromone and qubit mapping, but or higher dimensional qubit arrangements like 2D
heuristic visibility jointly decide the selection o the next node to be and 3D the ollowing expressions are employed.
visited, where pheromone governs edge selection and the visibility
Dab = |xa  xb | + |ya  yb |  1 (10)
metric helps to choose the next vertex based on the shortest distance
value. In this manner, ants construct a solution by visiting each vertex in
Dab = |xa  xb | + |ya  yb | + |za + zb |  1 (11)
the graph. Moreover, ants deposit pheromones on the edges it has visited
during its travel and to control the pheromone accumulation charac- Qmap is used or the ranking o such solutions where a low value or
teristic, some amount o pheromone gets evaporated rom all edges ater Qmap represents better solution quality. In case o a tie between any two
a certain time. This process o pheromone deposition and evaporation or more solutions, a random solution is picked rom this set.
updates pheromone strength on edges, which nally enorce the ants to
Example 6. In continuation with Example 5, we use the previously
converge and nd the best path in the graph.
computed data and nd ve qubit mapping solutions or ve ants. At the
In our case, ACO is implemented on the weighted complete graph
end o the rst iteration, we nd ve distinct orderings as
produced at the end o phase II. In our implementation, the number o
π={q1q2q3q5q4, q2q1q3q5q4, q3q1q2q5q4, q4q1q2q3q5, q5q1q2q3q4}. Cost
ants (m) is set to be equivalent to number o nodes in the graph and ant is
unction or each mapping is computed using Eqn. (8). For the rst
placed randomly on a vertex. Initially pheromone strength on these
sequence q1q2q3q5q4, edge weight values between any two qubits are
edges is set to 1. The probability o selecting node b rom node a or any
obtained rom the Fig. 6(a) and their corresponding distance values are
ant k at time t is perormed using the ollowing transition rule
evaluated using Eqn. (9). The computed values or the above mentioned
α*(Sab )β ordering are Dq1q2=|2-1|-1=0, Dq1q3=|3-1|-1=1, Dq1q5=|4-1|=3,
pkab (t) =  if b ∈ Not Visited Dq1q4=|5-1|=4 and Qmap (π(q1q2q3q5q4))= 1*0.5+2*0.0306=0.5612,
α*(Sak )β
k∈notvisited (6) where 0.3733, 0.0306 represent edge weights. Based on Qmap values,
these solutions are ranked as summarized in Table 1.
= 0 otherwise
Once all the ants construct their initial solutions, the pheromones
where τab , Sab represent pheromone strength and heuristic visibility o update process is carried out using the given mathematical ormulation.
edge ab. The probability o moving rom node a to node b comes into m
∑
eect only i it was not previously visited otherwise it moves to other τab (t + 1) = (1  ρ)τab (t) + Δab (t) (12)
k=1
non-visited nodes. The exponents α and β control the infuence o these
two parameters based on the behavior o ants. Basically these exponents where (1 ρ) represents pheromone decay parameter while ρ indicates
are needed or balancing the exploitation and exploration eatures o the evaporation coecient (0 < ρ < 1). The term Δab updates the phero-
search algorithm. I α is set to a large value then pheromones deposited mones based on the tness o the path which is evaluated using the cost
by ants in a specic path will be more desirable thereby making the ants unction (Qmap) or all the ants and is represented as
to use that path only which results into a premature convergence to the /
solution. I β is set to a higher value then the ants will nd the best path Δab = Wrank K Qmapk if (a, b) ∈ pathk
(13)
solution independently thereby causing delay in converging to the 0 otherwise
desired solution. So, a trade-o between these parameters is required Here, WKrank is the weighted rank computed or the path developed by
and here, we have considered similar values or both the exponents as α ant k which is expressed as
= β = 0.5.
The heuristic visibility parameter in Eqn.(6) is problem-specic and
K
Wrank K
= Totno  rankno +1 (14)
in our case, this parameter (Sab) has been dened as a combination o
both edge weight (Eab) and node weight (Na, Nb) values. where Totno represents the total number o solutions which is considered
as m since there are m ants while rankno designates the ranking o the Kth
Sab = Eab + Na + Nb (7) ant. Thereore, weighted rank (Wrank) depends on the rankings o the
The next node selection is based on the value o Sab indicating that corresponding solutions. More precisely, a higher ranked solution will
more preerence is given to vertex b which has higher Sab value with be assigned to a higher weighted value. The interpretation represented
vertex a. in Eqn. (13) suggests that more pheromones will be received by edges
belonging to best path solution that contains least Qmap value. In
Example 5. Consider the previously obtained graph in Fig. 6(a). The general, edges which are visited by many ants and which are residing

16
A. Bhattacharjee et al. Integration 78 (2021) 11–24

Fig. 7. (a): 1D representation o qubits. (b): 2D (2 × 3) representation o 4gt11_84 circuit. (c): 3D (2 × 2 × 2) representation o 4gt11_84 circuit.

Fig. 8. (a): Path computation in 2D grid or benchmark circuit 4gt11_84. (b): 3D (2 × 2 × 2) representation o 4gt11_84 circuit.

Fig. 9. (a): SWAP insertion in 2D grid or circuit 4gt11_84. (b): Resulting 2D representation ater exchanging qubits q3 and q4

within best path solution will be assigned more pheromones, so that they (t + 1)th iteration is less than the Bestpath value o tth iteration then
are more likely to be selected in uture iterations. Bestpath is updated to this new value. Ater reaching a specic number o
Pheromone update expression in Eqn. (12) changes the pheromone iterations (Icount), the algorithm is terminated and a resulting qubit
concentration initially by reducing its intensity on all edges by a con- conguration is realized. The maximum number o iteration in our
stant decay unit (1 ρ) and then each ant k deposits additional amount implementation was set to 100.
o pheromone (using Eqn. (13)) on the edges (here it is edge a and b) it In order to avoid the algorithm getting stuck at local optima, we reset
has travelled. Here, we have set the co-ecient ρ to 0.5. the pheromone matrix to its initial value 1 i the cost in Bestpath remains
Ater completing this entire round o iteration, ants are again placed unchanged or 25% o the total iteration number (Icount).
to their initial starting vertices and nding the best path solution is The mapped (Bestpath) qubit representations or benchmark circuit
executed iteratively. The best solution determined at the end o each (see Fig. 5(a)) realized at the end o ACO algorithm in 1D, 2D and 3D
iteration is recorded into a variable Bestpath but i the value o Bestpath. In congurations have been depicted in Fig. 7(a)-(c). For both 2D and 3D

17
A. Bhattacharjee et al. Integration 78 (2021) 11–24

Table 2
Comparison with 1D heuristic approaches on SWAP utilization.
Benchmark names No. O qubits Gate count Proposed method SWAP requirement Best 1D results Number o SWAP gates added in

in LACL2.0 in LACL2.1 in LACL2.2 [17] [6] [23] [25] [37]

4gt4-v0_80 6 44 30 30 30 30 34 34 33 32 –
4gt10-v1_81 5 36 21 21 19 19 20 30 22 22 16
4mod5-v1_23 5 24 10 10 9 9 9 16 13 15 15
4gt11_84 5 7 1 1 1 1 1 3 4 4 1
rd32-v0_67 4 8 2 2 2 2 2 2 – 4 –
3_17_13 3 14 4 4 4 4 4 6 5 6 3
4gt13-v1_93 5 17 6 6 6 6 6 11 9 9 6
4_49_17 4 32 12 12 12 12 12 20 15 15 16
hwb4_52 4 23 11 11 10 10 10 14 9 9 9
4gt5_75 5 22 12 11 10 10 12 17 13 13 –
alu-v4_36 5 32 17 16 16 16 18 23 20 16 17
aj-e11_165 5 60 33 32 33 32 36 39 35 33 26
4gt12-v1_89 6 53 31 31 31 31 35 35 33 33 –
4mod7-v0_95 5 40 23 23 21 21 21 28 – 22 22
mod5adder_128 6 87 51 50 48 48 51 85 53 53 –
rd53_135 7 78 64 62 63 62 66 76 69 66 68
ham7_104 7 87 66 65 66 65 68 84 67 63 70
mod8-10_177 6 109 72 72 72 72 72 77 71 71 –
hwb6_58 6 146 102 102 102 102 118 136 108 98 145
rd73_140 10 76 33 32 33 32 56 62 44 44 75
QFT5 5 10 7 7 7 7 6 12 – – –
QFT6 6 15 11 11 11 11 12 22 – – –
QFT7 7 21 18 18 18 18 26 39 – 18 –

Amongst all the available paths (Npaths) existing between any two
Table 3 non-adjacent qubits qa and qb, a specic path (p) is chosen using a path
Comparison with meta-heuristic (HS) approach in 1D. cost metric (pcost) as given in Eqn.(15).
Benchmark No. O Gate Best results rom our SWAP used in ∑ gq
names qubits count approach [37] pcos t = (15)
q∈p
G
3_17_13 3 14 4 3
4gt11_84 5 7 1 1
hwb4_52 4 23 10 9
where G represents total gate count and term gq designates number o
4gt10-v1_81 5 36 19 16 gates interacting with qubit q. This metric computes a cumulative eect
alu-v4_36 5 32 16 17 (interactions) o the qubits existing within path p in the remaining cir-
rd53_135 7 78 62 68 cuit. Ater determining the cost or all the possible paths, the path with
hwb5_55 5 109 39 60
least cost is selected.
hwb6_58 6 146 102 145
rd73_140 10 76 32 75 For any given path p, SWAP gates can be embedded in various
ham7_104 7 87 65 70 possible manners beore a non NN-compliant quantum gate. The number
rd84_142 15 112 54 142 o such SWAP insertion options (ns) or any path p is related to the
4mod7-v0_95 5 40 21 22 number o components (Ncomp) occurring between the two end points o
4gt12-v1_89 6 53 31 26
4mod5-v1_23 5 24 9 15
p. More precisely, number o qubits appearing between the two non-
4_49_17 4 32 12 16 adjacent qubits on path p corresponds to the possible SWAP options as
4gt13-v1_93 5 17 6 4 expressed below
cnt3-5_108 16 125 87 170
ns = Ncomp + 1 (16)

representations, qubit are mapped in 2 × 3, 2 × 2 × 2 structures (see

Fig. 7(b)-7(c)) while garbage values (g) are used or padding the vacant Example 7. The global qubit ordering or benchmark 4gt11_84 is
positions in the congurations (see Fig. 8). already computed in Example 6. Now, i SWAPs are inserted between the
non-adjacent qubits then it will turn into NN architectures, but to reduce
SWAP requirement, we need to apply local reordering policy. Now,
3.2. Local reordering consider the 2D global reordered solution in Fig. 7(b) over which we
execute our local reordering technique. Initially we scan the circuit to
The use o SWAP gate increases overall cost o the resulting NN nd those gates that have distance values more than 0. While searching,
representation as it increases the number o operations in the circuit we nd that the third gate with qubit q2 and q3 rom the let o the circuit
which in turn also rise the computational time o the design. Thereore, has a distance value o 1 as Dq2q3=|2-1|+|3-2|-1=1+1-1=2-1=1 and
reduction o SWAP count in NN circuits is important in order to control Dq2q3=|1-0|+|0-0|+|1-0|-1=1+0+1-1=2-1=1. So, we have two options
design overheads. In the global reordering scheme, we re-positioned that can make the qubits adjacent; either we can ollow the path p1: q3,
qubits to minimize global SWAP demand, and next we introduce local q4, q2 or can take route p2: q3, q1, q2. Again, or each o these paths - p1,
ordering o qubits to minimize SWAP gate count. p2 there exists two possible ways o inserting SWAPs as only a single
By examining the circuit or each gates whose qubits (control/target) qubit exist between the two points q2 and q3. Furthermore, the cost o
are not adjacent to one another, i the distance between the interacting each path is estimated to be 0 and 0.142 or p1 and p2 respectively. As
qubits is ound to be greater than zero, then all possible paths existing path p1 has least path cost, so, it is chosen or SWAP insertion.
within the SWAP region are examined. The number o such paths can be For each o these ns ways, we need to keep track o the impact
estimated as suggested in Re. [32] irrespective o any specic archi- imposed on the remaining gates in the circuit. To estimate this impact,
tectural layout o quantum circuits.

18
A. Bhattacharjee et al. Integration 78 (2021) 11–24

Table 4
Comparison o our 2D results over reported heuristic 2D works.
Benchmark No. O Gate Proposed Method SWAP requirement Best Number o SWAP gates added in
names qubits count Results
Grid in in in in in in [31] [28] [26] [30] [24]
Size LACL1.0 LACL1.1 LACL1.2 LACL2.0 LACL2.1 LACL2.2
iterative joint

4gt4-v0_80 6 44 2×3 13 13 13 12 12 12 12 18 15 17 16 – –
4gt10-v1_81 5 36 3×2 15 15 15 14 12 12 12 13 15 16 14 22 15
4mod5-v1_23 5 24 2×3 8 8 10 8 8 10 8 10 7 11 8 – –
4gt11_84 5 7 2×3 1 1 1 1 1 1 1 2 2 2 2 – -
3_17_13 3 14 2×2 4 4 4 4 4 4 4 4 3 6 5 8 5
decod24-v3_46 4 9 3×2 2 2 2 2 2 2 2 2 – 3 2 – –
4gt13-v1_93 5 17 3×3 3 3 3 3 3 3 3 3 – 2 – – –
4_49_17 4 32 2×2 9 9 9 9 9 9 9 9 – 13 10 – –
hwb4_52 4 23 2×2 8 8 8 8 8 8 8 7 9 9 7 – –
4gt5_75 5 22 3×3 7 7 7 7 7 7 7 7 10 8 9 – –
alu-v4_36 5 32 2×3 10 10 11 8 8 10 8 9 11 10 11 – –
aj-e11_165 5 60 3×2 22 28 22 22 28 22 22 24 22 24 18 37 16
4gt12-v1_89 6 53 2×3 16 16 28 16 16 18 16 22 18 19 20 – –
4mod7-v0_95 5 40 3×3 10 12 10 10 11 10 10 14 14 13 10 – –
mod5adder_128 6 87 3×2 36 35 37 34 35 30 30 35 36 41 28 45 33
rd53_135 7 78 5×2 43 37 31 34 37 31 31 40 40 39 29 47 30
ham7_104 7 87 2×4 34 36 30 30 36 40 30 34 45 48 38 53 37
mod8-10_177 6 109 3×3 50 44 40 40 44 40 40 41 43 45 39 – –
hwb5_55 5 109 3×2 51 51 39 39 43 44 39 44 49 45 38 64 37
hwb6_58 6 146 2×3 69 59 64 64 59 64 59 62 76 79 63 85 59
rd73_140 10 76 4×3 30 28 32 28 24 32 24 31 43 37 28 – –
QFT5 5 10 3×2 4 4 3 3 4 3 3 3 5 5 5 – –
QFT6 6 15 2×3 6 6 5 5 6 5 5 8 7 6 5 – –
QFT7 7 21 4×2 10 10 9 9 10 9 9 13 14 18 14 22 13
QFT8 8 28 2×4 16 15 14 14 13 14 13 16 23 18 18 25 17
QFT9 9 36 3×3 18 16 18 18 16 18 16 25 36 34 24 27 22
QFT10 10 45 5×3 31 30 25 25 30 24 24 43 51 53 33 43 37
sys6-v0_144 10 62 4×4 24 24 23 23 26 24 23 32 – 31 30 – –
rd84_142 15 112 4×4 58 56 42 42 59 43 42 64 62 54 48 – –
cnt3-5_108 16 125 4×4 52 63 48 48 59 55 48 67 84 69 54 – –
ham15_108 15 458 4×4 265 237 197 197 250 220 197 249 280 328 – 355 223
cycle10_2_110 12 1212 5×3 610 591 537 537 528 568 528 598 588 839 – 824 483

the cost unction (Qmap) is used and the one that leads to a least Qmap limited number o gates. Restricting the cost evaluation over a specic
value will be selected. During this computation, the impact on the number o gates [24] can be considered a reasonable policy as gates
remaining gates in the circuit needs to be taken into account and to make appearing later in the circuit can provide a negative eect on decision
this impact ecient, we have implemented a window based look-ahead making process (how to move control/target qubits) as the interaction
approach, where dierent look-ahead criteria are explored. pattern o qubits may change rom one circuit segment to the other.
Based on the underlying look-ahead criteria, we categorized the CLASS 1.1: Similar to CLASS 1, here also, we start rom path
applied searching technique into the ollowing classes. calculation ollowed by path selection and then computation o possible
CLASS 1.0: The most common way in look-ahead policy is observing SWAP insertion (ns) paths. But here unlike previous class, the cost o
the impact on all the remaining gates in the circuit. In this class, block implementing these ns options has been evaluated by considering the
partitioned representation o the input circuit is considered. Let’s eect on the remaining gates within the same block in which gate g is
consider a gate g occurring within block Bi whose qubits are not placed residing as well as the gates occurring within the next immediate block
at adjacent positions. To turn the qubits adjacent, path selection is done (i any). This class is represented as LACL1.1. See, the next example to
using path cost metric and then an appropriate solution is obtained understand the operation o this class.
depending on the impact o (Qmap) on rest o the gates in block Bi and
Example 9. For making gate g3 NN-compliant (in Fig. 7(b)), Qmap
all the look ahead gates in the remaining blocks o the given partitioned
value is estimated over the next immediate block B2 or selecting a
circuit.
suitable option (see Fig. 9(a)) to insert the SWAPs. As gate g3 is the last
The same procedure is ollowed or all the non-adjacent gates
gate occurring within block B1, so cost evaluation is done only on block
occurring within the three blocks and this orm o look-ahead strategy is
B2. Next, SWAP is applied to move qubit q3 towards q2 as movement o
represented as LACL1.0.
qubit in this direction leads to a lower Qmap value than moving q2 to-
The ollowing example demonstrates this look-ahead policy.
wards q3.
Example 8. Reerencing example8, where a suitable path (p1) or CLASS 1.2: In this class, decision regarding the best qubit movement
making the third gate NN-compliant is determined, there are two option is determined by limiting the impact evaluation. For any non-
possible ways in which SWAP gates can be inserted and are represented adjacent gate g occurring within block Bi, the Qmap estimation is con-
using arrows indicating movement o qubit q3 towards q2 and vice versa ducted only over the remaining gates o Bi. I gate g happens to be the
(see Fig. 9(a)). Now, each o these options is evaluated by estimating last gate in Bi then cost is evaluated considering only the rst gate
Qmap value or the remaining gates (B2+B3) in the partitioned circuit as occurring within the next immediate block Bi+1. This orm o look-ahead
gate g3 is the last gate occurring within the block B1. Based on the least scheme is designated as LACL1.2.
Qmap value, SWAP gates are inserted exchanging the positions o qubits In the previous classes, a specic path is chosen among all the
q3 and q4 and the resulting 2D representation is shown in Fig. 9(b). available paths using a heuristic path selection metric which may not
Instead o evaluating the impact on all the remaining gates in the result to an ecient NN representation as remaining paths are discarded
block partitioned circuit, look-ahead process can also be applied to a rom urther evaluations. For this purpose, local reordering process is

19
A. Bhattacharjee et al. Integration 78 (2021) 11–24

Table 5 Now, let consider the earlier design in Fig. 7(b) to understand the
Comparison with meta-heuristic approach in 2D. operation o this class.
Benchmark No. O Gate Grid Best results rom SWAP Example 10. We already have seen that there exist two paths (p1, p2)
names qubits count Size our approach used in
[29]
or the third gate g3 and or each such path there exists two possible
ways to insert SWAP gates. Both o these options or path p1 and p2 are
3_17_13 3 14 2 4 4
evaluated separately by considering the eect on all the remaining gates
×
2
4gt11_84 5 7 2 × 1 1 over block B2 and B3. For path p1, Qmap values are 1.065 or moving q2
3 towards q3 via. q4 and 0 or moving q3 towards q2 via. q4. Similarly, or
QFT5 5 10 3 × 3 3 path p2 the values are 0.0306 or moving q2 towards q3 via. q1 and,
2
1.0956 or moving q3 towards q2 via. q1. Option o moving q3 towards q2
mod8-10_177 6 109 3 × 40 39
3
via. q4 is chosen due to its least impact on the remaining circuit.
QFT6 6 15 2 × 5 5 CLASS 2.1: This class is based on the combinations o CLASS 2 and
3 CLASS 1.1. Like CLASS 2, here all possible SWAP insertion options or all
QFT7 7 21 4 × 9 10 gates are evaluated and Qmap is calculated using the approach
2
described in CLASS 1.1. The look-ahead procedure dened in this class is
mod5adder_128 6 87 3 × 30 28
2 expressed as LACL2.1.
4gt4-v0_80 6 44 2 × 12 13 Similarly, the next class (CLASS 2.2) is ormed using the underlying
3 look-ahead policies o CLASS 2 and CLASS 1.2.
QFT8 8 28 2 × 13 16 CLASS 2.2: Consideration o all the paths between two non-adjacent
4
QFT9 9 36 3 × 16 19
qubits is ollowed as per the procedure mentioned in CLASS 2 and the
3 cost evaluation is done using the rules o CLASS 1.2.
QFT10 10 45 5 × 24 31
3 4. Experimental results
4gt10-v1_81 5 36 3 × 12 11
2
alu-v4_36 5 32 2 × 8 8 We have implemented the synthesis scheme using C++ on Intel core
3 i5 processor with 3.30 GHZ clock and 4 GB RAM. Evaluation o our
rd53_135 7 78 5 × 31 28 combined (global and local) reordering scheme is conducted by carrying
2 out experiments on various benchmark [36] and the computed results
hwb5_55 5 109 3 × 39 38
2
are summarized in twelve tables.
hwb6_58 6 146 2 × 59 63 In Table 2, we summarize 1D results and compare it to heuristic
3 works done in ([6,17,23,25,37]). It is apparent rom the table that the
rd84_142 15 112 4 × 42 42 proposed approach registers an average improvement o 13% over [6],
4
36% over [17], 16% over [23], 16% over [25] and 15% over [37].
ham15_108 15 458 4 × 197 199
4 Comparison with the meta-heuristic work o [37] is given in Table 3,
4gt12-v1_89 6 53 2 × 16 16 where also we have made 10% average improvement in SWAP count.
3 The 2D results are summarized in Table 4 and we have compared our
dierent look-ahead classes with [24,26,28,30,31]. For the case o 2D
results, we also have registered 25% average improvement over [24],
revised in which all the possible paths (Npaths) existing between two non-
26% over [26], 22% over [28], 15% over [30] and 20% over [31].
adjacent qubits are considered rather than working on a certain path.
As our NN algorithm belongs under meta-heuristic category, we have
Assessing all the possible paths Npaths is the principle behind the
compared our 2D results with a meta-heuristic work o [29], where also
ollowing look-ahead policies as discussed next.
we have registered 4% average improvement in Table 5. To testiy the
CLASS 2.0: This class is similar to CLASS 1 except that all possible
optimality o our results, we have compared our 2D results with the
paths determined or any non NN-compliant quantum gate g residing
results o a 2D exact approach [27] and also have compared our 1D work
within block Bi are considered. For each such path, all possible options
with another 1D based exact technique [22] in Table 6.
(ns) are evaluated based on the Qmap value computed over rest o the
In comparing our 3D results with [31], we keep a steady improve-
gates in Bi as well as the gates occurring in the remaining blocks in the
ment o 16% on an average in Table 7. Results rom our 2D NN archi-
given circuit. We examine all the ns options with SWAP insertion to nd
tecture on higher qubit benchmarks are presented in Table 8, where we
the least cost path which nally leads to the desired NN solution.
only could produce comparison with 2D work [30] as other 2D works do
Implementing look-ahead process in such a manner is denoted as
not have results over the same circuits used in Table 8. The 3D results
LACL2.0.
over the same higher qubit circuits (as used in Table 8) are presented in

Table 6
Comparison with optimal works or 1D and 2D architecture.
Benchmark In 2D architecture In 1D architecture

Exact approach [27] This work Exact approach [22] This work

Grid SWAP Run time Grid Best SWAP Run time SWAP Run time Best SWAP Run time
size value (sec.) size value (sec.) value (sec.) value (sec.)

3_17_13 2×2 4 17.6 2×2 4 0.01 2 0.1 4 0.01

4gt11_84 2×3 1 1644.5 2×3 1 0.03 1 8.9 1 0.02
decod24- 2×2 2 0.5 3×2 2 0.02 3 0.4 3 0.02
v3_46
rd32-v0_67 2×2 2 0.2 2×3 2 0.02 2 0.3 2 0.01
hwb4_52 2×2 7 42752.9 2×2 8 0.02 – – – –
QFT5 – – – – – – 6 2463.2 7 0.03

20
A. Bhattacharjee et al. Integration 78 (2021) 11–24

Table 7
Comparisons o our 3D results with existing 3D works.
Benchmark No. O Gate Grid Proposed Method SWAP overhead Best SWAP Count % Imprv.
names qubits count Size Result in [31] Over [31]
In In In In In In
LACL1.0 LACL1.1 LACL1.2 LACL2.0 LACL2.1 LACL2.2

4gt4-v0_80 6 44 2×2 13 13 12 12 12 12 12 16 25
×2
4gt10-v1_81 5 36 2×2 14 15 13 13 15 12 12 12 0.0
×2
4mod5-v1_23 5 24 2×2 10 10 10 8 8 8 8 8 0.0
×2
4gt11_84 5 7 2×2 1 1 1 1 1 1 1 1 0.0
×2
rd32-v0_67 4 8 2×2 2 2 2 2 2 2 2 3 33.33
×2
3_17_13 3 14 2×2 4 4 4 4 4 4 4 4 0.0
×2
decod24-v3_46 4 9 2×2 2 2 2 2 2 2 2 2 0.0
×2
4gt13-v1_93 5 17 2×2 3 3 3 3 3 3 3 3 0.0
×2
4_49_17 4 32 2×2 9 9 9 9 9 9 9 9 0.0
×2
hwb4_52 4 23 2×2 8 8 8 8 8 8 8 7 14.28
×2
4gt5_75 5 22 2×2 7 7 7 7 7 7 7 8 12.5
×2
alu-v4_36 5 32 2×2 10 11 9 9 11 9 9 8 12.5
×2
4gt12-v1_89 6 53 2×2 24 21 21 20 19 20 19 22 13.63
×2
4mod7-v0_95 5 40 2×2 10 11 10 10 11 10 10 16 37.5
×2
mod5adder_128 6 87 2×2 39 34 35 35 34 30 30 37 18.91
×2
rd53_135 7 78 2×2 35 34 32 32 32 28 28 34 17.64
×2
ham7_104 7 87 2×2 44 32 36 36 32 36 32 33 3.03
×2
mod8-10_177 6 109 2×2 45 43 40 40 41 40 40 42 4.76
×2
hwb5_55 5 109 2×2 43 42 38 38 52 38 38 43 11.62
×2
hwb6_58 6 146 2×2 66 62 58 57 62 57 57 65 12.30
×2
rd73_140 10 76 3×2 25 23 31 23 23 24 23 30 23.33
×2
QFT5 5 10 2×2 4 4 3 3 4 3 3 3 0.0
×2
QFT6 6 15 2×2 6 5 5 5 5 5 5 6 16.66
×2
QFT7 7 21 2×2 9 9 8 8 9 8 8 10 20
×2
QFT8 8 28 2×2 12 9 11 11 9 11 9 9 0.0
×3
QFT9 9 36 2×2 21 20 14 14 17 14 14 24 41.66
×3
QFT10 10 45 2×2 32 30 21 21 25 20 20 33 39.39
×3
sys6-v0_144 10 62 2×3 22 26 22 22 22 22 22 28 21.42
×2
rd84_142 15 112 3×2 50 60 48 47 54 47 47 49 4.08
×3
cnt3-5_108 16 125 3×2 56 52 55 50 50 50 50 57 12.28
×3
ham15_108 15 458 3×3 213 222 183 183 209 195 183 266 31.20
×2
cycle10_2_110 12 1212 2×2 498 470 472 472 471 472 470 557 15.61
×3
Shor3 10 2076 3×2 1331 1444 1238 1238 1275 1328 1238 1218 1.64
×2
Average improvement 16.13

21
A. Bhattacharjee et al. Integration 78 (2021) 11–24

Table 8
Comparison o our 2D results on higher qubit circuits.
Benchmark No. O Gate Grid Number o SWAPs used in our 2D design Best results rom SWAP used in %
names qubits count Size our 2D classes Re. [30] Imprv.
in in in in in in
Over [30]
LACL1.0 LACL1.1 LACL1.2 LACL2.0 LACL2.1 LACL2.2

rev_17 17 136 5×4 151 158 155 125 125 129 125 214 41.58
rev_18 18 153 5×4 204 195 189 154 154 154 154 221 30.31
rev_19 19 171 6×4 194 218 211 159 159 169 159 256 37.89
ac_21_1 21 130 4×6 51 50 54 33 33 50 33 116 71.55
ac_21_2 21 67 6×4 51 43 44 39 39 40 39 53 26.41
ac_21_3 22 42 4×6 37 37 38 28 28 31 28 51 45.09
hm_20 20 73 5×4 42 37 36 29 29 29 29 69 57.97
hm_21 21 79 6×4 52 63 57 43 43 50 43 102 57.84
hm_22 22 85 6×4 58 56 59 51 51 49 49 94 47.87
add8_172 25 96 7×4 44 38 39 35 35 34 34 – –
add16_174 49 192 7×7 123 122 122 107 107 108 107 – –
add32_183 97 384 10 × 299 288 291 257 257 279 257 – –
10
rdom24 24 47 6×4 39 34 34 28 27 27 27 – –
rdom27 27 53 5×6 41 36 35 31 31 31 31 – –
rdom30 30 59 6×5 59 53 54 43 43 43 43 – –
rdom33 33 65 6×6 70 68 68 53 53 58 53 – –
rdom29 29 74 6×5 53 50 49 46 46 46 46 – –

Table 9
3D NN results rom higher qubit benchmarks.
Benchmark names No. O qubits Gate count Grid Size Number o SWAPs used in our 3D design

in LACL1.0 in LACL1.1 in LACL1.2 in LACL2.0 in LACL2.1 in LACL2.2

rev_17 17 136 2 ×3 × 3 127 133 141 97 97 93

rev_18 18 153 2 ×3 × 3 142 146 160 107 107 104
rev_19 19 171 3 ×3 × 3 173 192 186 134 134 134
ac_21_1 21 130 3 ×3 × 3 42 39 50 25 25 28
ac_21_2 21 67 3 ×3 × 3 39 40 34 27 27 27
ac_21_3 22 42 3 ×3 × 3 35 30 30 28 28 30
hm_20 20 73 3 ×3 × 3 46 29 47 28 28 29
hm_21 21 79 3 ×3 × 3 49 45 49 36 36 37
hm_22 22 85 3 ×3 × 3 49 47 46 37 37 33
add8_172 25 96 3 ×3 × 3 42 38 36 35 35 36
add16_174 49 192 5 ×4 × 3 88 87 81 80 80 81
add32_183 97 384 6 ×5 × 4 249 244 243 222 222 224
rdom24 24 47 3 ×3 × 3 35 31 28 22 22 22
rdom27 27 53 3 ×3 × 3 38 39 32 28 28 28
rdom30 30 59 4 ×3 × 3 45 42 37 37 38 37
rdom33 33 65 4 ×3 × 3 58 61 38 38 38 38
rdom29 29 74 4 ×3 × 3 50 50 56 45 42 42

Table 9, where we could not produce the comparison as any o the 3D o the gate in a block yielding improved results.
works has not experimented with the same set o benchmarks as used in Although we have seen quite good improvements in SWAP require-
Table 9. ment or most o the benchmarks rom our approach, or a ew unction
In all the result tables, we have explored the results rom our the results are not that eective and it is due to heuristic nature o global
dierent look-ahead approaches like LACL1.0, LACL1.1, LACL1.2, LACL2.0, reordering phase. So, this particular area can be investigated urther to
LACL2.1, LACL2.2 and the best result rom these approaches are used to get more improved solutions.
compare the existing works’ results. Although this work was ocused on NN design requirement, other
In our experimentation, we have seen that the local reordering constraints or dierent quantum architectures also exist, or example,
scheme based on LACL2.0, LACL2.1, LACL2.2 is computationally more IBMQX [5] has CNOT constraints. Depending on circuit size, the IBM
expensive than the schemes LACL1.0, LACL1.1, LACL1.2 as it consider architecture changes its grid congurations and several variations like
evaluation o all possible paths occurring between any two non-adjacent IBM QX3 [5], QX4 [38] and Q20 [39] are proposed. Though the un-
interacting qubits to reach towards best possible solution. The run time derlying design constraints remain dierent or NN and IBM QX archi-
comparison between these two Look-ahead classes is also produced in tectures, one common eature is that both designs implements SWAPs to
Table 10, where it is seen that LACL1 is computationally aster than overcome their design restrictions.
LACL2 .
Another point to be mentioned that the NN transormation process 5. Conclusion
or higher topological layouts (2D, 3D) involves additional time steps
than the corresponding 1D solutions as additional mapping scheme is In this work, we have shown a hybrid synthesis approach or trans-
executed to map the 1D solutions to 2D and 3D based solutions. ormation o quantum circuits to NN-compliant architectures. In the
Unlike other look-ahead policies (like [23,25,31]), our obtained so- hybrid approach, rst we have executed a probabilistic based global
lutions are better and it is due to the underlying circuit partition tech- qubit ordering scheme and then have employed a look-ahead based local
nique where impact evaluation is conducted depending on the position reordering technique to minimize the SWAP requirement. We have

22
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