MODULE 2: INPUT/OUTPUT

ORGANIZATION
Dr Shreema Shetty
Dept CSE
SCEM

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ACCESSING I/O-DEVICES
• A single bus-structure can be used for connecting I/O-devices to a computer
(Figure1).
• Each I/O device is assigned a unique set of address.
• Bus consists of 3 sets of lines to carry address, data & control signals.
• When processor places an address on address-lines, the intended-device
responds to the command.
• The processor requests either a read or write-operation.
• The requested-data are transferred over the data-lines.

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3
• There are 2 ways to deal with I/O-devices:
1) Memory-mapped I/O & 2) I/O-mapped I/O.
1) Memory-Mapped I/O
Memory and I/O-devices share a common address-space.
Any data-transfer instruction (like Move, Load) can be used to exchange
information.
For example, Move DATAIN, R0; This instruction sends the contents of location
DATAIN to register R0. Here, DATAIN address of the input-buffer of the keyboard.

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2) I/O-Mapped I/O

Memory and I/0 address-spaces are different.

A special instructions named IN and OUT are used for data-transfer.

Advantage of separate I/O space: I/O-devices deal with fewer address-lines.

Dr Shreema Shetty

Dept CSE

SCEM
5
I/O Interface for an Input Device

1) Address Decoder: enables the device to recognize its address when this
address appears on the address-lines (Figure 2).

2) Status Register: contains information relevant to operation of I/O-device.

3) Data Register: holds data being transferred to or from processor.

There are 2types:i) DATAIN Input-buffer associated with keyboard. ii) DATAOUT
Output data buffer of a display/printer.

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MECHANISMS USED FOR INTERFACING I/O-DEVICES

1) Program Controlled I/O

• Processor repeatedly checks status-flag to achieve required synchronization b/w

processor & I/O device. (We say that the processor polls the device).

• Main drawback: The processor wastes time in checking status of device before
actual data-transfer takes place.

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2) Interrupt I/O

• I/O-device initiates the action instead of the processor.

• I/O-device sends an INTR signal over bus whenever it is ready for a

data-transfer operation.

• Like this, required synchronization is done between processor & I/O device.

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3) Direct Memory Access (DMA)

• Device-interface transfer data directly to/from the memory w/o continuous

involvement by the processor.

• DMA is a technique used for high speed I/O-device.

Dr Shreema Shetty

Dept CSE

11
SCEM
INTERRUPTS
• There are many situations where other tasks can be performed while waiting for
an I/O device to become ready.

• A hardware signal called an Interrupt will alert the processor when an I/O device
becomes ready.

• Interrupt-signal is sent on the interrupt-request line.

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• The processor can be performing its own task without the need to continuously
check the I/O-device.

• The routine executed in response to an interrupt-request is called ISR.

• The processor must inform the device that its request has been recognized by
sending INTA signal.

(INTR Interrupt Request, INTA Interrupt Acknowledge, ISR Interrupt Service

Routine) • For example, consider COMPUTE and PRINT routines (Figure 3.6).

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INTERRUPTS
• There are many situations where other tasks can be performed while waiting for
an I/O device to become ready.
• A hardware signal called an Interrupt will alert the processor when an I/O device
becomes ready.
• Interrupt-signal is sent on the interrupt-request line.
• The processor can be performing its own task without the need to continuously
check the I/O-device.
• The routine executed in response to an interrupt-request is called ISR.

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The processor first completes the execution of instruction i.
• Then, processor loads the PC with the address of the first instruction of the ISR.
• After the execution of ISR, the processor has to come back to instruction i+1.
• Therefore, when an interrupt occurs, the current content of PC is put in
temporary storage location.
• A return at the end of ISR reloads the PC from that temporary storage location.
• This causes the execution to resume at instruction i+1.

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• When processor is handling interrupts, it must inform device that its request has
been recognized.
• This may be accomplished by INTA signal.
• The task of saving and restoring the information can be done automatically by
the processor.
• The processor saves only the contents of PC & Status register.
• Saving registers also increases the Interrupt Latency.

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• Interrupt Latency is a delay between

→ time an interrupt-request is received and

→ start of the execution of the ISR.

• Generally, the long interrupt latency in unacceptable.

Dr Shreema Shetty

Dept CSE

SCEM 18
19
INTERRUPT HARDWARE
• Most computers have several I/O devices that can request an interrupt.
• A single interrupt-request (IR) line may be used to serve n devices (Figure 4.6).
• All devices are connected to IR line via switches to ground.
• To request an interrupt, a device closes its associated switch.
• Thus, if all IR signals are inactive, the voltage on the IR line will be equal to Vdd.
• When a device requests an interrupt, the voltage on the line drops to 0.
• This causes the INTR received by the processor to go to 1.

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• The value of INTR is the logical OR of the requests from individual devices.
INTR=INTR1+ INTR2+ . . . . . +INTRn
• A special gates known as open-collector or open-drain are used to drive the INTR line.
• The Output of the open collector control is equal to a switch to the ground that is
→ open when gates input is in ”0‟ state and
→ closed when the gates input is in “1‟ state.
• Resistor R is called a Pull-up Resistor because it pulls the line voltage up to the high-voltage
state when the switches are open.

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ENABLING & DISABLING INTERRUPTS
• All computers fundamentally should be able to enable and disable interruptions as desired.

• The problem of infinite loop occurs due to successive interruptions of active INTR signals.

• There are 3 mechanisms to solve problem of infinite loop:

1) Processor should ignore the interrupts until execution of first instruction of the ISR.

2) Processor should automatically disable interrupts before starting the execution of the ISR.

3) Processor has a special INTR line for which the interrupt-handling circuit.

Interrupt-circuit responds only to leading edge of signal. Such line is called edge-triggered.

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• Sequence of events involved in handling an interrupt-request:
1) The device raises an interrupt-request.
2) The processor interrupts the program currently being executed.
3) Interrupts are disabled by changing the control bits in the processor status register (PS).
4) The device is informed that its request has been recognized.
In response, the device deactivates the interrupt-request signal.
5) The action requested by the interrupt is performed by the interrupt-service routine.
6) Interrupts are enabled and execution of the interrupted program is resumed.

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HANDLING MULTIPLE DEVICES
• While handling multiple devices, the issues concerned are:

1) How can the processor recognize the device requesting an interrupt?

2) How can the processor obtain the starting address of the appropriate ISR?

3) Should a device be allowed to interrupt the processor while another interrupt is

being serviced?

4) How should 2 or more simultaneous interrupt-requests be handled?

Dr Shreema Shetty

Dept CSE
25
SCEM
POLLING
• Information needed to determine whether device is requesting interrupt is available in
status-register
• Following condition-codes are used:
DIRQ Interrupt-request for display.
KIRQ Interrupt-request for keyboard.
KEN keyboard enable.
DEN Display Enable.
SIN, SOUT status flags.

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• For an input device, SIN status flag in used.

SIN = 1 when a character is entered at the keyboard.

SIN = 0 when the character is read by processor.

IRQ=1 when a device raises an interrupt-requests (Figure 4.3).

• Simplest way to identify interrupting-device is to have ISR poll all devices connected to bus.

• The first device encountered with its IRQ bit set is serviced.

• After servicing first device, next requests may be serviced.

Dr Shreema Shetty

Dept CSE
27
SCEM
• Advantage: Simple & easy to implement.

● Disadvantage: More time spent polling IRQ bits of all devices.

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VECTORED INTERRUPTS

• A device requesting an interrupt identifies itself by sending a special-code to processor over

bus.
• Then, the processor starts executing the ISR.
• The special-code indicates starting-address of ISR.
• The special-code length ranges from 4 to 8 bits.
• The location pointed to by the interrupting-device is used to store the staring address to ISR.
• The staring address to ISR is called the interrupt vector.

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• Processor
→ loads interrupt-vector into PC &
→ executes appropriate ISR.
• When processor is ready to receive interrupt-vector code, it activates INTA line.
• Then, I/O-device responds by sending its interrupt-vector code & turning off the
INTR signal.
• The interrupt vector also includes a new value for the Processor Status Register.

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CONTROLLING DEVICE REQUESTS
• Following condition-codes are used:

KEN Keyboard Interrupt Enable.

DEN Display Interrupt Enable.

KIRQ/DIRQ Keyboard/Display unit requesting an interrupt.

• There are 2 independent methods for controlling interrupt-requests. (IE

interrupt-enable).

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1) At Device-end

IE bit in a control-register determines whether device is allowed to generate an

interrupt-request.

2) At Processor-end, interrupt-request is determined by

→ IE bit in the PS register or

→ Priority structure

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INTERRUPT NESTING
• A multiple-priority scheme is implemented by using separate INTR & INTA lines for each
device
• Each INTR line is assigned a different priority-level (Figure 4.7).
• Priority-level of processor is the priority of program that is currently being executed.
• Processor accepts interrupts only from devices that have higher-priority than its own.
• At the time of execution of ISR for some device, priority of processor is raised to that of
the device.
• Thus, interrupts from devices at the same level of priority or lower are disabled.

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Privileged Instruction

• Processor's priority is encoded in a few bits of PS word. (PS Processor-Status).

• Encoded-bits can be changed by Privileged Instructions that write into PS.

• Privileged-instructions can be executed only while processor is running in

Supervisor Mode.

• Processor is in supervisor-mode only when executing operating-system routines.

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Privileged Exception

• User program cannot

→ accidently or intentionally change the priority of the processor &

→ disrupt the system-operation.

• An attempt to execute a privileged-instruction while in user-mode leads to a

special type of interrupt called Privileged Exception.

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● Each of the interrupt request lines are assigned a different priority level.
● Interrupt request received over these lines are sent to a priority arbitration
circuit in the processor.
● A request is accepted only if it has higher priority level than that currently
assigned to the processor.

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SIMULTANEOUS REQUESTS
• The processor must have some mechanisms to decide which request to service when
simultaneous requests arrive.
• INTR line is common to all devices (Figure 4.8a).
• INTA line is connected in a daisy-chain fashion.
• INTA signal propagates serially through devices.
• When several devices raise an interrupt-request, INTR line is activated.
Polling the status register of I/O devices is the simplest mechanism to determine by the
order in which the devices are polled.

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• Processor responds by setting INTA line to 1. This signal is received by device 1.
• Device-1 passes signal on to device 2 only if it does not require any service.
• If device-1 has a pending-request for interrupt, the device-1
→ blocks INTA signal &
→ proceeds to put its identifying-code on data-lines.
• Device that is electrically closest to processor has highest priority
• Advantage: It requires fewer wires than the individual connections.

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Arrangement of Priority Groups
• Here, the devices are organized in groups & each group is connected at a
different priority level.

• Within a group, devices are connected in a daisy chain. (Figure 4.8b).

Dr Shreema Shetty

Dept CSE
42
SCEM
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 EXCEPTIONS
• An interrupt is an event that causes → execution of one program to be
suspended & → execution of another program to begin.
• Exception refers to any event that causes an interruption. For ex: I/O interrupts.
1. Recovery from Errors
• These are techniques to ensure that all hardware components are operating
properly.
• For ex: Many computers include an ECC in memory which allows detection of
errors in stored-data.
(ECC Error Checking Code, ESR Exception Service Routine).

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• If an error occurs, control-hardware → detects the errors & → informs processor
by raising an interrupt.

• When exception processing is initiated (as a result of errors), processor. →

suspends program being executed & → starts an ESR. This routine takes
appropriate action to recover from the error.

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2. Debugging

• Debugger → is used to find errors in a program and

→ uses exceptions to provide 2 important facilities: i) Trace & ii) Breakpoints

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i) Trace
• When a processor is operating in trace-mode, an exception occurs after
execution of every instruction (using debugging-program as ESR).
• Debugging-program enables user to examine contents of registers,
memory-locations and so on.
• On return from debugging-program,next instruction in program being debugged
is executed, then debugging-program is activated again.
• The trace exception is disabled during the execution of the debugging-program.

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ii) Breakpoints

• Here, the program being debugged is interrupted only at specific points selected
by user.

• An instruction called Trap (or Software interrupt) is usually provided for this
purpose.

• When program is executed & reaches breakpoint, the user can examine memory
& register contents.

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3. Privilege Exception

• To protect OS from being corrupted by user-programs, Privileged Instructions are

executed only while processor is in supervisor-mode.

• For e.g.

When processor runs in user-mode, it will not execute instruction that change
priority of processor.

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DIRECT MEMORY ACCESS (DMA)
• The transfer of a block of data directly b/w an external device & main-memory
w/o continuous involvement by processor is called DMA.
• DMA controller → is a control circuit that performs DMA transfers (Figure 8.13).
→ is a part of the I/O device interface. → performs the functions that would
normally be carried out by processor.
• While a DMA transfer is taking place, the processor can be used to execute
another program.

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• DMA interface has three registers (Figure 8.12):

1) First register is used for storing starting-address.

2) Second register is used for storing word-count.

3) Third register contains status- & control-flags.

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• The R/W bit determines direction of transfer.
If R/W=1, controller performs a read-operation (i.e. it transfers data from memory
to I/O),
Otherwise, controller performs a write-operation (i.e. it transfers data from I/O to
memory).
• If Done=1, the controller → has completed transferring a block of data and → is
ready to receive another command. (IE Interrupt Enable).
• If IE=1, controller raises an interrupt after it has completed transferring a block of
data. • If IRQ=1, controller requests an interrupt.

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 • Requests by DMA devices for using the bus are always given higher priority
than processor requests.
• There are 2 ways in which the DMA operation can be carried out:
1) Processor originates most memory-access cycles. DMA controller is said to
"steal" memory cycles from processor. Hence, this technique is usually called
Cycle Stealing.
2) DMA controller is given exclusive access to main-memory to transfer a block of
data without any interruption. This is known as Block Mode (or burst mode).

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BUS ARBITRATION

• The device that is allowed to initiate data-transfers on bus at any given time is
called bus-master.

• There can be only one bus-master at any given time.

• Bus Arbitration is the process by which → next device to become the bus-master
is selected & → bus-mastership is transferred to that device.

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CENTRALIZED ARBITRATION
• A single bus-arbiter performs the required arbitration (Figure: 4.20).
• Normally, processor is the bus-master.
• Processor may grant bus-mastership to one of the DMA controllers.
• A DMA controller indicates that it needs to become bus-master by activating BR line.
• The signal on the BR line is the logical OR of bus-requests from all devices connected
to it.
• Then, processor activates BG1 signal indicating to DMA controllers to use bus when it
becomes free.
• BG1 signal is connected to all DMA controllers using a daisy-chain arrangement. • If
DMA controller-1 is requesting the bus,

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Then, DMA controller-1 blocks propagation of grant-signal to other devices.
Otherwise, DMA controller-1 passes the grant downstream by asserting BG2.
• Current bus-master indicates to all devices that it is using bus by activating BBSY line.
• The bus-arbiter is used to coordinate the activities of all devices requesting memory
transfers.
• Arbiter ensures that only 1 request is granted at any given time according to a priority
scheme.
(BR Bus-Request, BG Bus-Grant, BBSY Bus Busy).

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• The timing diagram shows the sequence of events for the devices connected to
the processor.

• DMA controller-2 → requests and acquires bus-mastership and → later releases

the bus. (Figure: 4.21).

• After DMA controller-2 releases the bus, the processor resources

bus-mastership.

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DISTRIBUTED ARBITRATION

• All device participate in the selection of next bus-master (Figure 4.22).

• Each device on bus is assigned a 4-bit identification number (ID).
• When 1 or more devices request bus, they → assert Start-Arbitration signal & → place
their 4-bit ID numbers on four open-collector lines ARB 0 through ARB 3 .
• A winner is selected as a result of interaction among signals transmitted over these
lines.
• Net-outcome is that the code on 4 lines represents request that has the highest ID
number.
• Advantage: This approach offers higher reliability since operation of bus is not
dependent on any single device.

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For example:
Assume 2 devices A & B have their ID 5 (0101), 6 (0110) and their code is 0111.
Each device compares the pattern on the arbitration line to its own ID starting from MSB.
If the device detects a difference at any bit position, it disables the drivers at that bit position.
Driver is disabled by placing ”0” at the input of the driver.
In e.g. “A” detects a difference in line ARB1, hence it disables the drivers on lines ARB1 & ARB0.
This causes pattern on arbitration-line to change to 0110. This means that “B” has won
contention.

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BUS
• Bus → is used to inter-connect main-memory, processor & I/O-devices →
includes lines needed to support interrupts & arbitration.

• Primary function: To provide a communication-path for transfer of data.

• Bus protocol is set of rules that govern the behavior of various devices
connected to the buses.

• Bus-protocol specifies parameters such as: → asserting control-signals → timing

of placing information on bus → rate of data-transfer.

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• A typical bus consists of 3 sets of lines:

1) Address,

2) Data &

3) Control lines.

• Control-signals → specify whether a read or a write-operation is to be performed. →

carry timing information i.e. they specify time at which I/O-devices place data on the bus.

• R/W line specifies → read-operation when R/W=1. → write-operation when R/W=0.

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• During data-transfer operation,

One device plays the role of a bus-master.

Master-device initiates the data-transfer by issuing read/write command on the

bus.

The device addressed by the master is called as Slave.

• Two types of Buses: 1) Synchronous and 2) Asynchronous.

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• The two approaches are:
1) Centralized Arbitration: A single bus-arbiter performs the required arbitration.
2) Distributed Arbitration: All devices participate in selection of next bus-master.
• A conflict may arise if both the processor and a DMA controller or two DMA controllers
try to use the bus at the same time to access the main-memory.
• To resolve this, an arbitration procedure is implemented on the bus to coordinate the
activities of all devices requesting memory transfers.
• The bus arbiter may be the processor or a separate unit connected to the bus.

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• The processor must inform the device that its request has been recognized by
sending INTA signal.

(INTR Interrupt Request, INTA Interrupt Acknowledge, ISR Interrupt Service

Routine)

• For example, consider COMPUTE and PRINT routines

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SYNCHRONOUS BUS

• All devices derive timing-information from a common clock-line.

• Equally spaced pulses on this line define equal time intervals.

• During a ”bus cycle‟, one data-transfer can take place.

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A sequence of events during a read-operation
• At time t0, the master (processor) → places the device-address on address-lines
& → sends an appropriate command on control-lines (Figure 7.3).
• The command will → indicate an input operation & → specify the length of the
operand to be read.
• Information travels over bus at a speed determined by physical & electrical
characteristics.
• Clock pulse width(t1-t0) must be longer than max. propagation-delay b/w
devices connected to bus.

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 The clock pulse width should be long to allow the devices to decode the address &
control signals.
• The slaves take no action or place any data on the bus before t1.
• Information on bus is unreliable during the period t0 to t1 because signals are changing
state.
• Slave places requested input-data on data-lines at time t1.
• At end of clock cycle (at time t2), master strobes (captures) data on data-lines into its
input-buffer
• For data to be loaded correctly into a storage device, data must be available at input of
that device for a period greater than setup-time of device.

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74
A Detailed Timing Diagram for the Read-operation

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• The picture shows two views of the signal except the clock (Figure 7.4).

• One view shows the signal seen by the master & the other is seen by the salve.

• Master sends the address & command signals on the rising edge at the
beginning of clock period (t0).

• These signals do not actually appear on the bus until tam.

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• Sometimes later, at tAS the signals reach the slave.
• The slave decodes the address.
• At t1, the slave sends the requested-data.
• At t2, the master loads the data into its input-buffer.
• Hence the period t2, tDM is the setup time for the master‟s input-buffer.
• The data must be continued to be valid after t2, for a period equal to the hold
time of that buffers.
Disadvantages
• The device does not respond. • The error will not be detected.

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Multiple Cycle Transfer for Read-operation

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• During, clock cycle-1, master sends address/command info the bus requesting a
“read‟ operation.

• The slave receives & decodes address/command information (Figure 7.5).

• At the active edge of the clock i.e. the beginning of clock cycle-2, it makes
accession to respond immediately.

• The data become ready & are placed in the bus at clock cycle-3.

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• At the same times, the slave asserts a control signal called slave-ready.

• The master strobes the data to its input-buffer at the end of clock cycle-3.

• The bus transfer operation is now complete.

• And the master sends a new address to start a new transfer in clock cycle4.

• The slave-ready signal is an acknowledgement from the slave to the master.

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ASYNCHRONOUS BUS
• This method uses handshake-signals between master and slave for coordinating
data-transfers.

• There are 2 control-lines:

1) Master-Ready (MR) is used to indicate that master is ready for a transaction.

2) Slave-Ready (SR) is used to indicate that slave is ready for a transaction.

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The Read Operation proceeds as follows:
• At t0, master places address/command information on bus.
• At t1, master sets MR-signal to 1 to inform all devices that the
address/command-info is ready.
MR-signal =1 causes all devices on the bus to decode the address.
The delay t1 – t0 is intended to allow for any skew that may occurs on the bus.
Skew occurs when 2 signals transmitted from 1 source arrive at destination at
different time
Therefore, the delay t1 – t0 should be larger than the maximum possible bus skew.

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• At t2, slave

→ performs required input-operation &

→ sets SR signal to 1 to inform all devices that it is ready (Figure 7.6).

• At t3, SR signal arrives at master indicating that the input-data are available on bus.

• At t4, master removes address/command information from bus.

• At t5, when the device-interface receives the 1-to-0 transition of MR signal, it removes
data and SR signal from the bus. This completes the input transfer.

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84
• A change of state is one signal is followed by a change is the other signal. Hence
this scheme is called as Full Handshake.

• Advantage: It provides the higher degree of flexibility and reliability.

Dr Shreema Shetty

Dept CSE

SCEM
85
INTERFACE-CIRCUITS
• An I/O Interface consists of the circuitry required to connect an I/O device to a
computer-bus.

• On one side of the interface, we have bus signals.

On the other side, we have a data path with its associated controls to transfer data
between the interface and the I/O device known as port.

• Two types are:

1. Parallel Port transfers data in the form of a number of bits (8 or 16)

simultaneously to or from the device.

2. Serial Port transmits and receives data one bit at a time.

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• Communication with the bus is the same for both formats.

• The conversion from the parallel to the serial format, and vice versa, takes place
inside the interface circuit.

• In parallel-port, the connection between the device and the computer uses

→ a multiple-pin connector and

→ a cable with as many wires.

• This arrangement is suitable for devices that are physically close to the
computer.

• In serial port, it is much more convenient and cost-effective where longer cables
are needed. Dr Shreema Shetty

Dept CSE

SCEM

87
Functions of I/O Interface

1) Provides a storage buffer for at least one word of data.

2) Contains status-flags that can be accessed by the processor to determine

whether the buffer is full or empty.

3) Contains address-decoding circuitry to determine when it is being addressed by

the processor.

4) Generates the appropriate timing signals required by the bus control scheme.

5) Performs any format conversion that may be necessary to transfer data

between the bus and the I/O device (such as parallel-serial conversion in the case
of a serial port).

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PARALLEL-PORT

Dr Shreema Shetty

Dept CSE
89
SCEM
90
• The output of the encoder consists of

→ bits representing the encoded character and

→ one signal called valid, which indicates the key is pressed.

• The information is sent to the interface-circuits (Figure 7.10).

• Interface-circuits contain

1) Data register DATAIN &

2) Status-flag SIN.

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When a key is pressed, the Valid signal changes from 0 to1.
Then, SIN=1 when ASCII code is loaded into DATAIN.
SIN = 0 when processor reads the contents of the DATAIN.
• The interface-circuit is connected to the asynchronous bus.
• Data transfers on the bus are controlled using the handshake signals:
1) Master ready &
2) Slave ready.

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INPUT-INTERFACE-CIRCUIT

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INPUT-INTERFACE-CIRCUIT
• Output-lines of DATAIN are connected to the data-lines of bus by means of
3-state drivers (Fig 4.29).

• Drivers are turned on when

→ processor issues a read signal and

→ address selects DATAIN.

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INPUT-INTERFACE-CIRCUIT

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• SIN signal is generated using a status-flag circuit .
SIN signal is connected to line D0 of the processor-bus using a 3-state driver.
• Address-decoder selects the input-interface based on bits A1 through A31.
• Bit A0 determines whether the status or data register is to be read, when
Master-ready is active.
• Processor activates the Slave-ready signal, when either the Read-status or
Read-data is equal to 1.

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PRINTER INTERFACE TO PROCESSOR

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Dr Shreema Shetty

Dept CSE
98
SCEM
99
GENERAL 8 BIT PARALLEL PROCESSING

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• Data-lines P7 through PO can be used for either input or output purposes (Figure 4.34).
• For increased flexibility,
→ some lines can be used as inputs and
→ some lines can be used as outputs.
• The DATAOUT register is connected to data-lines via 3-state drivers that are controlled
by a DDR.
• The processor can write any 8-bit pattern into DDR. (DDR Data Direction Register).
• If DDR=1,
Then, data-line acts as an output-line;
Otherwise, data-line acts as an input-line.

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• Two lines, C1 and C2 are used to control the interaction between interface-circuit and
I/0 device.
Two lines, C1 and C2 are also programmable.
• Line C2 is bidirectional to provide different modes of signaling, including the handshake.
• The Ready and Accept lines are the handshake control lines on the processor-bus side.
Hence, the Ready and Accept lines can be connected to Master-ready and Slave-ready.
• The input signal My-address should be connected to the output of an address-decoder.
The address-decoder recognizes the address assigned to the interface.
• There are 3 register select lines: RS0-RS2.
Three register select lines allows up to eight registers in the interface.
• An interrupt-request INTR is also provided.
INTR should be connected to the interrupt-request line on the computer-bus.
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