MIT Art Design and Technology University

MIT School of Computing, Pune

Department of Computer Science and Engineering

First Year Engineering

23CSE1105-Digital Electronics & Logic Design

Class - F.Y (SEM-II),

Unit - II Combinational Logic Design

Prof. Tushar Mote
AY 2024-2025 SEM-II
 Unit II - Syllabus
⮚Introduction to combinational logic.
⮚ Logical functions (SOP/POS): Standard/ canonical form,
⮚ Simplifications of logic functions using Karnaugh map (up to 4 variables),
realization using logic gates.
⮚ Design of combinational logic circuits: Multiplexers (MUX), Demultiplexers
(DEMUX), MUX/ DEMUX tree, code convertors, decoders, encoders,
⮚ 4-bit magnitude comparators, 4-bit parallel adder
 Logic Function Representations
• Set of Statements
• Truth Table
• Block Schematic
• K Map
• Boolean Expression
✔ Standard & Non-standard SOP & POS
✔ Minterms & Maxterms
✔ Standard Canonical minterms & maxterms form
• Logic Diagram
• Waveform
 Minterms / Maxterms
• A literal is variable in either uncomplemented or complemented form.
Ex for variable A, literals will be A or A’
• A minterm (m) is a special product of literals, in which each input variable
appears exactly once – standard PRODUCT term
• A maxterm (M) is a special sum of literals, in which each input variable
appears exactly once – standard SUM term
• A function with n variables has 2n minterms & maxterms (since each variable
can appear complemented or not)
• A three-variable function, such as f (x,y,z), has 23 = 8 minterms & maxterms
namely: m0, m1,……m7 & M0, M1,………M7.
• Minterm is TRUE for logical value of 1 & Maxterm is TRUE for logical value of 0

4
 MINTERMs & MAXTERMs
Input Variables Minterms Maxterms
x y z Term Designation Term Designation
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
 MINTERMs & MAXTERMs

Input variables Minterms Maxterms

x y z Term Symbol Term Symbol
0 0 0 x’y’z’ m0 x+y+z M0
0 0 1 x’y’z m1 x+y+z’ M1
0 1 0 x’yz’ m2 x+y’+z M2
0 1 1 x’yz m3 x+y’+z’ M3
1 0 0 xy’z’ m4 x’+y+z M4
1 0 1 xy’z m5 x’+y+z’ M5
1 1 0 xyz’ m6 x’+y’+z M6
1 1 1 xyz m7 x’+y’+z’ M7

BITS Pilani, Pilani Campus

 Sum of Minterms Form
• Every function can be written as a sum of minterms, which is a special
kind of sum of products form
• The sum of minterms form for any function is unique
• If you have a truth table for a function, you can write a sum of minterms
expression just by picking out the rows of the table where the function
output is 1
• f = x’y’z’ + x’y’z + x’yz’ + x’yz + xyz’
= m0 + m1 + m2 + m3 + m6
= Σm(0,1,2,3,6)
• f’ = xy’z’ + xy’z + xyz
= m4 + m5 + m7
= Σm(4,5,7)
• f’ contains all the minterms not in f

7
 Product of Maxterms Form
• Every function can be written as a product of maxterms, which is a
special kind of product of sums form
• The product of maxterms form for any function is unique
• If you have a truth table for a function, you can write a product of
maxterms expression just by picking out the rows of the table where
the function output is 0
• f = (x’+y+z).(x’+y+z’).(x’+y’+z’)
= M 4 . M 5 . M7
= πM(4,5,7)
• f’ = (x+y+z) . (x+y+z’) . (x+y’+z) .
(x+y’+z’) . (x’+y’+z’)
= M 0 . M1 . M2 . M 3 . M 6
= πM(0,1,2,3,6)
• f’ contains all the maxterms not in f
8
 Conversion between minterms
& Maxterms equation
f = x’y’z’ + x’y’z + x’yz’ + x’yz + xyz’
= m0 + m1 + m2 + m3 + m6
= Σm(0,1,2,3,6) = = πM(4,5,7)
f’ = xy’z’ + xy’z + xyz
= m4 + m5 + m7
= Σm(4,5,7) = πM(0,1,2,3,6)
f = (x’+y+z).(x’+y+z’).(x’+y’+z’)
= M4 . M5 . M7
= πM(4,5,7) = Σm(0,1,2,3,6)
f’ = (x+y+z) . (x+y+z’) . (x+y’+z) .
(x+y’+z’) . (x’+y’+z’)
= M0 . M1 . M2 . M3 . M6
= πM(0,1,2,3,6) = Σm(4,5,7)
 Logic Function Simplification
• Why simplify?
– Simpler expression uses less logic gates
– Thus: cheaper, less power, faster (sometimes)
• Simplification techniques:
– Algebraic Simplification
• Simplify Boolean functions by means of basic identities and theorems
• Requires skill and it lacks specific rules to predict each succeeding step in the
minimization process
– Karnaugh Maps - A graphical technique for simplifying an expression
• Advantages
– A more orderly process with well-defined steps compared with the trial-and-
error process sometimes used in algebraic simplification
– Always able to produce a minimum expression
• Disadvantage: Limited to 5 or 6 variables
– Quine-McCluskey
• Suitable for automation
• Can handle many variables (but computationally intensive)

10
Description of K-map and Terminology

• A K-map is a matrix consisting of rows and columns that

represent the output values of a Boolean function
• Objective: Fewest possible product terms and literals.
• Diagrammatic technique based on a special form of Venn
diagram
• K-map can be of two forms
– Sum-of-Product (SOP) Form
– Product-of-Sum (POS) Form

11
 2 Variable K map
• A two-variable function has four possible minterms. We can re-arrange these
minterms into a Karnaugh map

• Now we can easily see which minterms contain common literals

– Minterms on the left and right sides contain y’ and y respectively
– Minterms in the top and bottom rows contain x’ and x respectively
– Each cell in a 2-variable K-map has 2 adjacent neighbours.

12
 3 Variables K-Maps

• There are 8 minterms for 3 variables (a, b, c). Therefore, there are 8 cells in a
3 variable K-map b b
bc bc
a a
00 01 11 10 00 01 11 10
0 a'b'c' a'b'c a'bc a'bc' 0 m0 m1 m3 m2

a ab'c' ab'c abc abc' a m4 m5 m7 m6

1 1

c c

Note Gray code sequence

• Above arrangement ensures that minterms of adjacent cells differ by just one
variable both horizontally and vertically.
• Each cell in a 3-variable K-map has 3 adjacent neighbours.
13
 4 Variable K-maps
• Total cells are 16, representing 16 minterms possible with 4
variables.
• There are 2 wrap-arounds: a horizontal wrap-around and a
vertical wrap-around
• Every cell thus has 4 neighbours. For example, the cell
corresponding to minterm m0 has neighbours m1, m2, m4 and m8

yz y
in an n-variable K-map, wx
m0 m1 m3 m2
each cell has n adjacent m4 m5 m7 m6

neighbours m12 m13 m15 m14

x

w
m8 m9 m11 m10

14
 Adjacencies
• Adjacencies on three and four-variable maps

15
 Remarks about Groups
• Groups of minterms must be:
(1) Rectangular, and
(2) Have size in powers of 2’s (i.e. 1, 2, 4, 8, 16 etc.)
Otherwise they are invalid groups. Some examples of invalid
groups are:

1 1 1 1

1 1 1 1

1 1 1

1 1 1 1 1

Grouping 2n squares eliminates n variables

16
 Remarks about Groups
• Groups of minterms must be:
(1) Rectangular, and
(2) Have size in powers of 2’s (i.e. 1, 2, 4, 8, 16 etc.)
Otherwise they are invalid groups. Some examples of invalid
groups are:

1 1 1 1

1 1 1 1

1 1 1

1 1 1 1 1

Grouping 2n squares eliminates n variables

17
 Remarks about Groups
• Groups of minterms must be:
(1) Rectangular, and
(2) Have size in powers of 2’s (i.e. 1, 2, 4, 8, 16 etc.)
Otherwise they are invalid groups. Some examples of invalid
groups are:

1 1 1 1

1 1 1 1

1 1 1

1 1 1 1 1

Grouping 2n squares eliminates n variables

18
 PIs AND EPIs (1/3)

• To find the simplest (minimal) SOP expression from a K-

map, you need to obtain:
– Minimum number of literals per product term; and
– Minimum number of product terms.

• Achieved through K-map using

– Bigger groupings of minterms (prime implicants) where possible;
and
– No redundant groupings (look for essential prime implicants)

• Implicant: a product term that could be used to cover

minterms of the function.
 PIs AND EPIs (2/3)
• Prime implicant (PI): a product term obtained by
combining the maximum possible number of minterms from
adjacent squares in the map.
(That is, it is the biggest grouping possible.)
• Always look for prime implicants in a K-map.

1 1 1 1 1 1

🗴 ✓
1 1 1 1 1 1
 PIs and EPIs (3/3)
• No redundant groups:

1 1 1 1

1
1

1
1
🗴 1
1

1
1
✓
1 1 1 1

Essential prime implicants

■ Essential prime implicant (EPI): a prime implicant that

includes at least one minterm that is not covered by any
other prime implicant.
Grouping – 2 Adjacent cells (Pair)
• Grouping is a process of grouping the cells which contain 1s. The
output expression can be simplified by properly combining those
squares in the K map that contain 1s

Grouping a pair
of adjacent 1s
eliminates one
variable that
appears in both
complemented
and
uncomplemented
form

22
 Examples of Grouping Fours 1s
(Quads)

Grouping a quad
of adjacent 1s
eliminates the
two variables
that appears in
both
complemented
and
uncomplemented
form

23
Examples of Grouping Eight 1s (Octets)
• Grouping an octet
of adjacent 1s
eliminates the
three variables
that appears in
both
complemented
and
uncomplemented
form
• In General, group of 2n
variables, eliminates n
variables from Boolean
function.
24
 Complete Simplification Process

⮚ Construct the required K map and place 1s and 0s in the

squares according to the truth table

⮚ Grouping all the 1s which are logically adjacent to form

minimum number of groups with maximum size.

⮚ Check for redundancy to remove redundant groups, if any.

⮚ Write product term for all the groups(EPI’s) & Form the
OR sum of all the terms generated by each group.

25
K-Map Simplification of POS Expression -
Example CD1: F = π M(0,1,2,8,9,10,11,14,15)
AB How Many 0’s? –
00 01 11 10
How to cover these 0’s?
00 i.e. Groups-
0 1 3 2 1.Octets –
01
6 2.Quads-
4 5 7
11
12 13 15 14 3.Pairs-
10
8 9 11 10 4. Isolated 1’s -

Boolean Expression for each Simplified Boolean Expression =

Group + + + +
1
2
3
4
Solution:
K-Map Simplification of SOP Expression -
Example 2: F = Σ m(1,3,4,5,8,9,13,15)
CD
AB
10 How Many 1’s? –
00 01 11
How to cover these 1’s?
00 i.e. Groups-
0 1 3 2 1.Octets –
01
2.Quads-
4 5 7 6
11
12 13 15 14 3.Pairs-
10
8 9 11 10 4. Isolated 1’s -

Boolean Expression for each Simplified Boolean Expression =

Group + + + +
1
2
3
4
Solution:
K-Map Simplification of SOP Expression -
Example
CD
3: F = Σ m(2,5,7,11,13,15)
AB
00 01 11 10 How Many 1’s? –
How to cover these 1’s?
00 i.e. Groups-
0 1 3 2 1.Octets –
01
4 5 7 6 2.Quads-
11
12 13 15 14
3.Pairs- 11,22
10
8 9 11 10 4. Isolated 1’s -

Boolean Expression for each Simplified Boolean Expression =

Group + + + +
1
2
3
4
Solution:
 The Same K-Map with Two
Equally Good Solutions
• Consider the K map in Figure

• For this map, there are two possible Groupings, which require only
four pairs. Figure (a) shows one solution and Figure (b) shows the
other. Both expressions are of the same complexity, and so neither is
better than the other

32
 Converting to Minterms Form

• The K-map of a function is easily drawn when the

function is given in standard sum-of-products, or
sum-of-minterms form

• What if the function is not in sum-of-minterms?

– Convert it to sum-of-products (SOP) form
– Expand the SOP expression into sum-of-minterms
expression, or fill in the K-map directly based on the SOP
expression

33
 Example
• Use a K map to simplify
• Solution:
• Step 1: Multiply out the first term to get

• Step 2: Put 1’s & 0’s in the cells of k map

• Step 3: Group adjacent cells on k map
• Step 2: Write simplified Boolean expression
How Many 1’s? –
CD
AB How to cover these 1’s?
00 01 11 10 i.e. Groups-
1.Octets –
00
0 1 3 2
2.Quads-
01 7
4 5 6
3.Pairs-
11 12 13 15 14
4. Isolated 1’s -
10 8 9 11 10
34
Solution:
 Don’t-Care Conditions
• You don’t always need all 2n input
combinations in an n-variable
function
– If you can guarantee that certain
input combinations never occur.
For example, when dealing with
Binary-coded decimal (BCD), the
inputs for 1010 - 1111 (10-15)
will never occur
– When a certain input(s) will occur, • Don’t-care conditions can be
but we don’t care what the output used to help simplify Boolean
will be in response to them as we expression further in K-maps
are not going to use them in our • They could be chosen to be
circuit either '1' or '0', depending on
• We mark don’t-care outputs in truth which value will help the
tables and K-maps with Xs minimization

36
Example of Don’t Care Condition
Simplification
• Don't-care conditions should be changed to either 0 or 1 to
produce K-map looping that yields the simplest expression

37
Don’t Care Condition: Example 1
C
CD
• For comparison: AB 00 01 11 10

– WITHOUT Don’t-cares:
00
1 1
P = A'B'C'D’ + A'B'CD + A'BC'D 01
1 1
B
+ A'BCD' + AB'C'D 11
A
10 1
• Note: Cells with ‘0’ are not D
shown for clarity C
CD
AB 00 01 11 10
00 1 1
– WITH Don’t-cares:
P = A'B'C'D' + B'CD + BC'D 1
01
1
B
+ BCD' + AD 11 X X X X
A
10 1 X X

38
 Example 2
• Simplify the Boolean function represented by the following truth table.
Note don’t care conditions are marked as X’s in the truth table

• Solution: Firstly, we can extract the minterms

and write the standard SOP form of the
function:
F(W,X,Y,Z) = Σ m(1,3,7,11,15)

The don’t care conditions are expressed as:

d(W,X,Y,Z) = Σ d(0,2,5)

Thus, the entire function may be expressed as:

F(W,X,Y,Z) = Σ m(1,3,7,11,15) + Σ d(0,2,5)

39
 Example 2 (Cont.)

1. Place 1’s in the squares for minterms (1,3,7,11,15)

2. Place X’s in the squares for don’t cares (0,2,5)
3. Place 0’s in the remaining squares (4,6,8,9,10,12,13,14)
4. Group the adjacent 1’s (including any applicable X’s) into
the largest 2n groupings. One minimum solution uses the X
in the second row to yield the term . The other grouping
of 4 yields the term YZ

Thus, the solution is:

40
Ex- OR & Ex NOR Simplification on K
Map

In the case of EX-OR/EX-

NOR simplification we have
to look for:

1. Diagonal adjacencies, and

2. Offset adjacencies

41
Diagonal & Offset Adjacencies

42
 Checkerboard Pattern in K-Map
• When we rearrange the Exclusive-OR truth table to a K-Map as
shown below, we would observe Karnaugh map displays a
checkerboard pattern (every other square) of 0s and 1s and we
cannot form any groups on the map
• On a Karnaugh map diagonally adjacent terms can be simplified by
using either XOR or XNOR functions as functional elements

Truth table of K-Map for 2 variables K-Map for 3 variables K-Map for 4
EX-OR gate variables

43
 Odd and Even Functions
• For more than 2 inputs, XOR is called an odd function
– It is equal to 1 if the input variables have an odd number of 1’s
• Similarly, for more than 2 inputs, XNOR is called an even function
– It is equal to 1 if the input variables have an even number of 1’s

• As shown in the K-map, A ⊕ B ⊕ C = 1, if and only if the number of 1’s in

the input combination is odd
■ As Since XOR gates are only designed with 2
inputs, the 3-input XOR function is
implemented by means of two 2-input XOR
gates, as shown in figure

44
Odd and Even Function Examples

45
 MORE EXAMPLES (1/6)

• Example #2:
F(A,B,C,D) = A⋅B⋅C + B'⋅C⋅D' + A⋅D + B'⋅C'⋅D'

A
AB
CD 00 01 11 10

00 1 1
Fill in the 1’s.
01 1 1
D
11 1 1
C
10 1 1 1

B
 MORE EXAMPLES (2/6)
• Example #2:
F(A,B,C,D) = A⋅B⋅C + B'⋅C⋅D' + A⋅D + B'⋅C'⋅D'

A
AB
CD 00 01 11 10

00 1 1

01 1 1
D Find all PIs:
11 1 1
C
10 1 1 1

So the answer is: F(A,B,C,D) =

 MORE EXAMPLES (3/6)
• Example #3 (with don’t-cares):
F(A,B,C,D) = Σm(2,8,10,15) + Σd(0,1,3,7)

A
AB
CD 00 01 11 10

00 X 1
Fill in the 1’s and X’s.
01 X
D
11 X X 1
C
10 1 1

B
 MORE EXAMPLES (4/6)
• Example #3 (with don’t-cares):
F(A,B,C,D) = Σm(2,8,10,15) + Σd(0,1,3,7)

A Do we need to have an
AB
CD 00 01 11 10 additional term A'⋅B' to
00 X 1 cover the 2 remaining X’s?
01 X
D
11 X X 1
C
10 1 1

Answer: F(A,B,C,D) =
 MORE EXAMPLES (5/6)
• Find the simplest POS expression for example #2:
F(A,B,C,D) = A⋅B⋅C + B'⋅C⋅D' + A⋅D + B'⋅C'⋅D'

SOP FORM POS FORM

 MORE EXAMPLES (6/6)
• Find the simplest POS expression for example #3:
F(A,B,C,D) = Σm (2,8,10,15) + Σd (0,1,3,7)
Example: Draw the K-map of the complement of F, that is, F'.
F(A,B,C,D) = Σm (4,5,6,9,11,12,13,14) + Σd (0,1,3,7)

K-map of F’:
Answer in
SOP Form

K-map for Function F K-map of F’:

Answer in
Compliment of Function POS Form
 Combinational Logic Circuits
• The term "combinational" comes to us from mathematics which means an
unordered set where nobody cares which order the items came in
• With combinational logic, the circuit always produces the same output
solely by a given set of inputs , regardless of the order the inputs are
changed
• If there are m outputs and n inputs then there are m Boolean functions,
one describing each outputs
• The inside of a combinational circuit is made of logic gates and it does not
store any information (i.e. memoryless)
• There are circuits which depend on inputs and previous outputs. These
circuits are called sequential logic where we will discuss in later chapter
• Combinational logic circuits are important components of digital systems
Combinational vs. Sequential Logic

(a) Combinational (b) Sequential

Output = F (In) Output = F (In, Previous In)
 Designing Combinational Circuits
• In general we have to do following steps:
1. From the specifications of the circuit, determine the required
number of inputs and outputs and assign a letter symbol to
each
2. Derive the truth table that defines the relationship between
inputs and outputs
3. Obtain the simplified Boolean functions for each output as a
function of the input variables
4. Draw the logic diagram
5. Verify the correctness of the design
 Arithmetic Circuits

• Arithmetic circuits are the ones which perform arithmetic

calculations on binary numbers like addition, subtraction,
multiplication, and division etc.
• Arithmetic circuits can be built using logic circuits and they are
excellent examples of combinational logic design
• We will build arithmetic circuits by using the design procedure as stated
previously
 Adder

• Adders are the basic building blocks of all arithmetic circuits

• Adders add two binary numbers and give out sum and carry as output
• In modern computers adders reside in the arithmetic and logic unit (ALU)
where other operations are performed
• Basically we have two types of adders
• Half Adder
• Full Adder
 Half Adder
• Adding two single-bit binary values, X, Y produces a sum S bit and a carry out C-out bit
• This operation is called half addition and the circuit to realize it is called a half adder

S(X,Y) = Σ (1,2)

S = X⊕Y

Half Adder Truth Table C-out(X,Y) = Σ (3)

Inputs Outputs C-out = XY

X Y S C-out X
0 0 0 0 Y
Sum S

0 1 1 0
1 0 1 0 C-out
1 1 0 1
58
 Full Adder
• Adding two single-bit binary Sum S X

values, X, Y with a carry input

XY
C-in 00 01 11 10
bit C-in produces a sum bit S 0
0 2
1
6 4
1
and a carry out C-out bit 1 3 7 5
1 1 1 C-in

Y
The S function is the three-bit XOR function (Odd
Function): S = X ⊕ Y ⊕ (C-in)

Carry C-out X
XY
C-in 00 01 11 10
0 2 6 4
0 1
1 3 7 5
1 1 1 1 C-in

Y
C-out = XY + X(C-in) + Y(C-in)
Full Adder Circuit using XOR and Basic Gates
• Logical Implementation
Full Adder implemented by Two Half
Adders and an OR Gate
• A ‘Full Adder’ can also be implemented using
two half adders and an ‘OR’ Gate as follows:
The sum S = X ⊕ Y ⊕ (C-in)
The carry out
 Full Adder implemented by Two Half
Adders and an OR Gate
• Therefore and

• Block diagram representation of a

full adder using two half adders
 Digital Comparator
⮚ A comparator is a logic circuit used to compare the magnitudes of two
binary numbers.
⮚ Depending on the design, it may either simply provide an output that is active
(goes HIGH for example) when the two numbers are equal, or additionally
provide outputs that signify which of the numbers is greater when
equality does not hold.
⮚ The X-NOR gate (coincidence gate) is a basic comparator, because its output
is a 1 only if its two input bits are equal, i.e. the output is a 1 if and only if the
input bits coincide.
⮚ Let the two 4-bit numbers be A = A3A2A1A0 and B = B3B2B1B0.
⮚ EQUALITY = (A3 ʘ B3)(A2 ʘ B2)(A1 ʘ B1)(A0 ʘ B0)
 DIGITAL COMPARATOR

Block Schematic of n bit Digital Comparator

Design of 1-bit Magnitude Comparator

A=B: E = A0 ʘ B0
 Digital Components
■ High level digital circuit designs are normally made
using collections of logic gates referred to as
components, rather than using individual logic gates
■ Levels of integration (numbers of gates) in an
integrated circuit (IC):
■ Small scale integration (SSI): 10-100 gates
■ Medium scale integration (MSI): 100 to 1000 gates
■ Large scale integration (LSI): 1000-10,000 logic gates
■ Very large scale integration (VLSI): 10,000-upward
■ Common MSI circuits include encoders, decoders,
multiplexers, and demultiplexers
What we need to know about an MSI
circuit?
■ Function: what it does
■ Truth-table: input-output
■ Logic gate diagram: how it does it
■ Packaging (module pin-out): how to build it
■ Dynamic behavior (timing diagram):
■ Applications: where to use it
Multiplexers and De-Multiplexers
■ A multiplexer or mux selects one data line from two or more input
lines and routes data from the selected line to the output. The
particular data line that is selected is determined by the select
inputs
■ A demultiplexer or Demux performs the opposite function from a
MUX. It switches data from one input line to two or more data lines
depending on the select inputs
MULTIPLEXERS (1/5)
■ A multiplexer is a device which has
■ A number of input lines
■ A number of selection lines
■ One output line
■ It steers one of 2n inputs to a single output line, using n
selection lines. Also known as a data selector.

2n:1
inputs : Multiplexer output

...
MSB
select LSB
 MULTIPLEXERS (2/5)
■ Truth table for a 4-to-1 multiplexer:

Inputs Inputs
I0 0 I0
I1 4:1 I1
1 4:1
MUX Y
I2 2 Y Output I2 mux
I3 3 I3
S1 S0
S1 S0
select select
 MULTIPLEXERS (3/5)
■ Output of multiplexer is
“sum of the (product of data lines and selection lines)”
■ Example: Output of a 4-to-1 multiplexer is:
Y=?
■ A 2n-to-1-line multiplexer, or simply 2n:1 MUX, is made
from an n:2n decoder by adding to it 2n input lines, one to
each AND gate.
 MULTIPLEXERS (4/5)
■ A 4:1 multiplexer circuit:

I0

I1
Y
I2

I3

S1 S0
 MULTIPLEXERS (5/5)
■ An application:

■ Helps share a single communication line among a number

of devices.
■ At any time, only one source and one destination can use
the communication line.
 MULTIPLEXER IC PACKAGE
■ Some IC packages have a few multiplexers in each package (chip). The
selection and enable inputs are common to all multiplexers within the
package.
A0
Y0
A1
Y1
A2
Y2
A3
Y3
B0
B1
B2
B3
S
(select)
Quadruple 2:1 multiplexer
E'
(enable)
 LARGER MULTIPLEXERS (1/4)
■ Larger multiplexers can be constructed from smaller ones.
■ An 8-to-1 multiplexer can be constructed from smaller
multiplexers like this (note placement of selector lines):

I0
I1 4:1
I2 MUX
I3
2:1
S1 S0 MUX Y
I4
I5 4:1
I6 MUX S2
I7

S1 S0
LARGER MULTIPLEXERS (2/4)
I0
I0 I1 I2
I1 4:1
I2 MUX
I3
2:1
S1 S0 MUX Y I0 I1 I6
I4
I5 4:1 I4 I5 I6
I6 MUX S2
I7

S1 S0

■ When S2S1S0 = 000

■ When S2S1S0 = 001
■ When S2S1S0 = 110
 LARGER MULTIPLEXERS (3/4)
■ Another implementation of an 8-to-1 multiplexer using
smaller multiplexers:
When
I0 2:1 I0 S2S1S0 = 000
I1 MUX

I2 2:1 I2 S0
I3 MUX
4:1
S0 MUX Y I0
I4 2:1 I4
I5 MUX
S2 S1
S0 I6 2:1 Q: Can we use only 2:1
I7 MUX I6
multiplexers?
S0
MULTIPLEXERS: IMPLEMENTING FUNCTIONS (1/3)
■ Boolean functions can be implemented using multiplexers.
■ A 2n-to-1 multiplexer can implement a Boolean function of
n input variables, as follows:
1. Express in sum-of-minterms form. Example:
F(A,B,C) = A'⋅B'⋅C + A'⋅B⋅C + A⋅B'⋅C + A⋅B⋅C'
= Σ m(1,3,5,6)
2. Connect n variables to the n selection lines.
3. Put a ‘1’ on a data line if it is a minterm of the function, or ‘0’
otherwise.
MULTIPLEXERS: IMPLEMENTING FUNCTIONS (2/3)
■ F(A,B,C) = Σ m(1,3,5,6)

This method works because:

0 0
Output = m0⋅I0 + m1⋅I1 + m2⋅I2 + m3⋅I3
1 1 + m4⋅I4 + m5⋅I5 + m6⋅I6 + m7⋅I7
0 2
1 3 mux F
0 4 Supplying ‘1’ to I1,I3,I5,I6 , and ‘0’ to the rest:
1 5
1 6 Output = m1 + m3 + m5 + m6
0 7

A B C
MULTIPLEXERS: IMPLEMENTING FUNCTIONS (3/3)
■ Example: Use a 74151A to implement
f(x1,x2,x3) = Σ m(0,2,3,5)

Realization of f(x1,x2,x3) = ∑m(0,2,3,5).

(a) Truth table.
(b) Implementation with 74151A.
USING SMALLER MULTIPLEXERS (1/6)

■ Earlier, we saw how a 2n-to-1 multiplexer can be used to

implement a Boolean function of n (input) variables.
■ However, we can use a single smaller 2(n-1)-to-1
multiplexer to implement a Boolean function of n (input)
variables.
■ Example: The function
F(A,B,C) = Σ m(1,3,5,6)
can be implemented using a 4-to-1 multiplexer (rather
than an 8-to-1 multiplexer).
USING SMALLER MULTIPLEXERS (2/6)
■ Let’s look at this example:
F(A,B,C) = Σ m(0,1,3,6) = A'⋅B'⋅C' + A'⋅B'⋅C + A'⋅B⋅C + A⋅B⋅C'

1 0
1 1
0 2 1 0
1 3 mux F
C 1 F
0 4 mux
0 5 0 2
1 6 C' 3
0 7
A B C A B

■ Note: Two of the variables, A and B, are applied as selection lines

of the multiplexer, while the inputs of the multiplexer contain 1, C,
0 and C'.
 USING SMALLER MULTIPLEXERS (3/6)
■ Procedure
1. Express Boolean function in sum-of-minterms form.
Example: F(A,B,C) = Σ m(0,1,3,6)
2. Reserve one variable (in our example, we take the least
significant one) for input lines of multiplexer, and use
the rest for selection lines.
Example: C is for input lines; A and B for selection lines.
 USING SMALLER MULTIPLEXERS (4/6)
3. Draw the truth table for function, by grouping inputs by selection
line values, then determine multiplexer inputs by comparing input
line (C) and function (F) for corresponding selection line values.

MUX
A B C F
input
0 0 0 1
0 0 1 1 ? 0
0 1 0 0 ? 1 F
mux
0 1 1 1 ? 2
1 0 0 0 ? 3
1 0 1 0
1 1 0 1 A B
1 1 1 0
◈
USING SMALLER MULTIPLEXERS (6/6)
■ Example: Implement the function below with 74151A:
f(x1,x2,x3,x4) = Σ m(0,1,2,3,4,9,13,14,15)
■ Hardware Reduction Table
f(A,B,C) = m(1,2,4,7)
D0 D1 D2 D3

0 2 4 6
C

C 1 3 5 7

i/p to MUX C C C C

D0 D1 D2 D3

0 1 2 3
A

A 4 5 6 7

i/p to MUX A A A A
 DEMULTIPLEXERS (1/4)
■ Given an input line and a set of selection lines, a
demultiplexer directs data from the input to one of the
selected output line.
■ Example: 1-to-4 demultiplexer.
Outputs

Y0 = D∙S1'∙S0'
Y1 = D∙S1'∙S0
Data D demux
Y2 = D∙S1∙S0'
Y3 = D∙S1∙S0

S1 S0
select
 DEMULTIPLEXERS (2/4)
■ It turns out that the demultiplexer circuit is actually
identical to a decoder with enable.

2×4 0 Y0 = ?
Decoder 1
S1 A Y1 = ?
S0 B 2 Y2 = ?
3 Y3 = ?
E

D
Implementation of Boolean Function Using Demultiplexer (3/4)
Example 1: Implement the Function f(A,B,C)=m(0,1,3,5) using 1:8 demultiplexer.
Example 2: Full adder implementation using Demultiplexer
(4/4)

S(A,B,Cin) = ∑(1,2,4,7)
Cout(A,B,Cin) = ∑(3,5,6,7)
 Decoders
■ A combinational circuit that converts binary
information from n coded inputs to a maximum 2n
coded outputs → n to 2n decoder
■ n-to-m decoder, m ≤ 2n
■ Examples: BCD-to-7-segment decoder,
where n = 4 and m = 10
■ Enable input: it must be on (active) for the decoder to
function, otherwise its outputs assume a single
"disabled" output code word
Decoders (Cont.)

Only one output is HIGH for

each input code
2-to-4 Decoder
■ This is what a 2-to-4 decoder looks like on the inside
Encoders
■ Performs the inverse operation of a decoder
■ Has M input lines and N output lines of which only one
input line is usually active at a time
■ The output generates an N-bit output code dependent
upon which input is activated
 ENCODERS
■ Example: Octal-to-binary encoder.
■ At any one time, only one input line has a value of 1.
■ Otherwise, we need priority encoder.
 ENCODERS
■ Example: Octal-to-binary encoder.
D0
D1 x = D4 + D5 + D6 + D7
D2
D3 y = D2 + D3 + D6 + D7
D4
D5
D6
D7 z = D1 + D3 + D5 + D7

An 8-to-3 encoder

■ Exercise: Can you design a 2n-to-n encoder without using

K-map?
 Computer Science
& PRIORITY
Engineering
ENCODERS
⮚ The encoders discussed so far will operate correctly, provided that
one and only one decimal input is HIGH at any given time.

⮚ A priority encoder is a logic circuit that responds to just one input

in accordance with some priority system, among all those that
may be simultaneously HIGH.

⮚ The most common priority system is based on the relative

magnitudes of the inputs; whichever decimal input is the largest,
is the one that is encoded.

⮚ Example: A priority encoder would encode decimal 4 if both 3 and

4 are simultaneously HIGH.
 Computer Science
& 4-Input Priority
Engineering
Encoder
⮚ In addition to the outputs A and B, the circuit has a third output designated by
V.

⮚ This is a valid bit indicator that is set to 1 when one or more inputs are equal
to 1. If all inputs are 0, there is no valid input and V is equal to 0.

⮚ The minterms for the two functions A and B are derived from the table as
A = Σ m(1, 2, 3, 5, 6, 7, 9, 10, 11, 13, 14, 15)
B = Σ m(1, 3, 4, 5, 7, 9, 11, 12, 13, 15)