Signal Conditioning and Data Acquisition Circuits -Dr.

H N Suresh

B.E. Electronics and Instrumentation Engineering (EI)

Choice Based Credit System (CBCS)
Semester – IV
Signal Conditioning and Data Acquisition Circuits
(Common to EI, BM & ML)

Module -4
Notes
Prepared by
Dr.H N Suresh
Professor
Dept.of Electronics and Instrumentation Engineering
Bangalore Institute of Technology
V V PURAM,BENGALURU-04

Dept. Electronics & Instrumentation , BIT, Bengaluru-04

 Signal Conditioning and Data Acquisition Circuits -Dr.H N Suresh

Subject Code : 18 EI/BM/ML42 CIE Marks : 40

Course Learning Objectives: This course will enable the students to

 Define and describe Op Amp, basic concepts, characteristics and specification
 Gain knowledge about Linear and nonlinear applications op-amp.
 Design and develop circuits like, amplifiers, filters, Timers to meet industrial requirements.
 Get a firm grasp of basic principles of op-amp.

Revised Bloom’s Taxonomy Levels: L1 – Remembering, L2 – Understanding, L3 – Applying, L4 –

Analyzing, L5 – Evaluating, and L6 – Creating

Course Outcomes: After studying this course, students will able to:
1. Understand the basic principles and operation of op-amp.
2. Design and develop circuits to meet the practical applications
3. Implement and integrate the op-amp circuits in electronic gadgets.

Graduate Attributes (as per NBA)

 Engineering knowledge
 Problem analysis
 Design & development of solutions
 Investigation of Complex Problem
Question Paper Pattern:
 The question paper will have TEN questions.
 Each full question carry 20 marks
 There will be TWO full questions (with maximum of THREE sub questions) from each
module.
 Each full question will have sub questions covering all the topics under a module.
 The students will have to answer FIVE full questions, selecting ONE full question from each
module.
Text Books:

1. “Linear Integrated Circuits”, D. Roy Choudhury and Shail B. Jain, 4 th edition, Reprint 2010, New
Age International. (Module -1,2,3,4 & 5)
2. “Op - Amps and Linear Integrated Circuits”, Ramakant A. Gayakwad, 4 th edition, PHI (Module-3)
3. “A course in Electrical & Electronic Measurements & Instrumentation”, A K Sawhney, Dhanpat
Rai Publications, 19th edition, 2011.(Module-5)
Reference Books:
1. “Operational Amplifiers and Linear Integrated Circuits”, Robert. F. Coughlin & Fred. F. Driscoll,
PHI/Pearson, 2006
2. “Op - Amps and Linear Integrated Circuits”, James M. Fiore, Thomson Learning, 2001
3. “Design with Operational Amplifiers and Analog Integrated Circuits”, Sergio Franco, TMH, 3e,
2005

Syllubus: Module -4

555 Timer:Description of Functional Diagram, Monostable operation, Applications of

Monostable Multivibrator: Frequency Divider & Pulse Width Modulation. Astable operation,
Applications of Astable Multivibrator: FSK Generator and Pulse Position Modulation. Phase
Locked Loops: Basic Principles, Analog phase Detector/comparator, Voltage controlled

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 Signal Conditioning and Data Acquisition Circuits -Dr.H N Suresh

oscillator .PLL applications: Frequency Multiplication/Division, Frequency translation, FM

demodulation.

Explain the Pin description and explain the monostable and Astable operation of The
555 Timer

IC The 555 is a monolithic timing circuit that can produce accurate & highly stable time delays
or oscillation. The timer basically operates in one of two modes: either

Monostable (one - shot) multi vibrator

(ii) Astable (free running) multi vibrator

The important features of the 555 timer are these:

(i) It operates on +5v to +18 v supply voltages
(ii) It has an adjustable duty cycle
(iii) Timing is from microseconds to hours
(iv) It has a current o/p rator or

PIN CONFIGURATION

Pin description:
Pin 1: Ground: All voltages are measured with respect to this terminal.
Pin 2: Trigger:T he o/p of the timer depends on the amplitude of the external trigger pulse
applied to this pin.
Pin 3: Output: There are 2 ways a load can be connected to the o/p terminal either between
pin3& ground or between pin 3 & supply voltage(Between Pin 3 & Ground ON load) (Between
Pin 3 & + Vcc OFF load)

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 Signal Conditioning and Data Acquisition Circuits -Dr.H N Suresh

(i) When the input is low:The load current flows through the load connected between Pin 3 &
+Vcc in to the output terminal & is called the sink current.
(ii) When the output is high: The current through the load connected between Pin 3 & +Vcc
(i.e. ON load) is zero. However the output terminal supplies currentto the normally OFF load.
This current is called the source current.
Pin 4: Reset: The 555 timer can be reset (disabled) by applying a negative pulse to this pin.
When the reset function is not in use, the reset terminal should be connected to +Vcc to avoid
any false triggering.
Pin 5: Control voltage: An external voltage applied to this terminal changes the threshold as
well as trigger voltage. In other words by connecting a potentiometer between this pin& GND,
the pulse width of the output waveform can be varied. When not used,the control pin should
be bypassed to ground with 0.01 capacitor to prevent anynoise problems.
Pin 6: Threshold: This is the non inverting input terminal of upper comparator which monitors
the voltage across the external capacitor.
Pin 7: Discharge: This pin is connected internally to the collector of transistor Q1.
When the output is high Q1 is OFF.
When the output is low Q is (saturated) ON.
Pin 8: +Vcc: The supply voltage of +5V to +18V is applied to this pin with respect to ground.
From the figure, three 5k internal resistors act as voltage divider providing bias voltage of 2/3
Vcc to the upper comparator & 1/3 Vcc to the lower comparator. It is possible to vary time
electronically by applying a modulation voltage to the control voltage input terminal (5).
(i) In the Stable state: The output of the control FF is high. This means that the output
is low because of power amplifier which is basically an inverter. Q = 1; Output = 0
(ii) At the Negative going trigger pulse: The trigger passes through (Vcc/3) the output of the
lower comparator goes high & sets the FF. Q = 1; Q = 0
(iii) At the Positive going trigger pulse: It passes through 2/3Vcc, the output of the upper
comparator goes high and resets the FF. Q = 0; Q = 1The reset input (pin 4) provides a
mechanism to reset the FF in a manner which over rides the effect of any instruction coming
to FF from lower comparator.

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 Signal Conditioning and Data Acquisition Circuits -Dr.H N Suresh

Block Dia Of 555 timer

Monostable operation:

Wave forms for Monostable multivibrator

Dept. Electronics & Instrumentation , BIT, Bengaluru-04

 Signal Conditioning and Data Acquisition Circuits -Dr.H N Suresh

Initially when the output is low, i.e. the circuit is in a stable state, transistor Q1 is ON
&capacitor C is shorted to ground. The output remains low. During negative going trigger
pulse, transistor Q1 is OFF, which releases the short circuit across the external capacitor C
&drives the output high. Now the capacitor C starts charging toward Vcc through RA. When
the voltage across the capacitor equals 2/3 Vcc, upper comparator switches from low to high.
i.e.Q = 0, the transistor Q1 = OFF ; the output is high.
Since C is unclamped, voltage across it rises exponentially through R towards Vcc with a time
constant RC (fig b) as shown in below. After the time period, the upper comparator resets the
FF,i.e. Q = 1, Q1 = ON; the output is low.[i.e discharging the capacitor C to ground potential
(figc)]. The voltage across the capacitor as in fig (b) is given by

Vc = Vcc (1-e-t/RC)……. (1)

Therefore At t = T, Vc = 2/3 Vcc

2/3 Vcc = Vcc(1-e-T/RC) Or T = RC ln (1/3) Or T = 1.1RC seconds ……………. (2)

If the reset is applied Q2 = OFF, Q1 = ON, timing capacitor C immediately discharged. The
output now will be as in figure (d & e). If the reset is released output will still remain low until
a negative going trigger pulse is again applied at pin 2.

Applications of Monostable Mode of Operation:

(a) Frequency Divider:

The 555 timer as a monostable mode. It can be used as a frequency divider by adjusting the
length of the timing cycle tp with respect to the time period T of the trigger input. To use the
monostable multivibrator as a divide by 2 circuit, the timing interval tp must be a larger than
the time period of the trigger input. [Divide by 2, tp> T of the trigger]By the same concept, to
use the monostable multivibrator as a divide by 3 circuit, tp must be slightly larger than twice
the period of the input trigger signal & so on, [ divide by 3tp> 2T of trigger]

(b) Pulse width modulation: Pulse width of a carrier wave changes in accordance with the
value of a incoming (modulating signal) is known as PWM. It is basically monostable
multivibrator. A modulating signal is fed in to the control voltage (pin 5). Internally, the control

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 Signal Conditioning and Data Acquisition Circuits -Dr.H N Suresh

voltage is adjusted to 2/3 Vcc externally applied modulating signal changes the control voltage
level of upper comparator. As a result, the required to change the capacitor up to threshold
voltage level changes, giving PWM output.

The 555 timer as an Astable Multivibrator:

An Astable multivibrator, often called a free running multivibrator, is arectangular wave

generating circuit. Unlike the monostable multivibrator, this circuit does not require an external
trigger to change the state of the output, hence the name free running. However, the time during
which the output is either high or low is determined by 2 resistors and capacitors, which are
externally connected to the 55 timer.

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 Signal Conditioning and Data Acquisition Circuits -Dr.H N Suresh

Astable Multivibrator ;

Waveforms of Astable multivibrator

The above figures show the 555 timer connected as an astable multivibrator and its model
graph

Initially, when the output is high:

Capacitor C starts charging toward Vcc through RA & RB. However, as soon as voltage across
the capacitor equals 2/3 Vcc. Upper comparator triggers the FF & output switches low.

When the output becomes Low:

Capacitor C starts discharging through RB and transistor Q1, when the voltage across C equals
1/3 Vcc, lower comparator output triggers the FF & the output goes high. Then cycle repeats.
The capacitor is periodically charged & discharged between 2/3 Vcc& 1/3Vcc respectively.
The time during which the capacitor charges from 1/3 Vcc to 2/3 Vcc equal to the time the
output is high & is given by

Dept. Electronics & Instrumentation , BIT, Bengaluru-04

 Signal Conditioning and Data Acquisition Circuits -Dr.H N Suresh

tc = (RA+RB)C ln 2……………(1) Where [ln 2 = 0.69]= 0.69 (RA+RB) C

Where RA & RB are in ohms. And C is in farads.

Similarly, the time during which the capacitors discharges from 2/3 Vcc to 1/3 Vcc is equal to
the time, the output is low and is given by,

is equal to the time, the output is low and is given by, tc = RB C ln 2

waveform is td = 0.69 RB C …………………..(2) where RB is in ohms and C is in farads.

Thus the total period of the output

T = tc + td = 0.69 (RA+2RB) C …………….(3)

This, in turn, gives the frequency of oscillation as,f 0 = 1/T = 1.45/(R A+2RB)C ………(4)

Equation 4 indicates that the frequency f0 is independent of the supply voltage Vcc. Often the
term duty cycle is used in conjunction with the astable multivibrator. The duty cycle is the ratio
of the time tc during which the output is high to the total time period T. It is generally expressed
as a percentage.

% duty cycle = (tc / T )* 100

% DC = [(RA+RB)/ /(RA+2RB)] * 100

Applications of Astable Multivibrator:

FSK Generator:

The FSK generator is formed by using a 555 as an astable multivibrator whose frequency is
controlled by the state of transistor Q1. In other words, the output frequency of the FSK
generator depends on the logic state of the digital data input. One hundred and fifty hertz is one
of the standard frequencies at which the data are commonly transmitted. When the input is
logic 1, transistor Q1 is off. Under this conditions, the 555 works in its normal mood as an
astable multivibrator; that is, capacitor C1 charges through R3 and R2 to 2/3 VCC and discharge
through R2 to 1/3 VCC as long as the input is at 1 state. The frequency of the output wave form
is given by the equation

F0 = 1.45/(RA + 2RB)C = 1070 Hz

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 Signal Conditioning and Data Acquisition Circuits -Dr.H N Suresh

The Value of R1, R2, R3 are selected so that f0 represents a mark frequency (1070 Hz). On the
other hand, when the input is logic 0, Q1 is on (saturated), which in turn connect to a resistance
R1 across R3. This action reduces the charging time of the capacitor and increase the output
frequency which is given by the equation

F0 = 1.45/(RA||RC + 2RB)C = 1270 Hz

By proper selection of R1, this frequency is adjusted to equal the space frequency of 1270 Hz.
The difference between FSK signals 1070 Hz and 1270 Hz; this difference is called frequency
shift.

As shown in figure 1-1, the output of the 555 FSK generator is then applied to the 565 FSK
demodulator. Capacitive coupling is used to at the input to remove a dc level. As the signal
appears at the input of the 565, the loop locks to the input frequency and tracks it between the
two frequencies with the corresponding dc shift at the output. Resistor R 4 and capacitor C9
determine the free-running frequency of the VCO, while, C5 is a loop filter capacitor that
establishes the dynamic characteristics of the demodulator. Here C 5 must be chosen smaller
than usual to eliminate overshoot on the output pulse. A three-stage RC ladder (low-pass) filter
is used to remove the carrier component from the output. The high cutoff frequency (fH = 1/2
∏RC) of the ladder filter is chosen to be approximately halfway between the maximum keying
rate of 150 Hz and twice the input frequency, that is, approximately 2200 Hz. The output signal
of 150 Hz can be made logic compatible by connecting a voltage comparator between the
output of the ladder filter and pin 6 of the PLL. The VCO frequencies is adjusted with R 4 so
that at fIN = 1070 Hz a slightly positive voltage is obtained at the output.

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 Signal Conditioning and Data Acquisition Circuits -Dr.H N Suresh

Ppm: All the 555 astable circuits shown so far can be subjected to frequency modulation (FM)
or to pulse-position modulation (PPM) by simply feeding the modulation signal to pin 5 (which
connects to the IC’s internal divider chain); this modulation signal may be an AC signal that is
coupled to pin 5 via a blocking capacitor, as shown in Figure.

The 555’s
astable action is such that the pin 5 voltage influences the width of the mark, but not the space
part of each cycle, and thus provides both PPM and FM actions.

Phase Locked Loops: Basic Principles, Analog phase Detector/comparator, Voltage controlled
oscillator.PLL applications: Frequency Multiplication/Division, Frequency translation, FM
demodulation.

The phase-locked loop is one of the basic blocks in modern electronic systems. It is generally
used in multimedia, communication and in many other applications. There are two different
types of PLL’s – linear and nonlinear. The nonlinear is difficult and complicated to design in
the real world, but the linear control theory is well modeled in analog PLL’s. The PLL has
proved that a linear model is sufficient for most of the electronic applications.

What is a Phase-Locked Loop?

A phase-locked loop consists of a phase detector and a voltage controlled oscillator. The output
of the phase detector is the input of the voltage-controlled oscillator (VCO) and the output of
the VCO is connected to one of the inputs of a phase detector which is shown below in the
basic block diagram. When these two devices are feed to each other the loop forms. Block
Diagram and Working Principle Of PLL;

The phase-locked loop consists of a phase detector, a voltage controlled oscillator and, in
between them, a low pass filter is fixed. The input signal ‘Vi’ with an input frequency ‘Fi’ is
conceded by a phase detector. Basically the phase detector is a comparator that compares the

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 Signal Conditioning and Data Acquisition Circuits -Dr.H N Suresh

input frequency fi through the feedback frequency fo. The output of the phase detector is (fi+fo)
which is a DC voltage. The out of the phase detector, i.e., DC voltage is input to the low pass
filter (LPF); it removes the high-frequency noise and produces a steady DC level, i.e., Fi-Fo.
The Vf is also a dynamic characteristic of the PLL.

PLL Block Diagram

The output of the low pass filter, i.e., DC level is passed on to the VCO. The input signal is
directly proportional to the output frequency of the VCO (fo). The input and output frequencies
are compared and adjusted through the feedback loop until the output frequency is equal to the
input frequency. Hence, the PLL works like free running, capture, and phase lock.

When there is no input voltage applied, then it is said to be a free-running stage. As soon as the
input frequency applied to the VOC changes and produces an output frequency for comparison,
it is called a capture stage. The below figure shows the block diagram of the PLL.

Phase-Locked Loop Detector

The phase-locked loop detector compares the input frequency and the output frequency of the
VCO to produces a DC voltage which is directly proportional to the phase distinction of the
two frequencies. The analog and digital signals are used in the phase-locked loop. Most of the
monolithic PLL integrated circuits use an analog phase detector and the majority of phase
detectors are from the digital type. A double balanced mixture circuit is used commonly in
analog phase detectors.

Applications of Phase-Locked Loop

 FM demodulation networks for FM operations

 It is used in motor speed controls and tracking filters.

 It is used in frequency shifting decodes for demodulation carrier frequencies.

 It is used in time to digital converters.

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 Signal Conditioning and Data Acquisition Circuits -Dr.H N Suresh

 It is used for Jitter reduction, skew suppression, clock recovery.

VCO(Voltage Controlled Oscillator):

A Voltage controlled oscillator is an oscillator with an output signal whose output can be varied
over a range, which is controlled by the input DC voltage. It is an oscillator whose output
frequency is directly related to the voltage at its input. The oscillation frequency varies from
few hertz to hundreds of GHz. By varying the input DC voltage, the output frequency of the
signal produced is adjusted.

Types of Voltage Controlled Oscillator:

The VCOs can be categorized based on the output waveform:

 Harmonic Oscillators: The output waveform produced by harmonic oscillators is

sinusoidal. This can often referred as linear voltage controlled oscillator. The
examples are LC and Crystal oscillators.

 Relaxation Oscillators: The output waveform produced by harmonic oscillators is saw

tooth. This type can give a large range of frequency using reduced quantity of
components. Mainly it can be used in monolithic ICs

Example: IC 566

The IC 566 (or LM566) is an integrated circuit that produces a triangular wave and a square
wave output from two different output pins. It is an 8 pin IC shown below:

Pin Configuration; IC 566

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 Signal Conditioning and Data Acquisition Circuits -Dr.H N Suresh

frequency fo = (2/(R1C1))*((Vcc-Vc)/Vcc)
1. Ground

2. No connection
3. Square wave output

4. Triangular wave output

5. Modulating/Control voltage VC
6. Timing resistor R1 (connected between pin 6 to supply voltage VCC)
7. Timing capacitor C1 (connected between pin 7 to ground)

8. Supply voltage VCC

A rough internal circuit is shown below:

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 Signal Conditioning and Data Acquisition Circuits -Dr.H N Suresh

Voltage Controlled Oscillator:

Basically, the principle of operation is as such:

The Schmitt trigger switches the current source from charging and discharging the capacitor.

The IC charges and discharges the external capacitor C1 through the resistor R1. A triangular
waveform is obtained by passing the voltage waveform across the capacitor C1 through Buffer
Amplifier 2 and obtained as output through pin 4.

The voltage waveform across the capacitor when passed through a Schmitt trigger, produces a
square wave which is passed through the Buffer Amplifier 1 and obtained as output through
pin 4. Modulating voltage VC should be in the range of (3/4)Vcc < Vc < Vcc where VCC is
the supply voltage.VCC should be within 10 to 24 Volts.

The frequency modulation (by applying a varying modulating voltage VC) can be done in 10:1
ratio.The frequency of the output waveform is f0 = (2/R1C1)*((Vcc – Vc)/Vcc) .

An example circuit is shown below:

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 Signal Conditioning and Data Acquisition Circuits -Dr.H N Suresh

Voltage Controlled Oscillator

Applications of VCO

1. Tone generators

2. Frequency modulation

3. Function generator

4. Phase Locked Loop

Pll applications:
1.Frequency multiplication/Division

Multiplexing is a technique by which different analog and digital streams of transmission

can be simultaneously processed over a shared link. Multiplexing divides the high capacity
medium into low capacity logical medium which is then shared by different streams.
Communication is possible over the air radiofrequency, using a physical media cable, and light
opticalfiber. All mediums are capable of multiplexing. When multiple senders try to send over
a single medium, a device called Multiplexer divides the physical channel and allocates one to
each. On the other end of communication, a De-multiplexer receives data from a single
medium, identifies each, and sends to different receivers. Frequency Division Multiplexing

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 Signal Conditioning and Data Acquisition Circuits -Dr.H N Suresh

When the carrier is frequency, FDM is used. FDM is an analog technology. FDM divides the
spectrum or carrier bandwidth in logical channels and allocates one user to each channel. Each
user can use the channel frequency independently and has exclusive access of it. All channels
are divided in such a way that they do not overlap with each other. Channels are separated by
guard bands. Guard band is a frequency which is not used by either channel. Time Division
Multiplexing TDM is applied primarily on digital signals but can be applied on analog signals
as well. In TDM the shared channel is divided among its user by means of time slot. Each user
can transmit data within the provided time slot only. Digital signals are divided in frames,
equivalent to time slot i.e. frame of an optimal size which can be transmitted in given time slot.
TDM works in synchronized mode. Both ends, i.e. Multiplexer and De-multiplexer are timely
synchronized and both switch to next channel simultaneously. When channel A transmits its
frame at one end,the De-multiplexer provides media to channel A on the other end.As soon as
the channel A’s time slot expires, this side switches to channel B. On the other end, the De-
multiplexer works in a synchronized manner and provides media to channel B. Signals from
different channels travel the path in interleaved manner.

2. PLL FM demodulation basics

The way in which a phase locked loop, PLL FM demodulator works is relatively
straightforward. It requires no changes to the basic phase locked loop, itself, utilising the basic
operation of the loop to provide the required output. he phase locked loop, PLL is a very useful
RF building block. The PLL uses the concept of minimising the difference in phase between
two signals: a reference signal and a local oscillator to replicate the reference signal frequency.
Using this concept it is possible to use PLLs for many applications from frequency synthesizers
to FM demodulators, and signal reconstitution.

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 Signal Conditioning and Data Acquisition Circuits -Dr.H N Suresh

The PLL FM demodulator is normally considered a relatively high performance form of FM

demodulator or detector. Accordingly they are used in many FM receiver applications.

The PLL FM demodulator has a number of key advantages:

 Linearity: One of the advantages of the PLL FM demodulator is its high degree of
linearity. This is governed by the voltage to frequency characteristic of the VCO within
the phase lockedloop.Normally the phase locked loop will be able to operate over a
wide bandwidth - normally this is much wider than the bandwidth of the FM signal or
even the IF stages of the FM receiver. As the frequency deviation of the incoming FM
signal covers only a small portion of the PLL bandwidth the overall conversion is very
linear.
The VCO voltage to frequency curve is the main determining factor and this can be
made to be very linear for the range needed for FM demodulation. Distortion levels for
PLL FM demodulators are normally very low and are typically of the order of a tenth
of a percent. This makes the PLL FM demodulator a very good option for high fidelity
tuners as well as for many other applications including radio communications, etc.

 Insensitive to amplitude noise:

 Ease of incorporation into ICs:
 Manufacturing costs:

What is Frequency Translation?

The frequency translation can be defined as; it is one kind of method for transmitting a signal
from one fraction of the frequency axis to another fraction of the axis. This is frequently done
within the wireless communications system to transmit a passband signal toward baseband

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 Signal Conditioning and Data Acquisition Circuits -Dr.H N Suresh

previous to demodulation. Compound multipliers are used for performing frequency

conversion; however, a more efficient technique is to employ decimation.

Frequency Translation using PLL

The frequency shifting of an oscillator using a small factor is known as a frequency translator.
The block diagram of the frequency translator using PLL is shown below.

The block diagram can be built with a mixer, LPF, and the phase-locked loop. The fs (input
frequency which has to be transferred is applied to the mixer. Other i/p of the mixer is the o/p
voltage of VCO that is fo. As a result, the o/p of the mixer includes the difference signal and
sum (fo ± fs). The LPF which is connected to the mixer’s o/p discards the (fo +fs) signal &
provides the signal like (f0 – fs) at the o/p. The signal like (fo – fs) can be applied toward the
phase detector. The offset frequency f1 is i/p of the detector. In the locked mode, the o/p
frequency of VCO can be regulated to make 2- input frequencies of phase detector equivalent.

This gives,

f0-fs = f1 & f0 = fs +f1

By regulating f1 (offset frequency) can move the oscillator’s frequency to the preferred value.

Applications:

 The applications of frequency translation mainly include within the context of the parts
like QF4A512 & QF1D512.

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 Signal Conditioning and Data Acquisition Circuits -Dr.H N Suresh

 The interest signal moving is nearer to DC so that the filter’s 512 taps are more efficient.
The signal of interest moving under the highest operating frequency of the parts

 The applications of frequency translation mainly include conversion of frequency up,

frequency down, improved signal reception, and combined down change, groupings,
etc.

 This is all about frequency translation which can be used to transfer a form of signal
from one portion of the frequency axis to other one portion of the frequency axis. This
translation mainly happens often within a wireless communication system. This
translation can be used for transferring the signal from passband to baseband. For this,
the most efficient technique is decimation.

Exam questions:
1. With a neat functional diagram, explain the working of 555 timer as monostable
multivibrator and derive an expression for the frequency oscillation with relevant wave
2. Define capture range and lock range. Explain the process of capturing the lock and also
derive for capture range and lock range.
3. Describe Monostable multivibrator with necessary diagrams and derive for ON time
and recovery time.
4. What are the applications of PLL for the AM detection?
5. Mention two applications of analog multiplier.
6. A 555 timer is configured in actable mode with RA = 2 k ohm RB = 6 k ohm and C =
0.1 μF. Determine the frequency of oscillation.
7. Discuss the principle of operation of NE 565 PLL circuit (ii) How can PLL be modeled
as a frequency multiplier?
8. Draw the circuit diagram of a PLL circuit using as a FM detector.
9. Design a monostable multivibrator using 555 time for a pluse period of 2 ms
10. With block schematic explain the working principle of PLL IC NE 565. (12) (ii) Brief the
application of PLL IC for frequency multiplication.(Repeated)

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 Signal Conditioning and Data Acquisition Circuits -Dr.H N Suresh

Dept. Electronics & Instrumentation , BIT, Bengaluru-04