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An Overview of Hybrid DC-DC Converters:

From Seeds to Leaves
Yan Lu, Senior Member, IEEE, Junwei Huang, Student Member, IEEE, Zhiguo Tong, Student Member,
IEEE, Tingxu Hu, Student Member, IEEE, Wen-Liang Zeng, Member, IEEE, Mo Huang, Senior
Member, IEEE, Xiangyu Mao, Member, IEEE, and Guigang Cai, Member, IEEE

Abstract: With the surging demands for higher current at sub-1V supply level in high performance digital systems, high-efficiency
and high-current-density power converters are essential for system integration. Higher voltage supply buses are emerging for high
current applications to reduce the IR losses on the power delivery networks. Thus, there is a wide voltage gap between the power
bus and the digital supply rails at the point-of-load (PoL). Meanwhile, battery-powered portable or wearable devices favor
extremely high-power-density solutions, calling for novel power conversion topologies, which has been the hottest topic in the
power management IC area in the past decade. This paper reviews the switched-capacitor-inductor (SCI) hybrid DC-DC buck
converters from the topology “seeds” to their “leaves”. Here, we define six seeds, they are: 1) three-level buck, 2) double-step
down buck, 3) inductor-first buck, 4) always-dual-path buck, 5) buck-buck, 6) multiple-output hybrid buck. We try to analyze and
summarize their pros and cons, and to derive the evolution of the hybrid DC-DC converters, with milestone examples. Then, we
share our observations, design intuitions and suggestions to help the researchers and engineers to pick up and design a new SCI
hybrid DC-DC converter.

Index Terms—Buck converter, buck-boost, DC-DC conversion, hybrid converter topology, integrated voltage regulator, multi-level,
multiple-output, multi-phase, switched-capacitor converter, 3D power delivery for chiplet.

much about the solution size, for example the data centers
and high-performance computing (HPC), power conversion
I. INTRODUCTION1 efficiency is the first priority [3]. For applications that need
to be extremely compact and miniaturized, like the wearable
S WITCHING mode power converter plays a more and more
important role in both high-performance computing and
extremely-compact portable device applications. To reduce
and portable devices, power density would be more
important. In particular, for drones and micro flying robots,
the IR losses on the power delivery networks, conventional the weight of a solution is a prioritized requirement,
12V power bus on board has been elevated to 48V, while the demanding for what we define here as “flyweight” power
digital loads dive into sub-1V region [1], [2], as shown in Fig. conversion solutions. Therefore, according to the target
1. Thus, there is a wide voltage gap between the power bus applications, we may define the power density with a unit of
and the digital supply rails at the point-of-load (PoL), calling Watt per unit volume or Watt per unit weight. For HPC and
for new system structures and novel DC-DC topologies. chip-scale solutions, the maximum current instead of
Fig. 2 shows the requirements of hybrid DC-DC converter maximum power is more straight forward to represent the
for different applications. Both high efficiency and power delivery bottleneck. Thus, current density is also a
high-power density are two key specifications for DC-DC popular metric.
converters. For high-current applications that do not care too The performances of highly-integrated power converters
heavily depend on both the figure-of-merit (FoM) of active
devices and the quality factors of passive components
Manuscript received 10 August 2023; revised 10 October 2023 …
(especially the inductor). As the size and quality factor of an
This work is supported by the National Natural Science Foundation of inductor are limited by physical constraints, and a large
China under Grant 62122001 and by the Macao Science and Technology inductance can only be obtained with multiple turns of
Development Fund (FDCT) under 0023/2022/A1 and 0103/2022/AFJ.
(Corresponding author: Yan Lu)
winding, thus, a high-current power inductor would be bulky
Yan Lu, Junwei Huang, Zhiguo Tong, Tingxu Hu, Wen-Liang Zeng, Mo and costly. On the other hand, the energy density of a
Huang, Xiangyu Mao, and Guigang Cai are with the State Key Laboratory capacitor increases naturally with advanced processes [4].
of Analog and Mixed-Signal VLSI, Institute of Microelectronics, and
FST-DECE, University of Macau, Macao, China. (e-mail:
Thus, switched-capacitor-inductor (SCI) hybrid DC-DC
[email protected]) converter becomes a popular choice. Nonetheless, we should
find an optimum way to divide the voltages and guide the
currents, and to deliver the power to the load.

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VIN IOUT VIN

Conventional
48V Bus Buck IOUT

4-Cell Battery

DC-DC Converters
L1
VOUT
12V Bus VX VIN/2 L1
VOUT
3-Cell Battery VX
CL
VIN/2
2-Cell Battery CL
5V Bus Buck with
Stacked
1-Cell Battery Transistors
VIN

3.3V/2.5V/1.8V
to sub-1V
IOUT
Fig. 1. Application scenarios of hybrid DC-DC converter for XPUs. 3-Level VIN
Buck
L1 IOUT
Efficiency CF1 CF2 VOUT
VX
Conversion 2VIN/3 VIN/3
Density CF L1
Ratio CL VOUT
VX
VIN/2
Datacenter
CL
Wearable FCML
Buck
Flyweight

Weight Scalability
Fig. 3. Conventional buck with single or stacked-MOSFET, 3-level buck,
Technology Flexibility and flying capacitor multi-level (FCML) buck converters.
Fig. 2. Requirements of hybrid DC-DC converter for different applications. section: 1) three-level buck, 2) double-step down buck, 3)
inductor-first buck, 4) always-dual-path buck, 5) buck-buck,
To bridge this gap with a large voltage conversion ratio
6) multiple-output hybrid buck converter. The six “seeds”
(VCR) DC-DC converter, several research groups proposed
are somewhat related in a development path.
many innovative topologies and a lot of efficient operation
schemes [5], and summarized design guidelines [6]. The A. Three-Level Buck
basic idea of an SCI hybrid DC-DC converter is to use Fig. 3 shows the evolution from a simple conventional
switched-capacitor (SC) cells to reduce the voltage swing on buck to stacked-transistor buck, and from 3-level buck [7] to
the power inductor such that a smaller inductor can be used. flying capacitor multi-level (FCML) buck converters [8]. It
On the other hand, it also brings the drawback of slow is proven that stacked low-voltage (LV) transistors would
transient response as the inductor current slew rate also have considerably better FoM of RONQG than a single
becomes smaller. When an SC path is in-parallel with the high-voltage (HV) transistor when they are dealing with the
power inductor, it can share the current stress on the inductor, same voltage stress [9], where RON and QG are the
and may also provide fast transient output current, as the on-resistance and gate charge of the switch, respectively.
hard charging current only depends on the drain-source Besides the good switching characteristics, it allows the
voltage (VDS) of the switches. power switch to be implemented with standard and advanced
In this paper, we review and analyze the hybrid DC-DC logic devices, which avoids the cost of extra processing steps
buck converters from the topology “seeds” to their “leaves”. for HV devices; and excellent switching characteristics also
In the following section II, we introduce the existing hybrid leads to a reduced chip size [9].
converters in six categories, based on their fundamental When the input-output voltage gap is large, a conventional
ideas. Also, we try to analyze and summarize their pros and buck would have large voltage swing on the power inductor,
cons, and to derive the evolution process of the hybrid resulting in large current ripple. Then, it is natural to add a
DC-DC converters, with milestone examples. Then, in flying capacitor CF between the stacked transistors to obtain
Section III, we share our topology summary, observations, a 3-level converter with reduced inductor voltage swing.
design intuitions and suggestions for new/suitable topologies. With more stacked transistors and more flying capacitors,
In Section IV, we give our design steps and considerations to we will get an FCML buck converter, allowing us to use a
help the researchers and engineers to pick up the SCI hybrid much smaller inductance.
DC-DC converters for future works. Finally, we draw However, there are two critical issues associated with the
conclusions in Section V. FCML buck. First, all the output current, which is the largest
current in a step-down converter, would flow through the
II. TOPOLOGY SEEDS TO LEAVES power inductor, generating large I2R conductions loss on the
To better understand various hybrid DC-DC converters, inductor. Second, as the FCML is “series-series” operation
we define and discuss six “seeds” and their “leaves” in this for the SC network, the largest current would also flow

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VIN VIN DSD Buck [18] CCC Buck [21]

L1 VIN/2 L1 CF1 L1
VOUT VX1 VOUT VX1
CL
Any SC + CL
Converter Inductor VOUT
VIN

VX2 L2
CL
VIN VIN VX VOUT
VX2
CF2 L2
2VIN CF1 VIN/2 CL
VX = VIN
0 Fig. 5. The DSD topology and capacitor cross-connected (CCC) topology.
L1 CF2 VIN/2
CF VOUT
VIN VX DSD Buck with CCC Buck with
3VIN/2
CL VIN Transient Enhancement Transient Enhancement,
VX = VIN Switch [23] VCR Extension and DCM [20], [21]
VIN/2 VIN/2
VX1 L1 VX1
VOUT
3-Level Buck-Boost with
Buck-Boost 1/2 and 3/2 VIN Levels S1 CF1
S3 L1
[15] [16] CL S5
VOUT
VIN
Fig. 4. Three-level buck-boost converters, and the concept of any SC
S6
converter with post-stage inductor topology. VX2 S4 L2
S2 CF2 CL
through all the switches and the flying capacitors. More L2 VX2
importantly, usually all the power switches are integrated on
a single chip while the flying capacitors are off-chip, which Fig. 6. The DSD buck with transient enhancement switch, and CCC buck
means the largest current would flow in and out of the chip with transient enhancement and VCR extension.
multiple times, generating large additional conduction losses
on the I/O pads, bonding wires, routes, and contacts. inductors would be used to share the high output current [17].
Three-level and FCML bucks need additional control loop Combining the 2:1 SC converter and two-phase buck
for the flying capacitor voltage VCF balancing. Because the topologies, the double-step down (DSD) buck topology is a
capacitor currents are defined by the power inductor, when minimalist design [18]. Then, it becomes a popular product
the switching phase durations and component values have for server and laptop applications.
mismatches and variations, the capacitor voltage will shift Fig. 5 shows the DSD topology and its variant capacitor
from its ideal value, and may generate unwanted voltage cross-connected (CCC) or namely symmetrical DSD
stress on the switches. A dual-branch 3-level converter with topology [19]-[21]. A DSD converter has an intrinsic rough
cross-connected flying capacitors can solve this balancing current balance between the two inductor branches, because
issue without additional control loop [10]. the flying capacitor follows charge balance in steady state.
Another advantage of an FCML buck is its wide output But the capacitor charge balance does not necessarily mean
range. But, for most of the applications mentioned in this inductor current balance, when duty cycle or component
paper, we only need a large VCR, not a wide output range. mismatch happens, the two branches would still have certain
Therefore, we may simplify the operation states or modify current mismatch [22].
the SC topology for a higher efficiency. There is a tradeoff between inductor current ripple and
As shown in Fig. 4, with the 3-level converter as the transient response. For smaller current ripple, we use hybrid
“seed”, we can integrate any switched-capacitor block with a topology to reduce the inductor voltage swing, but it also
post-stage inductor for voltage regulation. For example, [11] reduces the inductor current slew rate during load transient.
and [12] incorporate traditional Dickson converter into Meanwhile, a conventional DSD converter cannot energize
hybrid solutions. [13] cascaded two SC stages to further its two inductors at the same time, otherwise, one low-side
reduce the input voltage. switch will see the high voltage VIN, doubling its voltage
Similarly, besides the step-down conversion, there are rating. Therefore, conventional DSD converter has a severe
also structures implemented to boost or step-up/step-down drawback of slower transient response speed.
the input voltage to implement boost [14] or buck-boost To address this issue, as shown in Fig. 6, additional
hybrid converters [15], [16], also shown in Fig. 4. In this way, transient enhancement switches can be added for energizing
the right-half-plane (RHP) zero in traditional boost and the two power inductors at the same time [23], while the
buck-boost converters is eliminated. Nonetheless, the CCC converter can have additional operation state for fast
efficiency would be degraded if the additional switches let energizing the inductors [21]. Also, we proposed in [21] to
the existing switches see a higher voltage, because then they compare the transient performance of the DSD and CCC
need to use higher voltage rating devices. works using the normalized output undershoot with respect
to the theoretical minimum undershoot of the conventional
B. Double-Step Down Buck DSD converter. With D > 0.5 operation state in [21], we
When the application desires higher current, two or more obtained a normalized undershoot value of only 0.73.

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 This article has been accepted for publication in IEEE Open Journal of the Solid-State Circuits Society. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/OJSSCS.2023.3334228

Tri-State DSD Buck [25] VIN Passive Stacked 3rd-Order Buck [34]
VIN
VX1 VOUT L1 IL1 IOUT = IL1 + IL2
VIN/4 S1 D
L1 I
CF1 VX1
CL VCF= VOUT ΔIOUT
VIN/2 L2
VX2 CF VOUT/D
CL IL2
VX2
3-Level Topology S2 1-D 0 IL1 t
@ Different FSW
L2 IL2 High current ripple, no cancellation.
CF2 Ladder + DSD Buck [26] (a) DC levels of IL1 and IL2 varies with D.

2VIN/5
VIN S1 S2 S3 S4 CF4 VX1 L1 VIN Inductor-First Inductor-on-Ground
VOUT
Switched-Capacitor (L2SC) Buck [35]
VIN/5 IL1
S7 L1 VOUT < VIN/3
S5 S1 S2
CL IOUT = IL1 + IL2 + ICF1,2
CF1 CF3 L2 VX1
VX2 I
2VIN/5 2VIN/5 CF2
Merged Switches S3 VOUT ΔIOUT
S6
VCF Self-Balanced CF1 VX2
IL2
Fig. 7. Examples with more switches and capacitors merged with the DSD. L2 CL
IL2 IL1 t
0
S4
VIN Inductor-First VIN L1
Buck [31] VX S6 Interleaved inductor current ripples.
L1 3VOUT Reduced inductor current by CF1,2.
S5 S5
S1 Inductor-First CL3 (b) DC levels of IL1 and IL2 varies with D.
VX with USB Cable S4
2VOUT
VOUT [33] 3V Fig. 9. The topologies with inductor-on-ground.
VOUT OUT CL2
CF S3
CL C F1
CF2 VOUT high-voltage stage require large volume and cost. Thus,
S2
S3 VOUT placing the inductor at the input side of a buck converter
VX switches >VIN for inductor S2
S1 CL1 allows it to operate with input (lower) current and to block
voltage-second balance.
(a) (b) high input voltage. In addition, the inductor-first topology
would have a continuous input current which significantly
Fig. 8. The inductor-first topologies: (a) with one flying capacitor, and (b)
with a more complex SC network for more outputs and wider VCR. reduces or eliminates the need for input capacitors.
Moreover, the continuous input current feature is favorable
Notice that the additional state for CCC buck can also help for electromagnetic interference (EMI) considerations.
to extend its VCR range from sub-1/4 to sub-1/3, as Consider the power inductor is followed by an SC
discussed in [20]. And also, we find that it enables the CCC network, the inductor voltage swing on the SC side will be an
to operation in discontinuous conduction mode (DCM) integer multiple of VOUT. When there is only one flying
without reverse inductor current. Because S3 and S4 can be capacitor, the maximum voltage on the SC terminal for the
both off during this state, then, both inductors can be inductor can only reach up to 2VOUT. As the switched
energized from zero current. inductor follows voltage-second balance in steady state, the
Fig. 7 shows some representative examples. To further simple inductor-first structure in [32] is limited to a voltage
extend the VCR, more switches and capacitors can be conversion ratio of VOUT/VIN = 1/(2−D), where D is the duty
employed in front of the DSD topology [24]-[27]. The high cycle. In other words, VIN < 2VOUT, which restricts its
voltage pre-stage may have a different switching frequency application in many scenarios.
FSW with the post-stage DSD [25]. An SC ladder topology is There are two main directions for the topology
merged with DSD in [26]. To deliver higher output current, improvement. The first one aims to increase the VCR and
the topology can be equipped with more inductors [18], overall performances of the inductor-first structure. To
[28]-[30]. We will come back to this topic in the topology increase the VCR, we need to add more flying capacitors to
summary section. step-down the output voltage. As shown in Fig. 8(b), the
work in [33] obtains a maximum VCR of 1/3 with multiple
C. Inductor-First Buck
capacitors and a complex SC network.
As depicted in Fig. 8, different from the traditional buck, The key to increase the VCR is to boost the voltage on the
an inductor-first structure swaps the positions of the inductor flying capacitors instead of using too many capacitors. As
and the switched-capacitor network [31]-[33]. In another shown in Fig. 9, the inductor-on-ground cell breaks the
way around, when reverse operating the inductor-first buck voltage tie between VOUT and VCF, allowing the flying
in [31], it becomes the KY boost converter in [14]. capacitor to have a higher voltage. Now, VCF = VOUT/D,
For the passive components, the DC resistance (DCR) of which can be adjusted by duty-cycle control.
the inductor is one of the main sources of power loss. On the The passive-stacked 3rd-order buck (PS3B) in [34] utilizes
other hand, capacitors have DC-value derating versus its the inductor-on-ground cell to obtain a VCR of D and to
stored voltage, which means that the capacitors used in have two inductors sharing the output current. Also, it

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 This article has been accepted for publication in IEEE Open Journal of the Solid-State Circuits Society. This is the author's version which has not been fully edited and
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Bidirectional Buck [36] Inductor-First Buck-Boost [37] Dual-Path Buck

L1 S5 S1 L1 S1 VIN D VOUT
VIN VIN VX VOUT = VIN·D/(1+D)
VOUT VOUT CF VOUT CL [38]
CF CF APEC
S4 S2 1-D L1
CL CL
Forward Mode: S4 S2
Inductor-First Buck S3 S3 Always-Dual-Path Bucks with One Inductor and Two Capacitors
Reverse Mode: L1
3-Level Buck VIN VOUT VIN VOUT
(a) (b)
Fig. 10. Convert the inductor-first buck into (a) a buck-boost converter, or CF1 CL CF1 CL
(b) a reconfigurable bidirectional buck converter. CF2 L1 CF2

ensures continuous input, ground, and output currents. [39] [40]

However, this structure suffers from large current ripples APEC VLSIC
because both inductor currents rise or fall simultaneously.
And, when D deviates from 0.5, the current distribution VIN VOUT VIN VOUT
between the two inductors becomes uneven, leading to CF2
increased conduction losses. CF1 CL CF1 CL
CF2
We proposed in [35] an inductor-first inductor-on-ground
switched-capacitor (L2SC) multi-path hybrid DC-DC L1 L1 [42]
[41]
converter. The two inductors and two flying capacitors ISSCC TCAS-I
operate with interleaved charging and discharging states, Fig. 11. The dual-path and always-dual-path hybrid converters.
significantly reduced the current ripple at light load.
VIN VCR = D/(2+2D)
Furthermore, it introduces a parallel capacitor path to reduce
Small Inductor Current
the current flowing through the inductors, advancing the CF1 L1 Inherent Current Balancing
efficiency and power density tradeoff. CF0 Small Switch Voltage Stresses
The second direction involves reconstruction of the VOUT
inductor-first topology for specific applications that require CL
flexible VCRs [36], [37]. As depicted in Fig. 10, our work in CF2 L2
[45]
[36] proposed a reconfigurable bidirectional buck converter, ISSCC
reusing the USB cable as a power inductor. This Fig. 12. The dual-inductor quad-path hybrid DC-DC converter.
reconfigurable structure combines the inductor-first
operation for the forward mode and a three-level buck series-parallel SC or modified series-parallel SC converter
operation for the reverse mode. Based on the inductor-first [44]. For [39], due to the absence of a path directly to ground
buck, [37] proposed a buck-boost converter with always for the inductor, the VCR is limited to >1/3, making it
reduced conduction loss, by adding a switch in parallel with unsuitable for wide voltage gap applications. In [40], the
the inductor. Moreover, this hybrid buck-boost converter has VCR is <1/2, with the inductor connects to ground in certain
always only one switch conducting on the main current paths, one or two phases. In [41] and [42], the VCR can be <1/3
achieving outstanding efficiency even with a tiny power with reduced voltage swing across the inductor.
inductor. This topology also belongs to the category of However, for ADP converters with only one inductor,
always-dual-path converter that to be discussed next. there will be a capacitive current path in both phases. Then,
there is a general issue. When the duty cycle largely deviates
D. Always-Dual-Path Buck
from 0.5, one phase will have obviously shorter duration,
Another way to reduce the inductor current is to have a squeezing the hard charging time. Then, there will be large
parallel SC path to share the current [38]. In general, a current spikes and thus large root-mean-square current IRMS
capacitor has higher energy density compared to an inductor, for the shorter phase, generate larger output ripple and EMI,
and the capacitor energy density improves proportionally and degrade the efficiency.
with the technology, while that of an inductor is limited by Combining the concepts of dual-path and DSD structures,
physical space constrains. Meanwhile, for space-constrained we arrive at the solution of dual-inductor quad-path buck
application scenarios, designers would like to have a topology [45], as shown in Fig. 12. It has a large VCR of
small-volume power inductor, which would have higher D/(2+2D), small inductor currents, small voltage stress of
DCR and thus larger conductions loss. VIN/2−VOUT on half of the switches. Like the DSD buck, the
Fig. 11 shows the dual-path [38] and the state-of-the-art inductors have inherently current balancing as CF0 would
always-dual-path (ADP) converters. A switched-capacitor charge and discharge equally during steady state. Moreover,
parallel path operates in either hard-charging mode [39]-[42] the above-mentioned hard charging current spike issue can
or soft-charging mode [43] would help to improve the be significantly alleviated, as the CF1 and CF2 discharging
efficiency, power density, and transient response at the same duration has been considerably extended in this topology,
time. Basically, all the ADP examples in Fig. 11 are based on allowing the use of smaller switches for the capacitor charge

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 This article has been accepted for publication in IEEE Open Journal of the Solid-State Circuits Society. This is the author's version which has not been fully edited and
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VIN VIN CDC1 CDC2

Superimposed
3-Level + Inductor-First
Quadratic Buck
[46] ISSCC
D [47] APEC
VIN
CF1 L1 L1
VX2 VX2
VIN/2 VX1
VX1 VO4
VO3
CF2 CF1 CF2 L1
VOUT VOUT VO2
DVIN CF VO1
VOUT
CL L2 CL Quad-Output Switched-Capacitor Buck
[55] ISSCC
VX3
VCR = VCR1 X VCR2 VCR = D2
(a) (b) CF1 L1
VIN VX1 Multi-Inductor
VO1
Fig. 13. Merged buck-buck converters: (a) 3-level converter merged with Multi-Output
inductor-first converter, and (b) a buck merged with PS3B converter. CL1
Hybrid Converter
CF2 L2 [56] APEC
VX2
VIN 3-Level SIMO VIN Dual-Output DSD Buck VO2
[53] ISSCC [54] ISSCC
CL2
VO1 VX1 L1
VO1 L3 POUT of the 3 outputs are
VX3 correlated due to
CL1 CF VO3
L1 capacitor charge balancing.
CL1 CL3
CF
VX1 VO2

VX2 L2 Fig. 15. (a) Quad-output hybrid converter with shared DC capacitors, and
CL2 VO2
(b) multiple-output hybrid converter with shared flying capacitors.
VO3
CL2
CL3 With the hybrid conversion concept and sharing the flying
(a) (b)
capacitor or intermediate filtering capacitors, a couple of
Fig. 14. Multiple-output hybrid DC-DC converters: (a) 3-level converter multiple-output hybrid DC-DC converters were proposed
with multiple outputs, and (b) DSD converter with dual outputs.
recently [53]-[56]. We draw examples in Figures 14 and 15.
With a three-level conversion in the front stage [53], as
transfer. DCM operation has also been demonstrated in [45]
shown in Fig. 14(a), the power inductor would have smaller
with good efficiency as well.
current ripple, the power switches enjoyed the benefits of
E. Buck-Buck Converter advanced CMOS process, and the flying capacitor is shared
The power inductor can also be placed in the middle of the among those three outputs. Also, the three-level operation
hybrid converter. As shown in Fig. 13(a), an interesting idea does not slow down the transient response, as it can still
is to merge a conventional buck with an inductor-first buck, provide high voltage swing to the power inductor during
sharing one inductor, namely single-inductor multi-stage transients, obtaining small cross regulation.
buck converter [46]. Or, the work [47] in Fig. 13(b) uses two On the other hand, similar to the three-level conversion,
inductors, one in the middle, one on the ground, to extend the the DSD conversion also reduces the inductor current ripple.
VCR as the superimposed quadratic buck converter. Since Meanwhile, it has two relatively small power inductors,
the “seed” idea is to merge two buck converters, its VCR capable of delivering higher output current. In [54], as
equals to the product of those of the two cascaded stages, we shown in Fig. 14(b), four extra low-voltage switches were
may call this kind of converters as buck-buck converter. added to direct the two inductor currents to two independent
Similar to the inductor-first buck, putting the inductor in outputs, obtaining a two-inductor two-output solution with
the middle can also reduce certain inductor current compared one shared CF. To balance the CF voltage and to further
to a conventional buck. The inductor in the middle can also alleviate the cross regulation, [54] used a timing balance
separate the switching frequencies on its two sides. The high mechanism and a hybrid sum and deviation technique.
side using high-voltage devices can use a lower FSW. Nonetheless, both the above works added extra power
switches on the high-current paths, like all the conventional
F. Multiple-Output Hybrid Buck single-inductor multiple-output converters did, adding extra
When it comes down to multi-core application, per-core conduction losses as well.
individual power supply has been proven to be an energy In the other way around, the two pioneering works, shown
saving system approach [48], [49]. Prior multiple-output in Fig. 15, employ multiple converters, and try to share some
designs mainly focused on how to effectively reuse a single of their capacitors for multiple outputs, thus, to arrive at a
power inductor for multiple outputs [50]-[52]. However, higher overall power density and efficiency [55], [56].
they are only suitable for low-power applications. When it Notice that the DC capacitors in [55] do not participate in
comes to high output current XPU applications, a single energy transfer like the flying capacitor does. On the other
power inductor can hardly handle such high current at tens of hand, the shared flying capacitors in [56] need to have
Amperes level for multiple outputs. charge balance in steady state, and thus the output power of

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 This article has been accepted for publication in IEEE Open Journal of the Solid-State Circuits Society. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/OJSSCS.2023.3334228

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VIN VOUT VOUT VIN

VCF = VOUT
VOUT

The First Choice of Low-Side The First Choice of High-Side

VIN VOUT VIN VOUT

VOUT VIN VOUT
VCF = VOUT VCF = VOUT

VIN VOUT VIN VOUT

VCF = VIN-VOUT VCF = VIN-VOUT

The First Choice of The First Choice of
Dual-Branch Buck Dual-Branch Hybrid Buck
Fig. 16. Turn the 2:1 SC converter into hybrid converters by replacing any
one of the switches with an inductor. VOUT
VIN VIN

C4 C3 C2 C1

VIN
VOUT
(a) Ladder
CL3 CL2 CL1 VOUT
CL
The First Choice of
Two Fly Capacitors
VIN VOUT
Fig. 18. The basic circuit cells and building blocks for a hybrid converter.
C4 C3 C2 C1 CL
converter! Furthermore, we can also replace two switches
with two power inductors [24], [34], [35]. Again, a new
hybrid converter!!
(b) Dickson But, with two or more inductors, we should not establish a
VOUT
state with two inductors in series which will generate
unwanted energy loss, similar to the charge redistribution
VIN CL loss when two capacitors connect in parallel. And of course,
circuit designers still need to analyze the voltage conversion
C4 C3 C2 C1
(c) Series-Parallel
ratio, small-signal transfer function, switch voltage stresses
and inductor current stresses of the new hybrid converter.
Although some SC converters could be very complicated
with many switches and capacitors, eventually, only a
VIN VOUT handful of topologies would make sense and be suitable for a
targeted application.
C3 C2 C1 CL
Fig. 17 shows the classic SC converters of ladder, Dickson
[58], series-parallel, and Fibonacci converters, and how prior
(d) Fibonacci arts turned them into hybrid converters [24], [26]-[30]. As
these hybrid converters are originated from the classic SC
Fig. 17. Transforming the classic SC converters into hybrid converters: (a)
ladder, (b) Dickson, (c) series-parallel, and (d) Fibonacci. topologies, they will most likely inherit the pros and cons of
these SC topologies, which means we should revisit the
the 3 outputs are highly correlated. Also, similar to analyses and comparison of these SC topologies. The total
single-output hybrid converters, it will suffer from load V·A metric of the switches, which is the sum of the products
transient response issues. of the switch voltage and current stresses, can be used to
evaluate the switch utilization of the power converters [59].
III. TOPOLOGY SUMMARY Now, with the routes shown in Fig. 18, let us discuss what
would be the favorable basic circuit cells and building blocks
From the discussions above, we can find a simple way to
for an SCI hybrid DC-DC converter [6].
invent or re-invent a new hybrid DC-DC topology [6]. With
the examples shown in Fig. 16, we find that we can obtain a A. A Good Low-Side Switch
new (but not necessarily new) hybrid converter by replacing For large voltage conversion ratio step-down DC-DC
any one of the switches in an SC converter with a power conversion, when one side of the power inductor connects to
inductor [57]. The embedded power inductor can be on the the output node, the other side would usually be switched to
input side, or the output side, or in the middle of the topology the ground for most of the time. Therefore, the circuit cell
[39]-[42]. Then, the SC converter becomes a hybrid with a single switch that connects the power inductor to the

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 This article has been accepted for publication in IEEE Open Journal of the Solid-State Circuits Society. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/OJSSCS.2023.3334228

transient response with reduced inductor voltage swing) of

Cai, ISSCC 2023
Yang, ISSCC 2023
hybrid DC-DC converters. Third, hard charging provides
Hu, ISSCC 2023
automatic CF voltage balancing, thus, simplifies the control
Zeng, ISSCC 2023
Wei, ISSCC 2020 loop design [10].
Hu, ISSCC 2022 TI, TPS54A20 D. Resonant SC Operation Helps the Efficiency
In a resonant switched-capacitor operation, the resonant
inductor shapes its current waveform into quasi-sinusoidal,
[65]
[21] reducing the RMS current of the switches when conducting
[25] the same average current in the slow-switching limit (SSL)
[43]
[45] region [63]. To deliver the same amount of power, resonant
[55] SC can operate at a lower frequency when compared to an
[60]
SC converter [43], [64]. On the other hand, the resonant
inductor also limits the instant output current, and its DCR
adds conduction loss. Usually, the value of a resonant
Fig. 19. Key performance comparison of recent 12V step-down hybrid
DC-DC converters.
inductor is much smaller than that of the power inductor in a
typical buck converter, so its DCR can be negligible. Overall,
ground is a must-have for high efficiency. Meanwhile, resonant SC operation would help to improve the peak
transistor stacking technique can be easily applied here to power conversion efficiency, but would not improve the
withhold high voltage stress with two or more low-voltage efficiency and power density tradeoff.
transistors, improves the FoM of the switches [8].
E. High Current, Multiple Paths, Multiple Inductors
B. Series Capacitor(s) on the High-Side In the past two decades, single-inductor multiple-output
Series capacitor(s) on the high-side is for reducing the DC-DC converter has also been a very popular research
power inductor voltage stress [43]. For a very large VCR, topic. However, when it comes to high current applications,
multiple capacitors may be involved. Therefore, from the the high current stress on the power inductor forces people to
topology selection perspective, the high-side part has the use multiple inductors. In the past year, a few multi-output
most variations [60], [61]. converters with multiple inductors have been proposed for
There are several considerations in selecting the high-side high current applications [54]-[56].
series capacitor topology. One major concern is the voltage
F. Performance Comparison and FoM
ratings of the capacitor(s) and the switches. High-voltage
capacitor has much less energy density while connecting two Fig. 19 compares the power conversion efficiency and the
or more capacitors in series also results in smaller equivalent current density of recent highly-integrated hybrid DC-DC
capacitance. As the voltage ratings of the capacitors and converters with 12 V input and 1.0V to 1.2V output. Here,
switches are technology process dependent, and only has the hybrid converter volume includes the inductors and
limited selections, the high-side series capacitor topology flying capacitors. The recent works obtained good peak
design is highly related to the available component voltage efficiencies for the 12V-to-1V application, while the DSD
ratings. Bootstrap circuit and intermediate voltage rail product [65] still holds the highest current density but only
designs are also very important for reducing the silicon area for 12V-to-1.2V (not to 1V) conversion. Since the SCI
and optimizing the switching losses [21]. hybrid DC-DC converters involve much more parameters
than the conventional converters, it is hard to have a fair and
C. Switched-Capacitor Hard Charging comprehensive comparison between different topologies. To
When two capacitors with different voltages exchange better evaluate the highly-integrated hybrid converters, we
charges in an SC converter, a high peak initial current would proposed in [62] an FoM of hybrid DC-DC converters as:
happen, diminishing the benefit of smaller RON of the J  VIN
FoM = , (1)
switches. Conventionally, hard charging is considered as a (1 −  )  VOUT
disadvantage, as it is the root cause for the inherent charge
where η is the peak efficiency and J is the current density at
redistribution loss of an SC converter. However, hard
peak efficiency. Here, a large VCR, high current density, and
charging has three advantages. First, hard charging provides
high efficiency result in a better FoM.
large output current to the load, as there is no current limiting
component (inductor) on the current path. As capacitors
IV. DESIGN CONSIDERATIONS
generally have larger energy storage density compared to
inductors, we can have large capacitance to reduce the dV on As we mentioned in the introduction part, although we
the capacitors and to mitigate the hard charging loss [40]. ultimately would like to have a “perfect” (high efficiency,
Second, hard charging provides instant response to output high power density, high current, large VCR, flexible and
voltage change [62]. When output voltage drops, the SC scalable) solution, different applications would have slightly
instant output current increases proportional to the VDS of the different focuses on the above-mentioned specifications.
power switches, alleviating the shortcoming (slower When we are designing converters for server rack and

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Fig. 20. Hybrid DC-DC conversion for 3D power delivery.

high-performance computing, efficiency is the priority. For

portable device, robots, drones: volume and weight are more
of concern.
Fig.21. Multiple aspects of hybrid power management solution for hitting
For a larger voltage conversion ratio, multi-stage SC the advanced power delivery target.
would be favorable. Meanwhile, for multi-stage step-down
conversion, the pre-stage would process higher voltage but Eventually, an SC power converter grid may be formed with
lower current, while the post-stage would deal with lower 3D packaging and miniaturized passives [73].
voltage but higher current. In order to reduce the passive In terms of topology and inductor selections, first of all,
component sizes and to obtain fast transient responses, a we would love to have high-Q inductor in all cases. But for
higher switching frequency would be essential, on the other the highly-integrated compact solutions, only miniaturized
hand, that would decrease the efficiency. Thus, a multi-stage inductor with high DCR can be used. Then, we can choose
converter should take the advantages of multiple device the capacitor parallel inductor dual-path topologies to reduce
voltage ratings and advanced packaging technology. The the average inductor current [41], [43], [45]. For board-level
pre-stage board-level converters use high-voltage devices design, the DSD family, including CCC [21] and quad-step
and high-Q inductors and operate at lower FSW of hundreds down topologies [30] with less complexity and good
of kHz, while the post-stage highly-integrated converters use inductors is a good choice. For chiplet 3D integration, where
low-voltage (1.8V or 1V) devices and integrated passives the high-density capacitors are closer to the load and power
and operate at higher FSW in 1 to tens of MHz range. delivery suffers from relatively larger I 2R losses,
Topologies with multi-path would naturally be more inductor-first buck, and inductor-in-the-middle buck-buck
feasible for the post-stage. Also, we may easily employ more are the possibilities.
power inductors to share the large current in a multi-path Another very important future direction is digitalization of
topology. The number of inductors for a DC-DC buck the analog and power-conversion circuits. Both digitally
converter is mainly decided by three factors: 1) the output controlled DC-DC power converters [74] and digital LDO
current level, 2) the available space, and 3) the equivalent regulators [75] have been widely studied. The digital
switching frequency. Prior examples show reference controllers can be more flexible, easy reconfigurable and
numbers ranging from 1A/inductor to 10A/inductor. Here, process scalable compared to the analog counterparts,
we capture the value of current per inductor around the peak especially for high-current applications. One possible step
efficiency point from the references. In space-limited further, new power converter topologies could also be
scenarios, a smaller inductor with low-Q may result in synthesized, there is a recent intriguing development in the
1A/inductor [35]. For high-current board-level designs with domain of automated topology generation [76], by refining
discrete components, bulky high-Q inductors may support the SCI hybrid DC-DC converter design into mathematical
10A/inductor [28]. questions, equations, and solutions.
Fig. 20 illustrates the conceptual cross section of a vertical Fig. 21 summarizes multiple aspects of fully-integrated
package solution with integrated voltage regulators (IVRs). voltage regulators (FIVR) or IVR for hybrid DC-DC power
For extremely compact 3D chiplet solution with advanced delivery to hit the target. The fully-synthesizable, flexibly
packaging technologies, we may have miniaturized package distributed, multiple-output, fast transient features are highly
or parasitic inductors that only support sub-1A per inductor favorable, to be enabled by novel converter topologies with
[66]-[68]. The IVR in [49] with an in-package substrate advanced packaging and passive technologies, and to be
inductor technology called coaxial magnetic integrated design-cycle accelerated by design automation.
inductor (CoaxMIL) [69] demonstrated ~86% peak
efficiency for a 1.8V-to-0.7V conversion with over 1A per V. CONCLUSIONS
inductor.
This paper reviews the recent very popular topic of
Also, we may have high-density deep-trench or
switched-capacitor-inductor hybrid DC-DC converters. We
metal-insulator-metal (MIM) capacitor technologies. Then,
defined six routes or categories for the hybrid topologies,
it would be more feasible to add post-stage SC converters on
summarized the existing converters into these six routes, and
chip [70]-[72], which may also remove the necessity of
discussed their advantages, drawbacks, and remaining issues.
post-stage on-chip low-dropout (LDO) regulators for
Then, we extracted the favorable basic cells and building
dynamic voltage scaling (DVS), as the SC converters can
blocks for hybrid converters, proposed a way to invent or
also provide fast transient as well as the LDO does [71].

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 This article has been accepted for publication in IEEE Open Journal of the Solid-State Circuits Society. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/OJSSCS.2023.3334228

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 This article has been accepted for publication in IEEE Open Journal of the Solid-State Circuits Society. This is the author's version which has not been fully edited and
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 This article has been accepted for publication in IEEE Open Journal of the Solid-State Circuits Society. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/OJSSCS.2023.3334228

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Power Electron., vol. 38, no. 9, pp. 11193-11220, Sept. 2023.

Yan Lu (Senior Member, IEEE) received the

B.Eng. and M.Sc. degrees in microelectronics Wen-Liang Zeng (Member, IEEE) received the
from the South China University of Technology, B.Sc., M.Sc., and Ph.D. degrees in electrical and
Guangzhou, China, in 2006 and 2009, computer engineering from the University of
respectively, and the Ph.D. degree in electronic Macau, Macau, China, in 2014, 2016, and 2020,
and computer engineering from The Hong Kong respectively. He is currently a Post-Doctoral
University of Science and Technology (HKUST), Fellow (Macau Fellow) with the Institute of
Hong Kong, China, in 2013. Microelectronics, University of Macau, where he
In 2014, he joined the State Key Laboratory of joined the State Key Laboratory of Analog and
Analog and Mixed-Signal VLSI, University of Mixed-Signal VLSI since 2013. His research
Macau, Macau, China, where he is currently an focuses on high-speed fully integrated, ultralow
Associate Professor. He has authored/coauthored more than 150 quiescent current integrated, hybrid integrated, and large conversion ratio
peer-reviewed technical articles and two books. His research interests high power density integrated dc–dc converters.
include wireless power transfer circuits and systems, high-density
integrated power converters and voltage regulators.
Dr. Lu is serving as a TPC Member for ISSCC and CICC, and an IEEE
SSCS Distinguished Lecturer (2022–2023). He has served as a Guest Editor
for the IEEE JSSC in 2022 and 2023, IEEE TCAS-I in 2019, and the IEEE Mo Huang (Senior Member, IEEE) received the
TCAS-II in 2018 and 2019. He has been serving as a Young Editor for the B.Sc., M.Sc., and Ph.D. degrees in
Journal of Semiconductors since 2021. He was a recipient/corecipient of the microelectronics and solid-state electronics from
NSFC Excellent Young Scientist Fund (Hong Kong-Macau) in 2021, the Sun Yat-sen University, Guangzhou, China, in
Macau S&T Award second prizes in 2018 and 2020, the IEEE Solid-State 2005, 2008, and 2014, respectively.
Circuits Society Pre-Doctoral Achievement Award (2013–2014), the IEEE From 2008 to 2014, he was an IC Design
CAS Society Outstanding Young Author Award in 2017, and the ISSCC Engineer and Project Manager with Rising
2017 Takuo Sugano Award for Outstanding Far-East Paper. Microelectronic Ltd., Guangzhou, China. From
2015 to 2016, he was a Post-Doctoral Fellow with
the State Key Laboratory of Analog and
Mixed-Signal VLSI (AMSV), University of
Macau, Macau, China. From 2017 to 2019, he was with the School of
Junwei Huang (Student Member, IEEE) received Electronic and Information Engineering, South China University of
the B.Eng. degrees in microelectronics from the Technology, Guangzhou, China, as an Associate Professor. He is currently
University of Electronic Science and Technology an Assistant Professor with AMSV and Institute of Microelectronics,
of China (UESTC), Chengdu, China, in 2018. He University of Macau, Macau, China. His current research interests are
is currently pursuing the Ph.D. degree with the power management integrated circuits and systems.
State Key Laboratory of Analog and Dr. Huang is serving as an Associate Editor of Microelectronics Journal
Mixed-Signal VLSI, University of Macau, Macau, since 2021. He has served as Technical Program Committee member of
China. multiple conferences. He was a recipient of the ISSCC 2017 Takuo Sugano
His research interests include hybrid DC-DC Award for Outstanding Far-East Paper.
converter and analog circuit design.

Xiangyu Mao (Member, IEEE) received the

BEng and MSc degrees in Electronic Engineering
Zhiguo Tong (Student Member, IEEE) received from Xidian University, Xi’an, China, in 2009 and
the B.E. degree in electronic science and 2012, respectively, and the Ph.D. degree in
technology from Tianjin University, Tianjin, electronic and computer engineering from
China, in 2018 and the M.Sc. degree in University of Macau, Macau, China, in 2022.
Microelectronics and Solid-State Electronics from From 2012 to 2019, he was an IC Design
Fudan University, Shanghai, China, in 2021. Engineer and then a Project Manager with
He is currently pursuing the Ph.D. degree in Hisilicon Corporation, Shenzhen, China, mainly
electrical and computer engineering with the State responsible for various analog IPs from 40 nm to 7
Key Laboratory of Analog and Mixed-Signal nm CMOS technology.
VLSI, University of Macau, Macao, China. He Dr. Mao is currently a Postdoctoral Fellow with the State Key Laboratory

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 This article has been accepted for publication in IEEE Open Journal of the Solid-State Circuits Society. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/OJSSCS.2023.3334228

> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 13

of Analog and Mixed-Signal VLSI, University of Macau. His research

interests are power management systems for multi-core processors,
including dc-dc converters, fully integrated voltage regulators, and power
integrity.

Guigang Cai (Member, IEEE) received the

B.Eng. degree in electrical engineering and
automation from Xi’an Jiaotong University, Xi’an,
China, in 2013, and the Ph.D degree in electrical
and computer engineering from University of
Macau, Macao, China, in 2022.
In 2023, He join the Microelectronic Thrust,
Function Hub, the Hong Kong University of
Science and Technology (Guangzhou),
Guangzhou, China, as an Assistant Professor. His
current research interests include hybrid DC-DC
converter, analog and digital low-dropout
regulator, switched-capacitor and isolated power transfer circuits and
systems.

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