Microprocessors and Microcontrollers

Introduction to Microprocessors and Microcontrollers

• A microprocessor is a CPU on a single chip (no onboard memory or I/O). It requires external
RAM, ROM and peripherals to form a computer 1 . Typical examples: Intel 8085, 8086; used in
PCs and high-performance systems.
• A microcontroller (MCU) is a “computer-on-chip” that integrates CPU, RAM, ROM (or Flash), and
I/O peripherals on one chip 1 . It is optimized for embedded control tasks (e.g. automotive
controllers, IoT devices) and often uses Harvard architecture for speed. MCUs do not need
complex external support or OS.
• Key differences: MCUs are low-cost, low-power, all-in-one chips for dedicated tasks; MPUs are
powerful CPUs needing external memory and peripherals 1 2 . MPUs follow Von Neumann
architecture (shared buses), MCUs often use Harvard architecture (separate data/instruction
buses) 3 .

8085 Microprocessor

Architecture

Block diagram of the Intel 8085 microprocessor. The 8085 is an 8-bit CPU (ALU and registers) on one chip.
Its main components include:
- Accumulator (A): 8-bit arithmetic/logic register. Used for most operations.
- General Registers (B, C, D, E, H, L): Six 8-bit registers. These can be paired as BC, DE, HL for 16-bit
operations 4 . For example, HL pair often holds memory addresses.
- Program Counter (PC): 16-bit register holding the address of the next instruction. After each fetch it
increments by one.
- Stack Pointer (SP): 16-bit register pointing to the top of the stack in memory (stack grows downward)
5 . Used for saving return addresses and temporary data during CALL/RET and interrupts.

- Instruction Register/Decoder: Holds the current opcode. The decoder determines the operation and
operands.
- Flag Register: 8 bits, with 5 important status flags: Sign (S), Zero (Z), Auxiliary Carry (AC), Parity (P), and
Carry (CY) 6 . These indicate the result of arithmetic/logical operations (e.g. Z=1 if result is zero).
- ALU (Arithmetic & Logic Unit): Performs arithmetic (ADD, SUB, etc.) and logical (AND, OR, etc.)
operations on the accumulator and data.
- Internal Buses:
- Data Bus: 8-bit bi-directional bus for data transfer between CPU and memory/I-O 7 .
- Address Bus: 16-bit uni-directional bus (A0–A15) carrying addresses from CPU to memory/I-O 7 .
- Control Bus: Several control and status signals (e.g. RDʼ, WRʼ for read/write, ALE, IO/Mʼ, interrupt lines,
clock, RESET) that coordinate operations.

• Serial I/O: The 8085 has a 1-bit serial input (SID) and output (SOD) port for bit-by-bit serial
communication 8 . (Data from SID is shifted into the Serial Shift Register; SOD shifts data out
from the accumulator.)

All these units work together during the instruction cycle: fetch (PC→memory read), decode, execute
(ALU operations or data transfer), and write-back.

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Pin Configuration

Pin layout of the 8085 (40-pin DIP). The pins (on a 40-pin DIP package) fall into groups 9 10 :
- AD0–AD7 (Multiplexed Address/Data Bus): 8 bi-directional lines. In the first clock phase (T1) they
output the low-order address bits (A0–A7) for memory access; in later phases they serve as data bus
(D0–D7) 11 .
- A8–A15 (Address Bus): 8 uni-directional lines carrying high-order address bits (A8–A15) from CPU to
memory/I-O 12 .
- ALE (Address Latch Enable): Output pulse that goes high in T1 to latch AD0–AD7 into an external latch
(e.g. 74LS373). This separates (demultiplexes) the address and data phases 13 .
- IO/Mʼ: Status line (LOW = memory operation, HIGH = I/O operation) 14 . This tells memory or I/O
device whether the address is for memory or peripheral.
- S0, S1 (Status Lines): These indicate the type of machine cycle (opcode fetch, memory read/write, I/O
read/write, etc.) when used with IO/Mʼ 15 .
- RDʼ, WRʼ: Active-low control outputs. RDʼ goes low to read data from memory/I-O, WRʼ goes low to
write data.
- CLK (Clock): Input clock (e.g. 3 MHz) that drives the processor timing.
- RESET IN/OUT: Input to reset CPU to initial state; RESET OUT pulses another CPU or device to reset.
- INTR, RST7.5, RST6.5, RST5.5, TRAP: Interrupt request inputs (discussed below).
- SID, SOD: Serial I/O data in/out (one bit).
- VCC (+5V) and GND: Power supply pins.

These pins allow the 8085 to interface with external memory and devices.

Bus Concept and Organization

• The 8085 uses a bus architecture: a set of shared lines (buses) that connect the CPU, memory,
and I/O. The address bus (16-bit) carries addresses from CPU to memory or I/O; the data bus
(8-bit) carries data in both directions 7 .
• Unidirectional vs. Bidirectional: Address lines are one-way (CPU→memory); data lines are two-
way, so either CPU or memory/I-O can drive them.
• Bus Organization: Internally, tri-state buffers drive these buses under control of signals (RDʼ/
WRʼ etc.) so only the intended device drives the lines at a time. The control bus lines (ALE, IO/Mʼ,
RDʼ, WRʼ, etc.) manage this data flow.

Multiplexing and Demultiplexing of Buses

• To save pin count, the 8085 multiplexes the lower half of the address bus with the data bus 16 .
Lines AD0–AD7 first carry address bits (A0–A7) and later act as data lines.
• Demultiplexing: The ALE signal is used to latch the address. When ALE=1 (T1 state), AD0–AD7
outputs address bits to an external latch (e.g. 74LS373). When ALE=0, the latch holds the address
and AD0–AD7 become the data bus 17 . This ensures address and data phases don’t conflict.
• This multiplexing reduces CPU pin count (32 I/O pins instead of 40+).

Static vs. Dynamic RAM

• Static RAM (SRAM): Each bit stored in a flip-flop (built from transistors). It is fast and doesn’t
need refreshing. However, it is complex and expensive, so SRAM chips have lower density. (Used
for CPU cache and small high-speed memory.) 18
• Dynamic RAM (DRAM): Each bit stored as charge in a tiny capacitor (with one transistor). Much
simpler, so chips have higher density and are cheaper per bit. But the charge leaks, so DRAM
must be refreshed periodically (refresh circuits). DRAM access is slower than SRAM. 18

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 • Uses: In microprocessor systems, DRAM is common for main memory; SRAM is used where
speed is critical (caches, registers).

Types of ROM

• Mask ROM: Data is written during chip manufacturing (hard-wired); users cannot alter it 19 .
Very low cost per bit, but inflexible (needs new mask to change data). Used for factory-
programmed code.
• PROM (Programmable ROM): Initially blank ROM that can be programmed (blown fuses) once
by the user. After programming, contents are permanent 20 . Useful for small-volume
customization.
• EPROM (Erasable PROM): Can be erased by UV light (through a quartz window) and
reprogrammed. Data remains without power. Relatively economical; rewritable, but erasing
requires special UV lamp 21 .
• EEPROM (Electrically Erasable PROM): Can be erased and rewritten electrically (e.g. one byte at
a time) without removing chip 22 . Non-volatile and flexible, but slower and more expensive.
Modern Flash memory is a type of EEPROM (used in firmware, BIOS).

Memory Mapping

• The 8085 has 16 address lines, giving a 64 KB (65536-byte) address space (0x0000–0xFFFF). This
space is “mapped” among ROM, RAM, and optionally memory-mapped I/O.
• ROM Placement: Typically, the lowest addresses (starting at 0000H) hold ROM. This is crucial
because on reset the CPU begins fetching from address 0000H 23 . If RAM were at 0000H, the
CPU might fetch garbage. Thus, BIOS or bootstrap code is usually at 0000H.
• RAM Placement: User RAM is usually placed at the higher end of address space (e.g. just below
FFFFH), but the exact map depends on hardware.
• I/O vs Memory Mapping: The 8085 provides 256 separate I/O addresses (00H–FFH) accessible
by IN/OUT instructions (IO/Mʼ high) 24 . This means it can address 64KB memory plus 256 I/O
ports simultaneously. Alternatively, devices could be mapped into the memory space (memory-
mapped I/O), but then they consume memory addresses. In Intel designs, I/O ports are usually
separate.
• Example: With I/O-mapped I/O, the CPU can address 64KB RAM/ROM and 256 I/O devices 24 . If
a device were memory-mapped, it would occupy some of the 64KB memory space.

8085 Software Architecture

Registers and Flags

• As above, the CPU’s register file consists of A, B, C, D, E, H, L (8-bit) plus PC and SP (16-bit) 25 .
The Accumulator (A) is used in all ALU operations.
• Flag register (often part of PSW along with A): contains status bits after each operation 6 . Key
flags: Zero (Z), Sign (S), Parity (P), Carry (CY), Auxiliary Carry (AC). For example, Z=1 if an operation
yields 0; CY=1 if there is a carry/borrow.
• Instruction Register/Decoder: After fetching, the opcode is placed here and decoded. Control
circuitry then enables the necessary data transfers.
• Control Signals (internal): The CPU generates control signals (ALE, RDʼ, WRʼ, etc.) based on the
current operation. These are used on the buses to read/write data or notify devices of the action.

3
Instruction Classification

The 8085 instruction set is organized into classes 26 :

- Data Transfer Instructions: Move data between registers, memory, and I/O (without changing it).
Examples: MOV R1,R2 , MVI A, 0xFF , LDA 2000H , STA 2000H , IN , OUT 27 .
- Arithmetic Instructions: Perform arithmetic on registers or memory. E.g. ADD B (add B to A), SUB
C , INR D (increment D), DCR E , INX H , DCX SP , DAA (decimal adjust) etc. They affect the flags
(Z, CY, etc.).
- Logical Instructions: Bitwise operations on registers/accumulator. Examples: ANA B (A←A & B),
XRA C (A←A XOR C), ORA D , CMA (complement A), RLC/RRC (rotate).
- Branching (Jump/Call) Instructions: Change program flow. Unconditional: JMP addr , CALL
addr , PCHL (jump to HL), RST n . Conditional: JZ addr , JNZ addr , JC addr , JNC addr ,
JP addr , JM addr , etc. These test flags and may jump. Also RET (return) instructions.
- Control Instructions: System control. NOP (no operation), HLT (halt CPU), DI / EI (disable/enable
interrupts), and SIM/RIM (serial interrupt control on the 8085A).

Addressing Modes

8085 instructions can specify operands in different ways 28 29 :

- Immediate Addressing: Operand is in the instruction itself. E.g. MVI A, 0x32 (load immediate 8-bit
data 0x32 into A) 28 . For 16-bit, e.g. LXI H, 3000H .
- Register Addressing: Operand is in a register. E.g. MOV A,B (copy B→A) 30 .
- Direct (Memory) Addressing: Instruction specifies a memory address. E.g. LDA 2000H loads
accumulator from memory address 2000H 31 , STA 3000H stores A to 3000H.
- Register Indirect: Memory address is in a register pair (HL). E.g. MOV A, M loads A from memory at
address in HL, MOV M,B stores B into memory at HL 32 . (Here M is a pseudo-operand meaning [HL].)
- Implied (Implicit) Addressing: No explicit operand; the accumulator or flags are used implicitly. E.g.
CMA (complement A), CMC , STC , RAL (rotate A via carry) 33 .

Assembly Language Programming and Debugging

• Programs are written in mnemonic assembly code and assembled into machine code. Each
instruction has an opcode and operands (if any) in a specific format. For example, ADD B is
encoded in one byte, LXI H, 3000H in three bytes.
• Debugging: As 8085 is low-level, programs are often debugged using emulators or simulators.
Techniques include single-stepping through instructions, inspecting registers and memory, and
using breakpoints. This helps identify logic errors or incorrect data handling 34 . Static
debugging (paper/tracing) and dynamic debugging (monitoring run-time state) are both used
34 .

• Example: A common debugging step is observing the Program Counter and register values after
each instruction to ensure branches and data moves occur as intended.

Programming Techniques

• Looping/Delays: Use registers or register pairs as counters. For example, load B with a count
and use DCR B / JNZ loop to create a delay or repetitive task. Nested loops (using D and C
registers) can create longer delays.
• Subroutines: Encapsulate code in routines with CALL and return with RET . Pass parameters
via registers or memory. This avoids code duplication.
• Optimizations: Use minimal instructions (e.g., use MOV instead of LDA if data is already in
registers), use auto-increment pairs ( INX/DX ), and leverage the accumulator operations.

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Instruction Format and Timing Diagram

Timing diagram for an 8085 instruction cycle (fetch and execute phases). Each instruction fetch-execute
sequence is broken into machine cycles and T-states (clock periods). For example, a simple register-to-
register MOV instruction might take:
- Opcode Fetch (Machine Cycle 1): 1 memory read (4 T-states).
- Execution (Machine Cycle 2): No additional memory access (often 3 T-states) 35 .
In general, the fetch cycle is 4 T-states, and many instructions execute in 3 T-states 35 . Complex
instructions (e.g. memory read/write) add extra machine cycles.
- A T-state is one clock period. A machine cycle is the time to perform a memory or I/O operation
(often 3–4 T-states). An instruction cycle includes all machine cycles for that instruction.
- ALE Timing: During the first T-state (T1) of the fetch cycle, ALE is high (1) to latch the low-order
address. Then ALE goes low, and the same lines provide data. RDʼ is asserted (low) when reading the
opcode from memory 35 .

Advanced Assembly Language Programming

Counters and Time Delay

• Software Counters: Use register decrements and jumps for counts/delays. For instance,
LXI B, 0x0100 then a loop: DCX B; MOV A,B; ORA C; JNZ loop . This waits until BC =
0000H (decrementing a 16-bit counter).
• Timing Loops: Carefully calculate instruction cycles to generate precise delays (e.g., blinking an
LED). Often one creates nested loops or uses DJNZ -like constructs (though 8085 has no DJNZ,
the effect is achieved with DCR / JNZ ).
• For time-critical tasks, one might pre-calculate loop counts or use an external timer chip (like
8254).

Interrupts

• Hardware Interrupts (8085 pins):

• TRAP: Non-maskable, highest priority. Vectored to address 0024H. Used for critical events (e.g.
power failure).
• RST 7.5/6.5/5.5: Maskable vectored interrupts (fixed vectors 003C, 0034, 002CH respectively).
RST7.5 is edge/level sensitive (depends on version), others are level-sensitive. These have
descending priority (7.5 highest of the three) 36 .
• INTR: General interrupt request (non-vectored). When INTR is high and the CPU detects it after
an instruction, it finishes the current instruction and outputs an interrupt acknowledge cycle. An
external device must then put an opcode on the data bus (often an RST instruction) to specify the
interrupt service routine.
• Software Interrupts (RST 0–7): There are 8 one-byte restart (call) instructions: RST 0 through
RST 7 . Executing RST n is equivalent to calling address n*8H (for example, RST 1 → call
0008H) 37 . These are often used to implement software-triggered interrupts or quick calls.
• Uses: Interrupts allow the CPU to respond to external events (key presses, timers, I/O status)
immediately. A common use is a timer or keyboard interrupt; the CPU saves context, jumps to an
ISR, and then resumes.

RST Instructions

• RST n is both a software instruction and the vector for hardware interrupts of the same name.
E.g., executing RST 3 pushes PC and jumps to 0018H. For hardware, if RST5.5 line is triggered,

5
 the CPU does an automatic RST 2 (vector 0010H). RST instructions are single-byte calls,
making interrupt vectors easy to predict.

Intel 8259 Programmable Interrupt Controller

Block diagram of the Intel 8259A PIC. The 8259 is an external chip that expands and prioritizes interrupts
for the 8085 38 . Key points:
- It provides 8 interrupt inputs (IR0–IR7) to the CPU (versus 5 on bare 8085) 38 . Internally, it encodes
and sends the highest-priority interrupt to the CPU on a single output line (connected to the CPU’s INTR
pin).
- Priority Resolution: The 8259 assigns a fixed priority to IR0–IR7. It also supports masking (each
interrupt can be disabled via the Interrupt Mask Register).
- Vectored Operation: On an interrupt acknowledge cycle, the 8259 places a vector (e.g., 8n for IRQn)
on the data bus so the CPU knows which ISR to execute.
- Cascading: Multiple 8259s can be daisy-chained to support up to 64 IRQ lines 39 .
- Modes: Supports level-triggered or edge-triggered modes.

Macros and Subroutines

• A macro is a sequence of instructions defined once (in assembly) and expanded inline wherever
invoked. It makes code reusable and easier to write (e.g. INCR_REG macro R expands to
INR R ). Macros do not execute as separate subroutines; they are assembler-time expansions.
• A subroutine is a piece of code called via CALL addr and returned by RET . Subroutines allow
code reuse at run-time without duplication. Parameters can be passed in registers or memory,
and the stack (SP) holds return addresses.

Stack Implementation

• The stack is an area of memory (usually RAM) used for storing return addresses, register values,
or local data. The Stack Pointer (SP) points to the top (current end) of the stack 25 .
• PUSH/POP: The 8085 has PUSH rp and POP rp (where rp is register pair BC, DE, HL, or PSW).
PUSH decrements SP and writes the register pair to memory; POP reads from memory into
the register pair and increments SP.
• CALL/RET: CALL addr pushes the return address (current PC+3) onto stack and jumps to addr.
RET pops the address back into PC. This uses the stack automatically.
• Example: To save register B and C before a subroutine, use PUSH B , and after finishing,
POP B .

Memory Interfacing

• Connecting Memory Chips: External RAM/ROM chips are attached to the 8085’s address/data/
control buses. Address lines A0–Ax connect to chip address inputs; data lines D0–D7 connect to
data inputs of chips.
• Chip Select Decoding: You typically use address decoding logic (e.g. a 74LS138 decoder) on the
high-order address lines to generate Chip Select (CS) signals. For instance, to interface an 8K×8
EPROM and 8K×8 RAM: tie A0–A12 as address inputs, and decode A13–A15 with a 3-to-8 decoder.
When A15–A13 = 000, CS enables EPROM; when 001, CS enables RAM 40 .
• Buffers/Latches: Use latches (like 74LS373) with ALE to separate addresses from data lines. Use
transceivers (74LS245) or buffers to handle data bus directions.

6
8085 Interfacing

8255 Programmable Peripheral Interface

• The 8255 PPI provides 24 programmable I/O pins divided into Port A (8 bits), Port B (8 bits),
and Port C (8 bits) 41 . Port C is often split into upper/lower (PC7–PC4 and PC3–PC0) for
handshake lines.
• Each port can be configured as input or output. The 8255 operates in three modes:
• Mode 0 (Simple I/O): Ports are basic 8-bit inputs or outputs. Port C bits can be used individually
for handshake signals.
• Mode 1 (Strobed I/O): One of Port A/B is used with handshake on Port C bits. For example, Port
A input with PC lines to request/acknowledge transfers. Interrupt capability is available in this
mode 42 .
• Mode 2 (Bidirectional Bus): Only Port A is bidirectional (with two sets of handshake lines on
Port C) 43 . Port B can operate in Mode 0 or Mode 1.
• Control Word: A control register (written via IN/OUT) sets the mode and direction of each port.
• Interfacing: 8255’s port pins directly connect to I/O devices (sensors, LEDs, etc.). The 8085
addresses the 8255 like memory: e.g., OUT to its address to write control word, IN/OUT to port
addresses to send/receive data.

8254 Programmable Interval Timer (PIT)

• The 8254 (successor of 8253) has 3 independent 16-bit counters (Counter 0,1,2) that can be
programmed for various timing modes 44 . Each counter has a clock input, gate input, and
output. When Gate=1, the counter decrements on each clock; when it reaches 0 it may generate
an output pulse or interrupt.
• Programming: A control word (sent via the data bus with appropriate address lines) selects
counter, mode (0–5), and binary/BCD. Then two bytes of count are written.
• Modes: Include interrupt-on-terminal-count, programmable one-shot, square-wave generator,
software-triggered strobe, etc. Useful for generating baud rates, delays, or timed events.
• Applications: Typical uses are creating precise delays, generating periodic interrupts, frequency
measurement, or as part of baud-rate generation for serial ports 45 .

General I/O Device Interfacing

• I/O devices (ADC, DAC, sensors, displays) are interfaced either via parallel ports or serial ports.
For parallel devices, use PPI or direct port lines. For serial devices, use serial interface chips (e.g.,
8251). Handshaking or interrupts can coordinate data transfer. Level shifting (e.g., between TTL
and RS-232 levels) is often needed.

8279 Keyboard/Display Controller

• The 8279 is a specialized chip for scanning keyboards and driving displays. It handles up to a 64-
key matrix and up to 16 7-segment digits (or a bit-mapped display).
• Keyboard: It periodically scans rows and columns (with X and Y scan lines) to detect key presses,
debounces them, and reports a key code to the CPU. The 8085 reads the key codes by polling or
interrupt.
• Display: It generates the multiplex signals and segment patterns for 7-seg LED displays. The
CPU writes display data into 8279’s internal display RAM; 8279 then continuously refreshes the
display.
• The 8279 also provides features like auto-incrementing addresses, look-up tables (for shifting
column data to key codes), and interrupt-on-keypress.

7
 • Example use: A microprocessor reads a matrix keypad (via 8279) and updates a 7-seg score
display through the same chip.

Applications of Microprocessors
• Multiplexed LED Displays: Driving a multi-digit 7-segment display by time-division multiplexing.
For example, 4 digits share segment lines, and each digit has its own enable line. The CPU/8255
outputs segment patterns to all digits but only enables one digit at a time in rapid succession.
Persistence of vision makes all digits appear lit.
• LCD Interfacing: Text LCDs often use a parallel interface (e.g. 8-bit bus plus control lines RS, RW,
E). The microprocessor writes characters/commands by setting data lines and toggling the
enable. Handshaking (busy flag) or fixed delays are used.
• Matrix Keyboard: A keypad (e.g. 4×4) is interfaced by connecting rows to output lines and
columns to input lines. The CPU drives one row low at a time and reads which column is low to
detect a press. This can be done with GPIO or via 8255 in Mode 1 or using 8279.
• Microprocessor-based System Design: Involves choosing the CPU (e.g. 8085), clock circuit,
memory (ROM/RAM) configuration, I/O devices, and bus interfacing logic (decoders, buffers).
Designers create a memory map and I/O map, implement address decoding, and write firmware.
• USART 8251: The Intel 8251 is a Universal Synchronous/Asynchronous Receiver/Transmitter that
provides serial communication for the 8085. In asynchronous mode, it formats data with start/
stop bits for RS-232 links. In synchronous mode, it can shift data bit-clocked. Typically used for
RS-232 serial ports to PCs or modems.
• RS-232C vs RS-422A: RS-232C is a common serial standard using single-ended signaling (±12V)
for short distances (≈15 meters) point-to-point. Only one driver and one receiver (full-duplex)
46 . RS-422A uses balanced differential pairs for data and clock (4-wire: 2 for transmit, 2 for

receive). It supports one driver and multiple receivers (up to ~10) on each pair, and much longer
distances (hundreds of meters) 46 . (RS-422 has better noise immunity due to differential
signaling.)
• Parallel Interfaces:
• Centronics Parallel (IEEE 1284): Originally used for printers. Uses 8 data lines plus control lines
(Strobe, Busy, Ack, etc.) to transfer bytes in parallel 47 . Modern bidirectional modes (EPP/ECP)
allow up to ≈2.5 MB/s.
• IEEE 488 (GPIB/HP-IB): An 8-bit parallel, multi-master bus for instrument control 48 . Up to 15
devices (controllers or peripherals) can share the bus. It has 8 data lines and 8 control lines (for
handshake, ATN, EO1, DAV, NRFD, NDAC, IFC, SRQ). It was widely used in test and measurement
equipment.

Each of these interfacing methods and applications involves both hardware (wiring, chip selection, level
translation) and software (device drivers, protocols).

Sources: Comprehensive 8085 architecture details 4 49 10 , instruction and interrupt info 26 28

36 , memory/RAM concepts 18 , PIC block diagram 38 , and interfacing standards 45 50 47 48 .

These notes synthesize textbook and up-to-date materials for exam preparation.

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19 20 21 22 Different Types of ROM | GeeksforGeeks

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23 digital logic - Memory mapping in the 8085 microprocessor - Electrical Engineering Stack Exchange
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24 I/O Mapped I/O or Memory Mapped I/O in 8085 Microprocessor

https://www.tutorialspoint.com/i-o-mapped-i-o-or-memory-mapped-i-o-in-8085-microprocessor

26 27 Instruction Set of 8085 Microprocessor : Classification with Examples

https://www.elprocus.com/instruction-set-of-8085-microprocessor/

28 29 30 31 32 33 36 37 8085 Microprocessor Addressing Modes and Interrupts

https://www.tutorialspoint.com/microprocessor/microprocessor_8085_addressing_modes_and_interrupts.htm

34 Debugging a machine level program | GeeksforGeeks

https://www.geeksforgeeks.org/debugging-a-machine-level-program/

35 Instruction cycle in 8085 microprocessor | GeeksforGeeks

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38 39 8259 PIC Microcontroller | GeeksforGeeks

https://www.geeksforgeeks.org/8259-pic-microprocessor/

40 Basic Concepts in Memory Interfacing with 8085 - Memory Interfacing

https://eee.poriyaan.in/topic/basic-concepts-in-memory-interfacing-with-8085-12255/

41 42 43 Microprocessor | 8255 (programmable peripheral interface) | GeeksforGeeks

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44 45 Microprocessor | 8254 programmable interval timer | GeeksforGeeks

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46 RS-232 vs RS-422 vs RS-485, What is the difference?

https://www.optcore.net/difference-between-rs-232-rs-422-and-rs-485/?srsltid=AfmBOopm8umkx6jdv0t6c-
DsEzqAt_-9jj0gc5FnQe4XumebE_xXDhRV

47 Parallel port - Wikipedia

https://en.wikipedia.org/wiki/Parallel_port

48 GPIB - Wikipedia
https://en.wikipedia.org/wiki/GPIB

50 8279 Programmable Keyboard

https://www.tutorialspoint.com/microprocessor/microprocessor_8279_programmable_keyboard.htm