Bansal Institute of Science and Technology,

Bhopal
(Department of Computer Science & Engineering)
Sem/Branch : 4th / CS Sub/Code: CS-404
SOLUTION OF IMPORTANT QUESTIONS OF UNIT 5

Q1. What is pipeline? Draw four segment pipelines.

In computing, pipeline refers to the logical queue that is filled with all the instructions for the
computer processor to process in parallel. It is the process of storing and queuing tasks and
instructions that are executed simultaneously by the processor in an organized way.

A pipeline includes processor tasks and instructions in different stages. The computer processor
works on each task in the pipeline. It works differently from the FIFO (first in-first out) and
LIFO (last in-first out) computing architecture, but allocates some processing time to each task in
the pipeline. The pipeline enables the processing of each task in parallel rather than waiting for a
task to finish and then moving onto another.

The organization of an instruction pipeline will be more efficient if the instruction cycle is
divided into segments of equal duration. One of the most common examples of this type of
organization is a Four-segment instruction pipeline.

A four-segment instruction pipeline combines two or more different segments and makes it as a
single one. For instance, the decoding of the instruction can be combined with the calculation of
the effective address into one segment.

The following block diagram shows a typical example of a four-segment instruction pipeline.
The instruction cycle is completed in four segments.

Segment 1:

The instruction fetch segment can be implemented using first in, first out (FIFO) buffer.

Segment 2:

The instruction fetched from memory is decoded in the second segment, and eventually, the
effective address is calculated in a separate arithmetic circuit.

Segment 3:

An operand from memory is fetched in the third segment.

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Segment 4:

The instructions are finally executed in the last segment of the pipeline organization.

Q2. Differentiate between instruction & arithmetic pipeline?

Arithmetic Pipelines are mostly used in high-speed computers. They are used to implement
floating-point operations, multiplication of fixed-point numbers, and similar computations
encountered in scientific problems.

To understand the concepts of arithmetic pipeline in a more convenient way, let us consider an
example of a pipeline unit for floating-point addition and subtraction.

The inputs to the floating-point adder pipeline are two normalized floating-point binary numbers
defined as:

X = A * 2a = 0.9504 * 103
Y = B * 2b = 0.8200 * 102

Where A and B are two fractions that represent the mantissa and a and b are the exponents.
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The combined operation of floating-point addition and subtraction is divided into four segments.
Each segment contains the corresponding suboperation to be performed in the given pipeline.
The suboperations that are shown in the four segments are:

1. Compare the exponents by subtraction.

2. Align the mantissas.
3. Add or subtract the mantissas.
4. Normalize the result.

We will discuss each suboperation in a more detailed manner later in this section.

The following block diagram represents the suboperations performed in each segment of the
pipeline.
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1. Compare exponents by subtraction:

The exponents are compared by subtracting them to determine their difference. The larger
exponent is chosen as the exponent of the result.

The difference of the exponents, i.e., 3 - 2 = 1 determines how many times the mantissa
associated with the smaller exponent must be shifted to the right.

2. Align the mantissas:

The mantissa associated with the smaller exponent is shifted according to the difference of
exponents determined in segment one.

X = 0.9504 * 103

Y = 0.08200 * 103

3. Add mantissas:
The two mantissas are added in segment three.

Z = X + Y = 1.0324 * 103

4. Normalize the result:

After normalization, the result is written as:

Z = 0.1324 * 104

Q3. Explain vector processing?

According to from where the operands are retrieved in a vector processor, pipe lined vector
computers are classified into two architectural configurations:

Memory to memory architecture – In memory to memory architecture, source operands,

intermediate and final results are retrieved (read) directly from the main memory. For memory to
memory vector instructions, the information of the base address, the offset, the increment, and
the vector length must be specified in order to enable streams of data transfers between the main
memory and pipelines. The processors like TI-ASC, CDC STAR-100, and Cyber-205 have vector
instructions in memory to memory formats. The main points about memory to memory
architecture are:

There is no limitation of size

Speed is comparatively slow in this architecture

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Register to register architecture – In register to register architecture, operands and

results are retrieved indirectly from the main memory through the use of large number of vector
registers or scalar registers. The processors like Cray-1 and the Fujitsu VP-200 use vector
instructions in register to register formats. The main points about register to register architecture
are:

Register to register architecture has limited size.

Speed is very high as compared to the memory to memory architecture.

The hardware cost is high in this architecture.

A block diagram of a modern multiple pipeline vector computer is shown below:

A typical pipe lined vector processor.

Advantages of Vector processor:
1. Parallelism and SIMD Execution: Vector processors are intended to perform Single
Guidance, Different Information (SIMD) activities. This implies that a solitary guidance can
work on numerous information components in equal, considering a huge speedup in errands that
include monotonous procedure on enormous datasets. This parallelism is appropriate for logical
recreations, reenactments of actual frameworks, signal handling, and different applications
including weighty mathematical calculations.
2. Proficient Information Development: Vector processors are enhanced for moving
information productively among memory and the computer chip registers. This is pivotal for
execution, as memory access is much of the time a bottleneck in many registering errands.
Vector processors commonly incorporate specific information development directions that can
move information in huge lumps, limiting the effect of memory dormancy.
3. Diminished Guidance Above: With SIMD tasks, a solitary guidance can play out similar
procedure on various information components. This lessens the above related with getting,
unraveling, and executing individual directions, which is especially helpful for errands that
include tedious computations.
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4. Energy Proficiency: By executing procedure on various information components at the same

time, vector processors can accomplish higher computational throughput while consuming
generally less power contrasted with scalar processors playing out similar activities
consecutively. This energy effectiveness is significant for superior execution registering (HPC)
applications where power utilization is a worry.
5. Logical and Designing Applications: Vector processors succeed in logical and designing
reproductions where complex numerical calculations are performed on huge datasets.
Applications like weather conditions displaying, computational liquid elements, atomic elements
reproductions, and picture handling can benefit altogether from the computational power and
parallelism presented by vector processors.
6. Superior Execution for Cluster Activities: Some true applications include controlling
exhibits or grids of information, for example, in information examination, AI, and illustrations
handling. Vector processors can perform activities like expansion, increase, and other component
wise procedure on whole clusters with a solitary guidance, significantly speeding up these
undertakings.
7. Compiler Streamlining: Vector processors frequently expect code to be written with a certain
goal in mind to make the most of their capacities. Compiler improvements can naturally change
undeniable level code into vectorized guidelines, permitting software engineers to zero in on the
algorithmic plan as opposed to low-even out advancements.
8. Memory Transmission capacity Usage: Vector processors can productively use memory
transfer speed by streaming information from memory into vector registers and afterward
performing calculations on those vectors. This can assist with alleviating the exhibition effect of
memory bottlenecks.
9. Vector Length Adaptability: Some vector processors permit adaptability in the length of
vector tasks, empowering software engineers to pick the proper vector length in light of the
application’s necessities and the accessible equipment assets.

Q4. What do you mean by ratio of pipeline processing?

The term "ratio of pipeline processing" typically refers to the efficiency or speed of a pipeline
system in processing tasks or data. In computing and engineering contexts, especially in
hardware design and software optimization, a pipeline is a sequence of stages where each stage
performs a specific operation on the input before passing it to the next stage.

The ratio of pipeline processing can be understood in a few different ways:

1. Throughput Ratio: This refers to how much faster a pipeline system can process tasks
compared to a non-pipeline system. It's often expressed as a ratio of speed improvement.
For example, a pipeline might have a throughput ratio of 2:1 compared to a non-pipeline
system, meaning it can process tasks twice as fast.
2. Efficiency Ratio: This measures how efficiently a pipeline utilizes its resources (such as
CPU cycles, memory, etc.) to process tasks. A higher efficiency ratio indicates that the
pipeline system wastes fewer resources and performs tasks more effectively.
3. Latency Reduction Ratio: In some cases, the ratio can refer to how much latency
(delay) is reduced by using a pipeline compared to non-pipeline processing. This is
particularly relevant in systems where reducing the time between input and output is
critical.
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In all cases, a higher ratio generally indicates better performance or efficiency of the pipeline
system. However, achieving high ratios often requires careful design, optimization of stages, and
minimizing overhead between stages in the pipeline.

Q5. Explain different between RISC & CISC.

RISC (Reduced Instruction Set Computer) and CISC (Complex Instruction Set Computer) are
two different computer architectures that have evolved over time, each with its own design
philosophy and characteristics. Here are the key differences between RISC and CISC
architectures:

1. Instruction Set Complexity:

 CISC: CISC processors have a complex instruction set, meaning they support a wide
variety of instructions that can perform complex operations. Instructions in CISC
architectures often include multiple steps and can directly operate on memory locations.
 RISC: RISC processors, in contrast, have a reduced and simplified instruction set.
Instructions are designed to be simpler and more basic, typically performing only one or
a few operations. RISC instructions are usually executed in a single clock cycle.

2. Instruction Execution:

 CISC: In CISC architectures, instructions can vary in length, and some instructions may
take multiple clock cycles to execute due to their complexity.
 RISC: RISC architectures aim for uniform instruction length and execution time. This
simplicity allows RISC processors to achieve higher instruction throughput and
potentially faster execution of programs.

3. Memory Access:

 CISC: CISC architectures often include instructions that can directly access memory and
perform operations, which can simplify programming but may lead to more complex
hardware design.
 RISC: RISC architectures typically follow a load-store model, where most operations are
performed on registers, and memory access is limited to load and store instructions. This
approach simplifies the processor's instruction set and pipeline design.

4. Hardware Complexity:

 CISC: Due to the complex nature of instructions and the variety of addressing modes,
CISC processors tend to have more complex hardware implementations.
 RISC: RISC processors are designed with simplicity in mind, which often results in a
more streamlined hardware architecture. This simplicity can lead to more efficient use of
hardware resources and easier scalability.

5. Performance and Efficiency:

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 CISC: CISC processors were historically designed to handle a wide range of tasks with
fewer instructions, making them suitable for diverse workloads but potentially sacrificing
some efficiency in specific tasks.
 RISC: RISC processors excel in tasks that can be optimized through pipelining and
efficient instruction execution. They are often favored in applications requiring high
performance, such as scientific computing and embedded systems.

Examples of Architectures:

 CISC: Examples of CISC architectures include Intel x86 (Pentium, Core series) and
AMD processors, which dominate desktop and server computing.
 RISC: Examples of RISC architectures include ARM (used widely in mobile devices and
embedded systems), MIPS, and PowerPC (historically used in gaming consoles and high-
performance computing).

In summary, while CISC processors focus on providing a broad and flexible set of instructions to
handle diverse tasks, RISC processors emphasize simplicity, efficiency, and the ability to
execute instructions quickly. The choice between RISC and CISC often depends on the specific
requirements of the application, performance considerations, and the intended use case of the
computing system.