2.

1 INTRODUCTION

ational amplifier, (op-amp) 1s a three stage circuit as shown in Fig. 2.1 and it is fabricated as an
is differential amplifier, the second stage provides additional voltage
integ
ted circuit. The first stage a

and the third stage provides current gain and low output impedance.
gan

Gain stage
Differential
or
output O Vo
Amplifier second stage
stage

Fig. 2.1 General block diagram of op-amp

and
The op-amp is integrated circuit that amplifiers the difference between two input voltages
an
electronic circuits and
produces a single output. Op-amps are used extensively in the design of
characteristics approach the
systems because of their relatively low cost and versatility and op-amp
1deal.

2.2 741 OP-AMP CIRCUIT

The 741 op-amp has been produced since 1966 by many semiconductor device manufacturers. Since
then, there have been many advances in op-amp design but the 741 is still a widely used general-purpose
op-amp.
. 2 shows the equivalent circuit of the op-amp. This circuit consists of three stages: the input
rential amplifier, the gain stage and the output stage. Fig. 2.2 also shows a separate bias circuit,
stablishes the bias currents throughout the op-amp. The 741 op-amp is biased with both positive
galve supply voltages. This eliminates the need for input coupling capacitors, which in turn
Rr t he circuit is also a dc amplifier. The dc output voltage is zero (for ideal op-amp not in
practical op-amp)
0p-amp) when the applied differential input signal is zero. Typical supply voltages are
C D
Vand Vr=-15 V. although input voltages as low as pOssible +5 V can be usea.
 Reference First stage Second stage Output stage
curTent
AVcc(+15 V)

12 134
Q138 Q14
Q15
R
27 Q

18 Out
R10 F R
27n
Rs 40 kO
39 kn S In In

Cc= 30 pF
Q20
REF Q23

Q16
Q10
Q7
3R =
SR= 50 kQ R
kO 100

SRI= 50 k2 R

1 kl I kA22
R
50 kO
-VEE(-15 V)y

Figure 12.14 The 741 op-amp circuit: 21.212, and R, generate a reference bias current, / rE- Qa O. and Q, bias the input stage, which is composed of Q, to , . Ihe
second gain stage is composed of ,, and Q,n With Q138 acting as active load. The class AB
output stage is formed by Q,, and Q2 with biasing devices ia 1s. and e1o
and an input buffer Transistors
Q23 15 221 Q24 and Q serve to protect the
amplifier against output short circuits and are normally cut off.
 741 IC OP-AMP 55
The

Nameofstage Components used Purpose

Transistor Resistor

Biasing circuit 1 12 Rs Generate bias current to supply entire op-amp circuit.

Biasing for eg9.10 R Provide bias for input stage

input stage
Bias for second
R10 Provide bias for both second stage and output stage.
stage and output

stage

Differential input . Q Q3. Q24 R, R2 R3 The input stage provide high input impedance to avoid

stage loading on the sources. It require two input terminals

and also provide low output impedance.

Second stage e16-179222 R R Provide an additional voltage gain

141522021 R, R, R1 Provide low output impedance large ac output voltage

Output stage
SWing and high current sourcing and sinking.
24
onecapacitor Provide frequency compensation

2.2.1 Bias Circuit

is generated using the two
Figure 2.2 shows the IC 741 op-amp circuit. The reference current IREF
diode connected transistors 1 and 212 and resistance Rs. The transistors 1» 210 and R4 form a
This current is generated in the
Widlar curent source that establish the bias current for the first stage.
collector of Q10. Another current mirror formed by Q and 2, is used for biasing the first stage.
The reference bias current IRpp is used to provide two proportional currents in the collectors of Q,1
This double-collector pnp transistor can be thought of as two transistors whose base-emitter junctions
are connected in parallel.
the collector of 21ap provides
Thus Q12 and Q13 form two-output current mirror-one output,
DIas current for Q17 second stage and other collector output
of 13A provides bias current for the
and Q19 are also a part of de bias process. The
output stage of the op-amp. Two more transistors 18
between the bases of the output transistors Q14
purpose of e1s and 219 is to establish two BE drops
and Q20

2.2.2 Input Stage

The IC 741 circuit consists of three stages:

1. Input differential stage

2. Intermediate single ended high-gain stage and

3. Output-buffering stage.
and
input stage consists of transistors , through 0, which is biased by
transistors Qg, e, 0
Tne
he purpose of each transistors are listed as follows:
 56 Integrated Circui

Transistors Purpose
Act as emitter follower to provide high input resistance and delivering the
and Q,
differential input signal to C-B amplifier

, and Act as common-base amplifier [cascoding the emitter follower with common
base amplifier results in a circuit with a low frequency gain approximately
equal to that of CB but with the problem of the low input resistance of the CB
is solved by buffering of CC stage]

Os.e, and Q7, and Forms active load of the input stage. This load circuit not only provides a high
resistors R1. Rz and R3 resistance load but also converts the signal from differential to single-ended
form with no loss in gain. The output of the input stage is taken single-end at
the collectors of
Q
Figure 2.3(a) shows a basic common-emitter differential pair used as the input to a differential
amplifier. If the input voltage V, were to be connected to a supply voltage of 15 V, with V2 at grounded
potential, then the B-E junction of O would be reverse biased by approximately 14.3 V. Since the
breakdown voltage of an npn transistor B-E junction is in the
range of 3-6 V, transistor 02 in Fig. 2.3(a)
would enter breakdown and suffer permanent damage

V 15V V2 V1 = 15Vo-
02
0.7V
0.7V+
14.3 V
=0.7 V
13.6 V
Q3

(a) (6)
Fig. 2.3 Basic differential input stage

Figure 2.3(b) shows the input stage of 741 op-amp with the same input
of Q, and Q, are forward biased, which means that the voltages. The B-E junction
series combination of B-E junctions of
O is reverse biased by approximately 13.6 V. The breakdown voltage of lateral , and
order of 50 V, which means that for this prp B-E junction 1s tn
input voltage polarity, the B-E junction of O provides
necessary breakdown protection for the input differential
amplifier stage.
 741 IC OP-AMP
The

2.2.3 Second Stage or Gain Stage

or intermediate stage consists of
The 1 ),7 P12p and two resistors R and Rg.

Transiors
Purpose
Act as an emitter follower, thus giving the
high input resistance to second
stage. This minimize the loading on the
input stage and avoids loss of gain.
Acts
common-emitter amplifier with a resistor in the emitter. Its load is
as a

composed of the high output resistance ofR,the

pnp current source 138 In
parallel with input resistance of the
output stage.
The transistor Q1 iseftectively two transistors connected in parallel with common base and
terminals. The area of emitter
2134 1s one-fourth the area of 21, and the area of
fourths that of Q12. Transistor Q138 provides the bias current for Q,13R is effectively three
Q7 and also acts as an active load to
nroduce a high voltage gain. Transistor Q17 operates in a common-emitter
voltage at the collector of 217 is the input signal to the output stage. The configuration. Therefore, the
level shift as it goes through this gain stage. Capacitor signal undergoes another dc
stage to provide frequency compensation.
Ccis connected in the feedback path of
second

2.2.4 Output Stage

The purpose of the output stage is to provide the
amplifier with low output resistance. In addition,
the output stage should be able to supply
large load currents without dissipating an excess large
amount of power in the IC 741. The output stage uses an efficient
output circuit known as class-AB
output stage.
The output of the gain stage or second stage is connected to the base of
follower and providesa very high input resistance and also minimizes the
Q23 which operates as emitter
on the second stage. Transistor
loading effect of the output stage
3A provides a bias current for 23 as well as
Q18 and which are
used to establish a quiescent bias current in the output transistors
are preferred to as short circuit
Q4 and Q20 Transistor Q1 and Q2
protection devices. These transistors are normally OFF; they conduct only
if the output is incidently connected to thus
ground, resulting in a very large output current.
2.2.5 Short-Circuit Protection Circuitryy
The output stage includes a number of transistors that are OFF during the normal operation of the
amplifier. If the ouput terminal is at a positive voltage because of an applied input signal, and if the
terminal is incidently shorted to ground potential, a large current will be induced in output transistor ,
A large current produces sufficient heating to cause transistor burnout which has to be avoided.

he short-circuit protection circuitry of 741 op-amp is shown in Fig. 2.4. Resistor R, and transistor
Pis limit the current in Q1 in the event of a short circuit. If the current in Q14 reaches 20 mA, the
volage drop across R is 540 mV, which is suflicient to bias Q15 in the conducting stage.
As 15 turns ON, excess base current into 14 is shunted through the collector of1 s The base
Current into Q, is then limited to a maximum value, which limits the collector current.
 58 Integrated Circuite
and D24 A large output current w
he maximum currentin O is limited by components R7, P21, its conducting state. Transist
sufficient to bias Q21 in Istor
result in a voltage drop across R, which will be this output transistor.
current away from O20
to protect
21 and P4 will shunt excessive output
9 Vcc

Q13A
Q14

Q15

Q18 Ro 27 2
Q19
Vo
Ri0 50 k
R 222 RL
O21

O20

R11
Q22 O24 50 k2

VEE
Fig. 2.4 Short-circuit protection circuitry of 741 op-amp

2.2.6 Device Parameters

The IC 741 consists of many npn and
pnp transistors. For the standard npn and pnp transistors,
following parameters will be used:

npn 10-14 A 200 125 V

pnp 10-14 A 50 50 V
 IC OP-AMP
The 741 59

In the 741 circuit the non-standard devices are Q12, Q1a and O0 Transistor Q1 will be assumed to
be equivalent to two transistors, 2134 and O138 with parallel base-emitterjunctions having the following
saturation currents

SA 0.25 x 10-14 A
SB0.75 10-14 A
x

Transistors 214 and will be assumed to each have an area three times the area of standard
Q20
transistors. The output transistors are having large area to provide large load currents to the load.
 ANALYSIS OF THE 741
23 DC
Thede
analvsis of the 1C 741 circuit is used to determine the bias point of each device. For the de
wsis ofan
analysis an op-amp
op-amp cireuit, the input terminals are grounded. The output of op-amp is zero when
rounded but practically we will not get zero output voltage because of transistor
are groi
the inputs
mismatch. The op-amp have very large gain (2,00,000 for IC 741 op-amp). Therefore the output
oltage is approximately near to either +Vcc or -VEE This is called saturated output when the op-
amp is in open-loop contiguration (no feedback between output and input). To overcome this problem
in the dc analysis it will be assumed that the op-amp is connected in a negative feedback loop that
stabilizes the output de voltage to zero volts.

2.3.1 Reference Bias Current

The reference current REF is generated in the branch composed ofthe two diode-connected transistors
1.12 and resistor Rs (Refer Fig 2.2). The circuit diagram is drawn separately as shown in
Fig. 2.5.

VBE12
O12

Rs 39 kn REF
th

VBE1
-VEE

Fig. 2.6 BC analysis ef referenee bias eurrent

 60
egrated Ciu
we can apply KVL for the circuit shown in Fig. 2.).

+BEPEE
cc VBE12 +REr Rs
cc-VBE12-BE VEE REF Rs
Yoc-PBE1Z-BE1+EE
IREF Rs
current
Occ 'EE15 Vand VELL Var 0.7V then thereference
=

15-0.7-0.7+15
REF 39x103

RE0.73 mA

2.3.2 Input-Stage Bias

The transistor 21 is biased by IREr and the voltage developed across it is used to bias the transis-
0 The transistor 1o has a series emitter resistanee R as shown in Fig. 2.6. (This is partof
circuit shown in Fig. 2.2). For this circuit, we assumed transistor have Bjo to be large.
The voltage developed across resistor R, from Fig. 2.6

BE1BE1O C1o R
BEI BE10CIo R 2
Using the equation (1.50), we can write the equation (2.2)

V,In IREE = Icio Ra 2

Ic1o

Note: lf RE0.73 mA, R 39 k2 and V 25 mV

25mV In 0.73mA CIO39 x 10
c1o
Solving, we get C1O 19 uA

The complete input stage is shown in Fig. 2.7 (Part of Fig. 2.2)
Ifthe transistorsQ, and Q, are symmetrical (all the parameters are same in both transistors) ther

If the transistors , and O, are having large Py then

and the base currents of transistors Q and

Q4 are equal, with a value of /(B+1) /B, where P
=

the B of pnp transistors Q3 and O4

The 741
1C OP-AMP
61
The current mirror formed by Qg and
we can express the output curTent of the
Q, is fed by an input current of 2/. Using the equation (1.27),
mirror.
21
2 ..(2.4)
1+
p

REF lc1o

+
Q10
VBE11 VBE10

Ic10 R4 R4
VEE

Fig. 2.6

*
Vcc

21

| 21
J
I+2/BpP o
Q4

21/Pp
X

Fig. 2.7 DC analysis of the 741 input stage

62 Integrater Cttun

Write a node equation at node X as shown in Fig. 2.7 and thus determine value aof I whe
the value
Can
P>1 then the equation (2.4) gives
2
25
1+

c1o +0
1

C121

I= ICio
2
9.5 uA, thus we that determine
For Co= 19 uA; I =lcid2;

2.6

loop feedback which stabilizes the val

of
Q, through Q4. Og and Q, form a negative
The transistors
at approximately Icio2. Fig. 2.8 shows the remaining part of the 741 input stage.

Ics=I IcA=I

Q7 Q16
=0 TB160
21
PN
=I
V

IPN /BN

R R

VEE
Fig. 2.8 DG analysis ef the 741 input stage (eentinued)
The 741 IC
OP-AMP 63

If we neglect the base current of . then

Similarly, we neglect the base current of O. then we obtain

The bias current of Q, can be detemined from

2 ..(2.7)

From Fig. 2.8, the voltage at node Y

V= VBE6 + IR ...(2.8)
Substituting equation (2.8) in equation (2.7)

2BE6+IR2 ..(2.9)
IcEP R3
where B denotes B of the npn transistors. To determine VRE We use the transistor exponential relationship
I
.(2.10)
BE6Vn
Substituting Is = 1071A, I = 9.5 uA and Vr 25 mV in equation (2.10), we get BE6

BE625x10-3 In95x10-6
10-14

BEG0.517 =517 mA ...(2.11)

Substituting VBE6 value in equation (2.9) to get Icq

2x9.5x106 517x103 +9.5x10x1x103

ICT 200 50x103

= 9.5 x 108+1.053 x
10
c 10.6 HA

2.3.3 Input Bias and Offset Currents

Input Bias Current
terminals is called input bias
flowing into the op-amp input
The average value of the two currents

current and denoted as

.(2.12)
2
21
We know that
64 Integrated Circui
then the equation (2.12) becomes
..2.13
bias current
From device parameters By= 200 and I =9.5 HA, therefore input
9.5 x10 47.5 nA
200
The bias current 1, is small for an op-amp constructed using BJT and it is reduced further by op-amm

constructed using FET.

Input Offset Current

The input currents of op-amp are the base currents of two transistors , and , used in the input stage
must be equal. But practically the tw
ldeally Q, and Q, must be perfectly matched and two currents
two transistors.
input base currents differ by a small amount due to mismatch of
The algebraic difference between the currents flowing into the two input terminals of the op-amp i-
called input offset current and denoted as Ios Mathematically it is expressed as,

os 1B1-Ip2|
where lp1 currententering into non-inverting input terminal
IR2current entering into inverting inputterminal

2.3.4 Input Offset Voltage

Whenever both the input terminals of the op-amp are grounded, ideally the output voltage should b
zero. However, in this condition, practical op-amp shows a small non-zero output voltage. To make thi
output voltage zero, a small voltage in millivolts is applied to one of the input terminals. Such voltag
makes the output exactly zero.
The additional de voltage applied to the one of input terminals which makes the output voltage zer
when the other terminal is grounded is called input offset voltage denoted as Vos Fig. 2.9 shows th
concept of input offset voltage.
IntheIC 741 op-amp, the input ofset voltage is due to mismatches between Q, and 0, between
and Q4, between O, and , and between R, and R
ldeal op-amp Practical op-amp
Vdc1

os
Zero volt
output is zero
Vdc2
additional dc voltage
applied to make output
as zero

Fig. 2.9 Concept of input offset

voltage
 IC OP-AMP
The 741 65

2.3.5 Input Common-Mode Range

The input common-mode range is the range of input common-mode (same input signal) voltages over
which the input stages remains in the linear active mode.

2.3.6 Second Stage Bias

Figure 2.10 shows the second stage of 741 op-amp. If we neglect the base current of Oz. then the
collect current of Q17 is approximately equal to the current supplied by source 213

Q12 Q138

REF Ic138 0.75 IREF

Q23
Ic17 Ic138
Q16
V Q17
B17

lEe59 Ka 59 k
LE17 Ra 100 kQ

Fig. 2.10 Second stage bias

The transistor Q 1R has scaled current 0.75 times that of Q12, its collector current will be
C1380.75 JREF Where we assumed that P, >> 1.
We know that p r E = 0.73 mA, the collector current of 1 3 8 is Ici3B = 0.75 pEE 5 5 0 uA. The

base-emitter voltage of Q17 1s

BE17 Vr In Cz ...(2.14)
IS17
From the device
parameters
BE1725 mV ln 0uA
10-14A
 Integrated Circuit
66
Fig. 2.10.
The collector current of Q1, can be determined from

..2.15)
IC16E16B17 Ra
substitute in equation (2.15)
Voltage at node x, BE17 t Ig17 Rg and

C16E16=Ip17
+ BEI7tE17g 2.16
Ro
negligible compared to
the input-stage bias I.
Note that the base current of Q1 will be

2.3.7 Output Stage Bias

short-circuit protection the current source of
Figure 2.ll showsthe output stage of 741 without the
transistor 13A provides a current of 0.25 IRET (because Is
of Q13A is 0.25 times the Ig of Q1) to the
circuit composed of Q18 219 and Rjo
current) of Q14 and Q9n then the
neglect the base currents
If we (very small compare to collector
IRE
to 0.25 Thus
emitter current of Q23 will also be equal
c23E23 0.25 REF= 180 uA

+Ncc

Q13A
0.25 IREF
Q14

Q19

Q18 o 0V

R10 4 0 kQ

0.25 IREF
Q20

NeE

Fig 2.11 The 741 output stage without the short circuit protection
 67
IC OP-AMP
The 741

we see that the base current of O9 is (/B, =

180/50) 3.6 LA, which is negligible.
Thus
determine the current in Rio as 15 pAA
Ifwe assume that BEI8 iS approximately 0.6 V, we can

0.6/40 k2= 15 uA].

The emitter current of O18 is

E180.25 REF RI0

.E18180- 15 =165 uA
which is approximately equal to Icis using this current we can find VBE18

165 uA
BE18Vn C18 25 mV In
10-14
Is1s
BE18588 mV
(= 0.6 V). The base current of Q1s is (ABy=
165 uA/200) 0.8 uA
which is close to the value assumed
in determine the Q19 Current as
which can be added to the cunrent Ria to
C19E19 R1otB18
RIo+

= 15 +0.8

= 15.8 LA

the base-emitter function of 21 can be determined as

The voltage drop across

BE19 In c1o
Is19
2 5 mV n 15.8 uA
10-14

BEI9 530 mV
establish two VRE drops between the bases
of the output
The purpose of transistor Q1g-1g are to
Can be determined as
transistors and
24 The voltage drop
Op0 VBR
BBBE18
+
BEL9 588 + 530
VBB1.118V
the series combination of the
base-emitter junction of Q14 and Q20, we can
SinceBR appears across

write

BBVInl4+ Ic20
n C20
S14 Is20
68 Integrated Circuits
2.4 SMALL-SIGNAL ANALYSIS OF THE 741
We can analyze the small signal voltage gain ofthe 741 op-amp by dividing it into its basic circuits

2.4.1 Input Stage

input stage.
circuit of the The collectors of
, and
Figure 2.12(a) shows the equivalent
ac O, are
connected to a constant de voltage, they are replaced by ground for ac analysis and the base of O, and
common base terminal open-circuited. The differential signal v, is applied
0, is equivalent to having the
between the input terminals
Transconductance of Input Stage
From Fig. 2.12(a), the input signal appears between input terminals across four equal emitterresistances
connected in series of transistors Q1, Q,, 2, and therefore, the emitter current i, can be
Written as

.2.17)
4r
where re denotes the emitter resistances of Q1, Q Q and Q4. Thus

.(2.18)
Js the four transistors 2, through Q4 supply load current (0 i) to the active load as indicated in
Fig. 2.12(b). The input differential resistance of the op-amp can be obtained from Fig. 2.12(a).

Vi4
=(1 + B) i, 4r

Ri =4(1+B)re ...(2.19)

Figure 2.12(6) show the load circuit fed with complementary pair of current signals. Neglecting the
signal current in the base of Q, we see that the collector current of , is approximately equal to the
input current oi
The transistors Q, and 2, are identical and their bases are tied together and equal resistances
(R, =R,) are connected in their emitters, therefore the collector currents of transistors Q, and Q, must
be equal. Now consider the output node of the input stage. The output current i, is given by
i 2ai .(2.20)
The factor 2inindicates that conversion from differential to single ended is performed without losing
half thesignal. The transconductance of the input stage G,

G (2.21)
Substitute equations (2.17) and (2.20) in equation
G ai,
.(2.22)
4ie 2r
 1C OP-AMP 69
The 741

Rid

Q3

dlle

Fig. 2.12 (a)

Q1

Q4
2ai
Ro4
Ro6 Ro
aie output node of input stage.
This output is applied to input
of second stage

act as

active load-
to input stage

R Rg R

Fig. 2.12 (b) Small-signal analysis for input-stage

 Integrated Circuits
70

Output Resistance Rot

we must find its output resistance R..
circuit of 741 op-amp
lo get complete small-signal equivalent looking from collector
and Ra The resistance R6
1S

This is the resistance having components

two R of Q4 as shown in Fig. 2.12(6).
is looking from emitter terminal
terminal of Q, and resistance Rd c o m m o n bases of O, and

simplified if we assume that the

considerably
Finding these resistances is base of Q4 is at virtual ground,
the resistance Ris
that the
are at virtual ground. Assuming
Q4,
indicated as shown in Fig. 2.13(a).
common-base transistor can
be written
From Fig. 2.13(a), the output resistance of a

R4[1+8m,
.2.23)

Ro6-[1+9m Rolo

Q4

-Ro4[1 + 9m ol o

Fig. 2.13 Simplified circuits to find output resistance Ro1

the collector of Q, as shown in Fig. 2.13(6)

The resistance R is the output resistance looking into
at the base is small enough to
The base Q, is not at signal ground. We shall assume that signal voltage
be written using equation (1.55)
make this approximation is valid. The output resistance Ra can
.(2.24)
Ro6[1 +8mRr Therefore
The final output resistance Ro is the parallel combination of R4 and Ro6
.2.25
R Ra l Ro6
Small-signal equivalent circuit for input stage.
Figure 2.14 shows the equivalent cireuit that we have derived for the input stage.

+0- -o Cs

RaV Gm1Vi Rot

-0

Fig. 2.14 Small signal equivalent circuit for the input stage of the 741 op-amp
The 741 IC OP-AMP
71

2.4.2 Second Stage or Gain Stage

Figure 2.15 shows the 741 second stage for
small-signal analysis. In this second stage, we determine
the value of the parameters of the equivalent circuit shown in Fig. 2.16.

Q138

ic17
Vi2
Q17

Re
Ri17
Fig. 2.15 741 second stage for small signal analysis

B16 O
O C17

Vi2 R2 ( Gm2 Vi2 Ro2

Fig. 2.16 Small-signal equivalent circuit of the second stage

Input resistance (R
Figure 2.17 shows the equivalent circuit to find input resistance.

From Fig. 2.17

R17 (P17+ ) Cnt R) .(2.26)
Based on the impedance reflection rule ((B+ 1) times of resistance appear in emitter terminal)
R2 (Pi6+ 1) Va6 t (R, l R7
(P16+ 1) Vel6 t (R, l (B7
-
+ 1) .17 t
R))) (2.27)
 72
Integrated Circuit

ic17

e16

e17
R
8
it is written based on the
impedance reflection rule

R17 (P17+ 1) (Ce17 + Ra

Ri2

Fig. 2.17 Equivalent circuit to determine input resistance

Output Resistance (R,

To determine the output resistance R of the second stage is shown in Fig. 2.18. We ground input
terminal and find the resistance looking back into the output terminal.

Q13 Ro17
-Ro13 Ro2

e16 e16
Q17

Rg
,Re Re
Rs

Fig. 2.18 Equivalent circuit to determine the output resistance R2

From the Fig. 2.18, the output resistance R, is the parallel combination of resistance Ro17 and
Ro2 R17 | Ri3 . 2.28
 OP-AMP
741 IC
The 73
FromFig. 2.18(6), the output resistance R17 can be written using equation (1.55)

Ro17Pe17 [1+ 8 R ..(2.29)

where R e17 +R) || R, I| 'e16
Erom Fig. 2.18(a), the output resistance R,1 can be written as

Ro13 ol3 .2.30)

Transconductance

The transconductance G2 1s the ratio of the short-circuit output current to the input voltage. Short-
circuiting the output terminal of the second stage as shown in Fig. 2.15, to ground make the signal
curent through the output resistance of O13B zero. The output short-circuit current becomes equal to
the collector current of 17 (ic7).

i11 CVb17 ..(2.31)

Tel7 + Rg

Apply voltage divider rule in Fig. 2.15 to get v7

Vb17
Rll R7 ..(2.32)
2 (R, ||R17) +rel6

2.4.3 Output Stage

Figure 2.19 shows the 741 output stage without short-circuit-protection circuitry. The stage is shown
driven by the second-stage transistor Q17 and loaded with a 2 k2 resistance. In the output stage
contains class-AB amplifier composed of 218 219 and Rio providing the bias of the output transistors
4 and Q20

Output Voltage Limits

emaximum positive output voltage is limited by the saturation of current-source transistor Q13A
Thus

o max ccCEsati3BE14 .(2.33)

ch
about 1 V below Vep The minimum output voltage (i.e. maximum negative amplitude) is
y the saturation of 2 7 . Neglecting the voltage drop across Rg. We obtain

..(2.34)
omin-EECEsat *BE23 BE20
which is about 1.5 V
above -

VgE
VEE
 Integrated Circuits
74

+Vcc
Q13A

a14

Out
O-
Q18
VRL2 k
Ri0

Q20

B2

Q17 NEE
Re
Output stage-

Fig. 2.19 741 output stage

2.4.4 Small-Signal Model

shown
stage of 741 op-amp
as shown in Fig. 2.20. The model is
The small-signal model of output second stage.
which is two open-circuit output voltage of
by va2
The output of second stage
o2-2R2 Va

Rout Out
Ro2 B23

Vo
i3Rin3 GvoVo2

Fig. 2.20 Model for the 741 output stage

The 741
IC OP-AMP 75

where G and R, determined from the second stage of 741 op-amp. Resistance Rns is the input
resistance of the output stage determined with the amplifier loaded with R. The voltage gain of the
second A, as

RinRo2
Av3-Gm22 Rnt+
The input resistance Rns looking into the base of 220 is approximately B20 R This resistance
appears in parallel with the series combination of the output resistance of 13A and the resistance of the
1 s 1 9 network.

Rin3P23 Rz | o13A
Rin3P23Rz
Output Resistance (Rou?
The output resistance of the op-amp Rout is determined from the Fig. 2.21. In accodance with the
definition of Raut the input source feeding the output stage is grounded, but its resistance is included.
We have assumed that the output voltage v, is negative and thus Q20 is conducting most of the
current; transistor 4 has therefore been eliminated. The exact value of the output resistance will
depend on which transistor (14 or P20) is conducting and on the value of load current

Q13A
o13A

Q19

Q18
Ro Ro23
Large resistance
Route20* B20+1
Q20

Ro2 Ro2
Ro23B23+1+e23
Fig. 2.21 Circuit for determining the output resistance
 76 Integrated Circuth
The resistance see looking into the emitter of Ø, is

R,23 B23+1Ro2Te23 .2.35

This resistance appcars in parallel with the series combination of r,13A and the resistance (0.-0
network. Since r3A alone is larger than Ra3. the cffective resistance between the base of 0 a
and
ground approximately to Ra23, the output
resistance Rou as

Rout Ro23+Te20
B20 +1
..(2.36
The output resistance of the 741l is specified to be typically 75 .
OF THE 7441
2.5 GAIN, FREQUENCY RESPONSE AND SLEW RATE
The overall small-signal voltage gain ofthe 741 op-amp.

2.5.1 Small-signal Gain

The overall small-signal gain can be determined from the cascade of equivalent circuits as shown in
Fig. 2.22. The load resistance R, is typically 2 k2 (based on the 741 data sheet)

Ro2 Rout

m1 i
Ro1 Vi2R2 VisRin3 Gvos Vo2 VoRL
Vo2-Sm2 Ro2 Vi2
O-

Fig. 2.22 Cascading the small-signal equivalent circuits

From Fig. 2.22, the overall gain can be expressed

2 Vo2 ..(2.3
i VVi2 Yo2

A-(R G R, R+Rout
2.38
A | R) Em2 R) R

2.5.2 Frequency Response

The 741 is an internally compensated op-amp. It employs the Miller compensation technique introdu
a dominant low frequency pole. Typically a 30 pF capacitor (Cc) is connected in the negative teeu
path of the second stage as shown in Fig. 2.2.
 IC OP-AMP
The 741
77
tIsing Miller theorem, the effective capacitance due to C between the base of Q1 and ground is
CinCc(1 +142) .2.39)
schere A, is thesecond-stage gain. Since the capacitance C is quite
large, webetween
eanacitances between the base of Q16 and signal ground. The total resistance
shall neglect all other
this node and
c
ground is

R,-(Ro l R) .(2.40)
Thus the dominant pole has a
frequency fp given by

Ip 21T Cin R .(2.40)

Assuming that all non-dominant are at high frequencies, the calculated values give rise to two Bode
plot shown in Fig. 2.23, where s34B =Sp

The unity-gain bandwidth f, can be calculated from

...(2.42)
AI (dB) A

Ao

-20 dB/decade

f3dB fAo fadB

Fig. 2.23 Frequency response of op-amp

2.5.3 Simplified Model of op-amp

Fgure 2.24 shows a simplified model of the 741 op-amp in which the high-gain second stage with its
Teedback capacitance Cis modeled by an ideal integrator.
ne gain of two second stage is assumed sufficiently large and a virtual ground appears at its input.
Or this reason the output resistance of the input stage and the input resistance of the second stage have
OEen
omitted. Furthermore, the output stage is assumed to be an ideal unity-gain follower.
 Integrated Cire
78

Unity gain amplifier

oV

Vo
(Gm Vi

the 741 op-amp

Fig. 2.24 Simplified model for

From Fig. 2.24

V,S)G .2.4
A(5)=V(S) sCc
replace s byjo
..(24
A(jw) =
G
joCc
and the magnitude of gain
becomes unity at o = ,
..(2.4
Cc

2.5.4 Slew Rate

2.25 with a step input. The
slew rate (SR) 1s|
Consider two unity-gain follower as shown in Fig. Slew rate is a mea
unit time, it is measured in V/usec.
maximum rate ofrise of the output voltagecan
per
in input signal.
of how quickly the output of an op-amp
change for a corresponding change

time
It will take some
to reach maximum

10V output
Vo
M 0

Fig. 2.25 Unity gain amplifier with step input

 IC OP-AMP 79
The 741

Modeling the second stage as an ideal integrator as shown in Fig. 2.24. The slew rate is caused due
tolimited charging rate ofthe compensating capacitor and current limiting and saturation of the internal
taoes of an op-amp, when a high frequeney, large amplitude signal is applied. The internal capacitor
stages
voltage cannot change mstantaneously. It is given by

ded ..(2.46)
From this cireuit, the output voltage will be

v.)= .(2.47)
Thus the slew rate (SR) is given by

SR = )_2/
d .(2.48)
Cc
2.5.5 Relationship Between f, and SR
A simple relationship exists between the unity-gain bandwidth f, and the slew rate SR.

.2.49)

SR
2
=
.2.50)
Cc
The transconductance Gn is given by

G 2re .2.51)
where r is the emitter resistance of each of 0 through Q4
2.52)
I
and
G2T
Substitute equation (2.52) in equation (2.51)
..(2.53)

o,Cc2Vr
..(2.54)
02CcVr
Substituting for I/C, in equation (2.54)
SR
.2.55)
or
AVT
SR 40,VT ..(2.56)
F
given
reduced. This
o, a higher value of SR is obtained, the total bias current is kept constant and G, is
is a viable technique for increasing slew rate.