Lecture 1:

Circuits &
Layout
 Outline
❑ A Brief History
❑ CMOS Gate Design
❑ Pass Transistors
❑ CMOS Latches & Flip-Flops
❑ Standard Cell Layouts
❑ Stick Diagrams

1: Circuits & Layout CMOS VLSI Design 4th Ed. 2

 A Brief History
❑ 1958: First integrated circuit
– Flip-flop using two transistors
– Built by Jack Kilby at Texas
Instruments
❑ 2010 Courtesy Texas Instruments

– Intel Core i7 μprocessor

• 2.3 billion transistors
– 64 Gb Flash memory
• > 16 billion transistors
[Trinh09]
© 2009 IEEE

1: Circuits & Layout CMOS VLSI Design 4th Ed. 3

 Growth Rate
❑ 53% compound annual growth rate over 50 years
– No other technology has grown so fast so long
❑ Driven by miniaturization of transistors
– Smaller is cheaper, faster, lower in power!
– Revolutionary effects on society

[Moore65]
Electronics Magazine

1: Circuits & Layout CMOS VLSI Design 4th Ed. 4

 Annual Sales
❑ >1019 transistors manufactured in 2008
– 1 billion for every human on the planet

1: Circuits & Layout CMOS VLSI Design 4th Ed. 5

Invention of the Transistor
❑ Vacuum tubes ruled in first half of 20th century
Large, expensive, power-hungry, unreliable
❑ 1947: first point contact transistor
– John Bardeen and Walter Brattain at Bell Labs
– See Crystal Fire
by Riordan, Hoddeson

AT&T Archives.
Reprinted with
permission.

1: Circuits & Layout CMOS VLSI Design 4th Ed. 6

 Transistor Types
❑ Bipolar transistors
– npn or pnp silicon structure
– Small current into very thin base layer controls
large currents between emitter and collector
– Base currents limit integration density
❑ Metal Oxide Semiconductor Field Effect Transistors
– nMOS and pMOS MOSFETS
– Voltage applied to insulated gate controls current
between source and drain
– Low power allows very high integration

1: Circuits & Layout CMOS VLSI Design 4th Ed. 7

 MOS Integrated Circuits
❑ 1970’s processes usually had only nMOS transistors
– Inexpensive, but consume power while idle

Intel
Museum.
[Vadasz69]
Reprinted
© 1969 IEEE. with
permission.

Intel 1101 256-bit SRAM Intel 4004 4-bit μProc

❑ 1980s-present: CMOS processes for low idle power

1: Circuits & Layout CMOS VLSI Design 4th Ed. 8

 Moore’s Law: Then
❑ 1965: Gordon Moore plotted transistor on each chip
– Fit straight line on semilog scale
– Transistor counts have doubled every 26 months

Integration Levels
SSI: 10 gates
MSI: 1000 gates
LSI: 10,000 gates
VLSI: > 10k gates
[Moore65]
Electronics Magazine

1: Circuits & Layout CMOS VLSI Design 4th Ed. 9

 And Now…

1: Circuits & Layout CMOS VLSI Design 4th Ed. 10

 Feature Size
❑ Minimum feature size shrinking 30% every 2-3 years

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 Corollaries
❑ Many other factors grow exponentially
– Ex: clock frequency, processor performance

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 CMOS Gate Design
❑ Activity:
– Sketch a 4-input CMOS NOR gate

1: Circuits & Layout CMOS VLSI Design 4th Ed. 13

 Complementary CMOS
❑ Complementary CMOS logic gates
– nMOS pull-down network
– pMOS pull-up network
– a.k.a. static CMOS

Pull-up OFF Pull-up ON

Pull-down OFF Z (float) 1

Pull-down ON 0 X (crowbar)

1: Circuits & Layout CMOS VLSI Design 4th Ed. 14

 Series and Parallel
❑ nMOS: 1 = ON
❑ pMOS: 0 = ON
❑ Series: both must be ON
❑ Parallel: either can be ON

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Conduction Complement
❑ Complementary CMOS gates always produce 0 or 1
❑ Ex: NAND gate
– Series nMOS: Y=0 when both inputs are 1
– Thus Y=1 when either input is 0
– Requires parallel pMOS

❑ Rule of Conduction Complements

– Pull-up network is complement of pull-down
– Parallel -> series, series -> parallel

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 Compound Gates
❑ Compound gates can do any inverting function
❑ Ex:

1: Circuits & Layout CMOS VLSI Design 4th Ed. 17

 Example: O3AI
❑

1: Circuits & Layout CMOS VLSI Design 4th Ed. 18

 Signal Strength
❑ Strength of signal
– How close it approximates ideal voltage source
❑ VDD and GND rails are strongest 1 and 0
❑ nMOS pass strong 0
– But degraded or weak 1
❑ pMOS pass strong 1
– But degraded or weak 0
❑ Thus nMOS are best for pull-down network

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 Pass Transistors
❑ Transistors can be used as switches

1: Circuits & Layout CMOS VLSI Design 4th Ed. 20

 Transmission Gates
❑ Pass transistors produce degraded outputs
❑ Transmission gates pass both 0 and 1 well

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 Tristates
❑ Tristate buffer produces Z when not enabled

EN A Y
0 0 Z
0 1 Z
1 0 0
1 1 1

1: Circuits & Layout CMOS VLSI Design 4th Ed. 22

 Nonrestoring Tristate
❑ Transmission gate acts as tristate buffer
– Only two transistors
– But nonrestoring
• Noise on A is passed on to Y

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 Tristate Inverter
❑ Tristate inverter produces restored output
– Violates conduction complement rule
– Because we want a Z output

1: Circuits & Layout CMOS VLSI Design 4th Ed. 24

 Multiplexers
❑ 2:1 multiplexer chooses between two inputs

S D1 D0 Y
0 X 0 0
0 X 1 1
1 0 X 0
1 1 X 1

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 Gate-Level Mux Design
❑
❑ How many transistors are needed? 20

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 Transmission Gate Mux
❑ Nonrestoring mux uses two transmission gates
– Only 4 transistors

1: Circuits & Layout CMOS VLSI Design 4th Ed. 27

 Inverting Mux
❑ Inverting multiplexer
– Use compound AOI22
– Or pair of tristate inverters
– Essentially the same thing
❑ Noninverting multiplexer adds an inverter

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 4:1 Multiplexer
❑ 4:1 mux chooses one of 4 inputs using two selects
– Two levels of 2:1 muxes
– Or four tristates

1: Circuits & Layout CMOS VLSI Design 4th Ed. 29

 D Latch
❑ When CLK = 1, latch is transparent
– D flows through to Q like a buffer
❑ When CLK = 0, the latch is opaque
– Q holds its old value independent of D
❑ a.k.a. transparent latch or level-sensitive latch

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 D Latch Design
❑ Multiplexer chooses D or old Q

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 D Latch Operation

1: Circuits & Layout CMOS VLSI Design 4th Ed. 32

 D Flip-flop
❑ When CLK rises, D is copied to Q
❑ At all other times, Q holds its value
❑ a.k.a. positive edge-triggered flip-flop, master-slave
flip-flop

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 D Flip-flop Design
❑ Built from master and slave D latches

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 D Flip-flop Operation

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 Race Condition
❑ Back-to-back flops can malfunction from clock skew
– Second flip-flop fires late
– Sees first flip-flop change and captures its result
– Called hold-time failure or race condition

1: Circuits & Layout CMOS VLSI Design 4th Ed. 36

 Nonoverlapping Clocks
❑ Nonoverlapping clocks can prevent races
– As long as nonoverlap exceeds clock skew
❑ We will use them in this class for safe design
– Industry manages skew more carefully instead

1: Circuits & Layout CMOS VLSI Design 4th Ed. 37

 Gate Layout
❑ Layout can be very time consuming
– Design gates to fit together nicely
– Build a library of standard cells
❑ Standard cell design methodology
– VDD and GND should abut (standard height)
– Adjacent gates should satisfy design rules
– nMOS at bottom and pMOS at top
– All gates include well and substrate contacts

1: Circuits & Layout CMOS VLSI Design 4th Ed. 38

 Layout Design Rules
A conservative but easy-to-use set of design rules for layouts with two
metal layers in an n-well process is as follows:

1.Metal and diffusion have minimum width and spacing of 4 λ .

2.Contacts are 2 λ × 2 λ and must be surrounded by 1 λ on the layers
above and below.
3.Polysilicon uses a width of 2 λ .
4.Polysilicon overlaps diffusion by 2 λ where a transistor is desired and
has a spacing of 1 λ away where no transistor is desired.
5.Polysilicon and contacts have a spacing of 3 λ from other polysilicon
or contacts.
6.N-well surrounds pMOS transistors by 6 λ and avoids nMOS
transistors by 6 λ .

1: Circuits & Layout CMOS VLSI Design 4th Ed. 39

 Example

1: Circuits & Layout CMOS VLSI Design 4th Ed. 40

 Example: Inverter

1: Circuits & Layout CMOS VLSI Design 4th Ed. 41

 Example: NAND3
❑ Horizontal N-diffusion and p-diffusion strips
❑ Vertical polysilicon gates
❑ Metal1 VDD rail at top
❑ Metal1 GND rail at bottom
❑ 32 λ by 40 λ

1: Circuits & Layout CMOS VLSI Design 4th Ed. 42

 Stick Diagrams
❑ Stick diagrams help plan layout quickly
– Need not be to scale
– Draw with color pencils or dry-erase markers

1: Circuits & Layout CMOS VLSI Design 4th Ed. 43

 Wiring Tracks
❑ A wiring track is the space required for a wire
– 4 λ width, 4 λ spacing from neighbor = 8 λ pitch
❑ Transistors also consume one wiring track

1: Circuits & Layout CMOS VLSI Design 4th Ed. 44

 Well spacing
❑ Wells must surround transistors by 6 λ
– Implies 12 λ between opposite transistor flavors
– Leaves room for one wire track

1: Circuits & Layout CMOS VLSI Design 4th Ed. 45

 Area Estimation
❑ Estimate area by counting wiring tracks
– Multiply by 8 to express in λ

1: Circuits & Layout CMOS VLSI Design 4th Ed. 46

 Example: O3AI
❑ Sketch a stick diagram for O3AI and estimate area
–

1: Circuits & Layout CMOS VLSI Design 4th Ed. 47