Nyquist-rate vs.

oversampling data converters

• Nyquist-rate converters operate with clock frequencies close to twice the

bandwidth of the analog signal (Nyquist rate) and generate output values
having a one-to-one correspondence with the input values.

Nyquist rate A/D converter

analog digital
Sampler Quantizer Coder
signal signal

Nyquist rate D/A converter

digital Smoothing analog

Decoder Interpolator
signal filter signal

ESE 553 78
 The structure of oversampling Delta-Sigma data converters

• Oversampling data converters are multi-rate systems. In the case of A/D

conversion the analog signal is sampled at much faster rates than the one
demanded by the sampling theorem and decimation is used for generating
the final digital output. For the D/A conversion, the input digital signal is
up-sampled and interpolated, the analog signal being obtained by low-pass
filtering.
Oversampling A/D converter

Digital
analog
Sampler ∆Σ modulator Coder decimation digital
signal (analog) signal
filter

Oversampling D/A converter

Digital
digital interpolation ∆Σ modulator Decoder
Smoothing analog
signal (digital) filter signal
filter

ESE 553 79
 Advantages of oversampling

• For a Nyquist-rate A/D converter SNR=10log(PS/PN)=6.02N [dB] (N
1),

N representing the resolution of the converter, in bits.
fs f
Define the oversampling ratio as R = = s
f N 2 fB
• R >> 1 eases the requirements for the anti-alias filter.
• R >>1 decreases the amount of the in-band quantization noise, therefore
increases the SNR
fs / 2
σ ε2
σ = ∫ S e ( f )df ⇒ S e ( f ) =
2
ε
− fs / 2
fs
fB
σ ε2
PN ,in −band = ∫ Se ( f )df =
− fB
R
• SNR=6.02N+10log(R) [dB] after ideal low-pass filtering at fB.
• “Plain oversampling” increases SNR with 3dB (0.5 bits) for every
doubling of the sampling frequency.

ESE 553 80
 Improving SNR in oversampling data converters

• Trade-in resolution in time with resolution in amplitude: use low-resolution

quantizers and oversampling to achieve high-accuracy digital representation
of analog signals (PCM).
• Large oversampling ratios are needed to obtain high SNR with a low
resolution quantizer if only plain oversampling is used.
• Methods to improve SNR for low oversampling ratio:
1. Signal predictive modulators:
– code a reduced range “error” signal obtained as the difference between the input
signal and its predicted value.
2. Noise shaping modulators:
– shape the spectrum of the quantization noise to reduce its in-band power.

ESE 553 81
 Signal predictive coding

• Signal predictive coding (∆ modulators)

e[k]
+
u[k] + y[k] u[k] + + y[k]
+ ADC + +
- -
quantization

DAC L(z) L(z)

If L(z) corresponds to an integrator and the ADC is on one bit (∆ modulator),

the signal-to-noise ratio, if slope noise does not occur, is given by:
SNR≅ ≅ 30log(R)-2.16 [dB].
Every doubling of R increasing SNR with 9dB (1.5 bits).

ESE 553 82
 Noise shaping: error feedback modulators

• Noise shaping: the spectrum of the quantization noise is shaped in such a

manner that most of its energy falls outside the band of interest
¹ Error feedback modulators
e[k]
+
u[k] + + y[k]
+ +
- Y(z)=U(z)+H(z)E(z)
quantization
-
1-H(z) + +
e[k]
• H(z) is chosen in such a manner that the in-band noise is minimized
(usually a high-pass filter).
• Disadvantage: the performances depend on the accuracy of the subtracting
block generating e[k].

ESE 553 83
 Noise shaping: ∆Σ modulators
² ∆Σ modulators e[k]
+
u[k] + y[k] u[k] + + y[k]
+
-
L(z) ADC +
-
L(z) +
quantization

DAC

L(z) 1
Y(z) = U(z) + E(z) = G(z)U(z) + H(z)E(z)
1 + L(z) 1 + L(z)
• G(z) = signal transfer function (STF)
• H(z) = noise transfer function (NTF)
The basic idea is the same as in the case of error feedback modulator. If
L(z)>>1 in the base band, then the output signal is equal to the input signal
plus a filtered (high-pass) version of the quantization noise.

ESE 553 84
 First-order ∆Σ modulator

• The filter L(z) from the general scheme is replaced by an integrator:

e[k]
+ y[k]=u[k-1]+(e[k]-e[k-1])
u[k] + z-1 + y[k] STF: G(z)=z-1
+
- 1-z-1 +
quantization NTF: H(z)=1-z-1

2
|H(ejω)|2=(2sin(ω/2))2 ≅ω2, ω«1 2
|H(e jω )|
For one bit quantizer, we have
SNR ≅30log(R)-3.41 dB
S e (ω)

π/R π ω

ESE 553 85
 Second order ∆Σ modulator
e[k]
+
u[k] + 1 + z-1 + y[k]
+ 1-z-1 + 1-z-1 +
- -
quantization

y[k]=u[k-1]+(e[k]-2e[k-1]+e[k-2])
STF: G(z)=z-1, NTF: H(z)=(1-z-1)2
|H(ejω)|2 =(2sin(ω/2))4 ≅ω4 , ω«1
In the case of one bit quantizer, SNR ≅50log(R)-11.13 dB
Doubling the sampling rate, the SNR is increased with 15dB (2.5 bits).

ESE 553 86
 Generalization to higher order

Increasing the number of integrators in the feed-forward path, the

following topology is obtained.
e[k]
+
u[k] + 1 + + 1 + z-1 + y[k]
+ 1-z-1 + + 1-z-1 + 1-z-1 +
- - - -
quantization

STF: G(z)=z-1; NTF: H(z)=(1-z-1)L

|H(ejω)|2= (2sin(ω/2))2L ≅ω2L , ω«1
For one bit quantizer,
 3(2L + 1) 
SNR = 10(2L + 1)log(R) + 10log 
 2π
2L


ESE 553 87
 Nonlinear effects in ∆Σ modulators

• The linear model for the quantizer cannot explain the entire dynamic
behavior of DS modulator. Some of the effects caused by the nonlinearity
of the quantizer and depreciating the SNR of the modulator are:
– SNR degradation for large amplitude inputs. In the case of large amplitude
inputs, the quantizer saturates and the quantization noise increases.
– Idle tones. For dc inputs (but not only) having rational values, the output of
the modulator is periodic, its spectrum having discrete components. If these
components are located inside the base band, they affect SNR.
– Dead zones. Small, fast changes in the input signal cannot be sensed by the
modulator, under certain conditions.
– Instability for DS modulators of order higher than 2.
• Because the quantizer is strongly nonlinear, DS modulators become
unstable for inputs with amplitudes above a certain value. The higher the
order, the smaller the admissible input range.

ESE 553 88
 Alternative topologies for high-order ∆Σ modulators

• Single-loop ∆Σ modulators with L-th order differentiator type NTF exhibit

poor stability due to the large gain of NTF at high frequencies.
• NTF should be a general high-pass function (simulations showed that a
high-frequency gain of approximately 3.5dB maximizes the dynamic
range).
• STF should have a frequency response corresponding to low-pass transfer
function, maximally flat to avoid signal distortion.
• An increase in SNR can be achieved if the transmission zeros of NTF are
distributed inside the signal band instead of locating all of them at dc (z=1).
• The stability problem of higher order ∆Σ modulators can be eliminated by
cascading first and/or second order modulators in order to implement more
aggressive NTFs. Multi-stage noise shaping (MASH) ∆Σ modulators are
thus obtained.

ESE 553 89
 Chain of integrators with distributed feedback

u
b1 +
-
+ ∫ +
-
+ ∫ +
-
+ ∫ +
-
+ ∫ +
+
-
∫ y

a1 a2 a3 a4 a5

CIFB topology
20
frequency response [dB]

-20

-40

-60

-80

-100

-120

-140
-2 -1 0 1
10 10 10 10
normalized frequency [rad/s]

ESE 553 90
 Chain of integrators with weighted feed-forward summation
u
b1 +
-
+ ∫ ∫ ∫ ∫ ∫

a1 a2 a3 a4 a5

-b 1 y
+
CIFF topology
20
frequency response [dB]

-20

-40

-60

-80

-100

-120

-140
-2 -1 0 1
10 10 10 10
normalized frequency [rad/s]
ESE 553 91
 Chain of resonators with distributed feedback

u
b1 +
+
- -
∫ +
-
+ ∫ +
+
- -
∫ +
-
+ ∫ +
+
-
∫ y

γ1 γ2

a1 a2 a3 a4 a5

CRFB topology
20
frequency response [dB]

-20

-40

-60

-80

-100

-120
-2 -1 0 1
10 10 10 10

normalized frequency [rad/s]

ESE 553 92
 Chain of resonators with weighted feed-forward summation
γ1 γ2
u - -
b1 +
-
+ ∫ +
+ ∫ ∫ +
+ ∫ ∫

a1 a2 a3 a4 a5

y
-b 1 +
CRFF topology
20
frequency response [dB]

-20

-40

-60

-80

-100

-120
-2 -1 0 1
10 10 10 10
normalized frequency [rad/s]
ESE 553 93
 Maximum achievable SNR
120

100

ros
ed ze
80 timiz
n-op
4, no
r5 , R =6 e d zer
os
60 orde im iz
= 32 , opt z eros
R e d
r 5, pt i m
iz
orde o n - o
SNR [dB]

32, n
40
, R =
r5
orde
20

0
oscillations
-20

-40

-60
-80 -70 -60 -50 -40 -30 -20 -10 0
input [dB]

ESE 553 94
 Waveforms and spectrum
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
time
0
-20
-40

-60
-80
-100

-120

-140

-160
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
normalized angular frequency (rad/s)
ESE 553 95
 Multistage (MASH) ∆Σ modulators

• The idea is to feed the second modulator with the quantization error of the first one and
then combine the digital outputs of the two stages in such a manner that the first
modulator error is canceled. To increase SNR, three low-order ∆Σ modulators can be
cascaded.
• Disadvantage: in the case of A/D conversion the parameters of the digital cancellation
circuitry has to match the parameters of the analog section.

y1[k]=u[k-1]+e1[k]-e1[k-1]; y2[k]=u[k-2]-e1[k-2]+e2[k]-e2[k-1] e2[k]

y[k]=u[k-2]+(e2[k]-2e2[k-1]+e2[k-2]) +
u[k-1]-e1[k-1] + z-1 +
STF: G(z)=z-2; NTF: H(z)=(1-z-1)2
+ 1-z-1 + y2[k]
-
quantization

e1[k]
+ y1[k] - + y[k]
u[k] + z-1 + + +
+ 1-z-1 + z-1 + z-1 +
-
quantization

ESE 553 96
 Band-pass ∆Σ modulators

• Used for the A/D conversion of narrow band, high frequency signals.
• In a digital radio receiver it is convenient to perform the A/D conversion
as close as possible to the front end.
digital
antena

low-pass low-pass and

DS I
decimation filter
• Classical approach RF modulator
front
using base-band ADCs end cos(ω0t)
low-pass low-pass and
DS Q
decimation filter
modulator

sin(ω0t)
digital

antena
digital

• A/D conversion low-pass and

decimation filter
I

performed at the RF front IF band-pass

DS
end cos(ω02n)
intermediate frequency modulator
low-pass and
decimation filter
Q
cos(ω01t)

digital sin(ω 02n)

ESE 553 97
 Discrete-time low-pass to band-pass transformation

• If f0 is the frequency of the modulated signal and fB is the bandwidth of the

modulating signal, the oversampling ratio is R=fs/2fB, where fs is the
sampling frequency.
• The noise transfer function of a band-pass ∆Σ modulator is a band-reject
one, whereas the signal transfer function is a band-pass one.
• Band-pass ∆Σ modulators can be obtained from low-pass ∆Σ modulators
using the low-pass to band-pass frequency transformation:
z+a
z → −z , −1 < a < 1
az + 1

• For a=0, the simplest LP to BP transformation is obtained (z-z2), the

resulting band-pass filter having the center frequency located at fs/4.

ESE 553 98
 Second-order band-pass ∆Σ modulator
This is the simplest second order ∆Σ modulator, obtained through LP to BP
transformation from the first order low-pass ∆Σ modulator.
e[k] e[k]
+
u[k] + 1 y[k] u[k] + 1 + y[k]
+ 1+z 2 + 1+z 2 +
+ + quantization

10

NTF: H (z ) = 1 + z
−2 0

STF: G (z ) = z − 2
-10

-20

-30

-40

-50 -2 -1 0
10 10 10
angular frequency (rad/s)

ESE 553 99
 Optimized 2nd order band-pass ∆Σ modulator

2 e[k]
+
u[k] + - 1 + z-1 + y[k]
+ 1-z-1 + 1-z-1 +
2/3 + -
quantization
2/3 2/3

10

z +1 2
NTF: H ( z ) = 3 -10
3z 2 + 1
-20

STF: G (z ) = 2
2z
3z + 1 -30

-40

-50
10 -2 10 -1 10 0
angular frequency (rad/s)

ESE 553 100

 Implementation of analog ∆Σ modulators
• Discrete time implementations. The integrators within the loop filter are
realized using one of the approaches:
– Switched capacitor
– Switched op-amp
– Switched current
• Continuous-time implementations. The loop filter is build using either:
– Active-RC integrators
– OTA active-C integrators
– OTA-C integrators
• Continuous-time ∆Σ modulators require a sample-and-hold circuit
u u
Discrete Continuous
time A/D time S/H A/D
y y
filter filter

D/A D/A

ESE 553 101

 Switched-capacitor circuits
• Switched-capacitor simulation of a resistor
• Assume the clock frequency is much larger than the frequency of the
analog signals, therefore v1 and v2 are constant over a clock cycle
φ1
φ1 φ2
∆qT (t ) = C [v1 (t ) − v2 (t )]
∆qT (t ) C
v1 C v2 φ2 t t+T/2 t+T t i (t ) = = [v1 (t ) − v2 (t )]
T T
T 1
Req = =
t t+T/2 t+T t C fC
• Switched-capacitor integrator C2
- phase φ1: vC (t ) = u (t ); y(t ) = vC (t ) φ1 φ2 - +
φ
1 2

  T u 1 y
v
 C1  t +  = 0 +
  2 C1
- phase φ2:  -
C v  t + T  = C v (t ) − C v (t )
 2 C2  2  Y (z )
H (z ) =
2 C2 1 C1 C 1
=− 1
U (z ) C2 z − 1
 T
- phase φ1: y (t + T ) = vC2 (t + T ) = vC2  t +  = y (t ) − u (t )
C1
 2 C2

ESE 553 102

 Switched-capacitor integrators insensitive to stray capacitances
• Non-inverting integrator with delay
C2
vC1 (t ) = u (t ) φ1 C1 φ2 - +
- phase φ1: 

+ - φ1
 y (t ) = vC2 (t )
u y
φ2 φ1

  T
vC1  t + 2  = 0
   Y (z ) C1 1
- phase φ2: 
H ( z ) = =
C v  t + T  = C v (t ) + C v (t ) U ( z ) C2 z − 1
 2 C2
 2
2 C2 1 C1

 T
- phase φ1: y (t + T ) = vC2 (t + T ) = vC2  t +  = y (t ) + u (t )
C1
 2 C2

• Delay-free inverting integrator

C2
φ1 C1 φ1 - +
Y (z ) + - φ1
H (z ) =
C z
=− 1 u y
U (z ) C2 z − 1 φ2 φ2

ESE 553 103

 Switched-capacitor realization of ∆Σ modulators

Second-order switched-capacitor low-pass ∆Σ modulator

delay-free integrator
integrator with delay
C
φ1 C φ1 C
u φ1 C φ2
latched
φ2 φ2
φ2 φ1 comparator y
φ1

Vref -Vref Vref -Vref

2 2 2 2

ESE 553 104

 Continuous-time realization of ∆Σ modulators

Continuous-time integrators
C C
R vin vin vout
vin vout Gm vout Gm
C

active-RC OTA active-C OTA-C (Gm-C)

First-order continuous-time ∆Σ modulator

C
u
Gm latched
comparator y
Clk

-VSS VDD
GmVref GmVref
2 2

ESE 553 105

 Continuous-time vs. switched-capacitors implementations

• Easy to breadboard • Easily simulated

• Less prone to pick-up digital noise • Compatible with VLSI CMOS process
• Easy to drive from external sources since • Insensitive to clock jitter and shape of op-
the SC current pulses are absent amp settling waveform (if full settling
• S/H circuit is inside the loop, thus the errors occurs)
introduced by its non-idealities are shaped • Loop filter parameters are set by capacitor
as the quantization noise ratios (highly accurate)
• Higher frequency range • No need for a separate S/H circuit
• Needs large capacitors, linear resistors, low- • Large capacitors required for high SNR
noise and linear op-amps (kT/C noise limit)
• Loop filter parameters are set by RC (C/Gm) • Large spike currents drawn by capacitors
time constants (not so accurate without are hard to drive from external sources
trimming or tuning) • SC circuits are true samplers and may cause
• Sensitive to clock jitter and shape of the 1 alias of out of band noise. More prone to
bit feedback waveform picking up digital noise.
• Loop filter does not scale with clock • Difficult to prototype because capacitor
frequency values are small, comparable with parasitic
• Discrete-time simulation is more difficult capacitances on a breadboard.

ESE 553 106