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8085 Instructions - Instruction Set of 8085 Microprocessor - MHE - Microprocessors and Microcontrollers

The document provides a comprehensive overview of the 8085 microprocessor instruction set, categorized into data transfer, arithmetic, logical, branch, stack, and I/O instructions. Each category includes specific instructions with their operations and effects on registers and memory. Additionally, it details the functionality of jump, call, return, and stack manipulation instructions.

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0% found this document useful (0 votes)
7 views14 pages

8085 Instructions - Instruction Set of 8085 Microprocessor - MHE - Microprocessors and Microcontrollers

The document provides a comprehensive overview of the 8085 microprocessor instruction set, categorized into data transfer, arithmetic, logical, branch, stack, and I/O instructions. Each category includes specific instructions with their operations and effects on registers and memory. Additionally, it details the functionality of jump, call, return, and stack manipulation instructions.

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8085 Instructions

Data Transfer Instructions


MOV Rd,Rs (Move the content of the source register to the destination register)
Rd←Rs,

MOV M, Rs (Move the content of the source register to the memory)


[M]←Rs,

MOV Rd, M (Move the content of the memory to the destination register)
Rd←[M],

MVI Rd, data (Move immediate 8-bit data to the register)


Rd←data,

MVI M, data (Move immediate data to memory)


[M]←data,

LDA 16­bit address (Load Accumulator direct)


A←[16-bit Address].

LDAX B/D Register pair (Load Accumulator Indirect)


A←[BC] or A←[DE]

LXI Register pair, 16­bit data (Load register pair immediate)


Register pair ←16 bits data, Rh←8 MSBs, Rl←8 LSBs of data.

LHLD 16­bit address (Load H and L registers direct)


L ←[address], H←[address+1].

STA 16­bit address (Store accumulator direct)


16-bit Address ←A,

SHLD 16­bit address (Store H and L pair registers direct)


[address]←L, [address +1]←[H].

XCHG (Exchange the contents of H and L with D and E)


H↔D, L↔E
Table: 8085 Data-transfer instructions set summary

Comment
Arithmetic Instructions

ADD R (Add register to accumulator)


A←A + R,

ADD M (Add memory to accumulator)


A←A+ [M],

ADC R (Add register to accumulator with carry)


A←A + R+CS,

ADC M (Add register to accumulator with carry)


A←A + M+CS,

ADI 8­bit data (Add immediate 8-bit data to accumulator)


A←A + data,

ACI 8­bit data (Add immediate 8-bit data to accumulator with carry)
A←A + data + CS,

DAD Register pair (Add register pair to H and L registers)


H–L←H–L + Register pair.

SUB R (Subtract register from accumulator)


A←A – R,

SUB M (Subtract memory from accumulator)


A←A – [M]

SBB R (Subtract register from accumulator with borrow)


A←A – R – CS.

SBB M (Subtract memory and borrow from accumulator)


A←A – [M] – CS.
SUI 8­bit data (Subtract immediate 8-bit data from accumulator)
A←A – 8-bit data.

SBI 8­bit data (Subtract immediate 8 bit data from accumulator with borrow)
A←A – 8-bit data -CS.

INR R (Increment register by 1)


R←R + 1

INR M (Increment memory by 1)


[M]←[M] +1

INX RP (Increment register pair)


RP←RP+1

DCR R (Decrement register bt 1)


R←R-1

DCR M (Decrement memory by 1)


[M]←[M] – 1

DCX RP (Decrement register pair by 1)


RP←RP-1,

DAA (Decimal adjust accumulator)


Machine cycles: 1, States: 4, Flags: all, one byte instruction

Table: 8085 arithmetic instruction set summary


Comment

Logical Instructions
CMP R (Compare register with accumulator)
A – R.

CMP M (Compare memory with accumulator)


A – [M]
CPI 8 ­ bit data (Compare immediate 8 bit data with accumulator)
A – 8-bit data.

ANA R (Logical AND register with accumulator)


A←A ∧ R

ANA M (Logical AND memory with accumulator)


A←A ∧ [M].

ANI 8­bit data (Logical AND immediate 8-bit data with accumulator)
A←A ∧ 8-bit data

ORA R (Logical OR register with accumulator)


A←A ∨ R

ORA M (Logical OR memory with accumulator)


A←A ∨ [M].

ORI 8­bit data (Logical OR immediate 8-bit data with accumulator)


A←A ∨ 8-bit data.

XRA R (EXCLUSIVE-OR register with accumulator)


A←A⊕R

XRA M (EXCLUSIVE – OR memory with accumulator)


A←A⊕[M]

XRI 8­bit data (EXCLUSIVE - OR immediate 8-bit data with accumulator)


A←A⊕data

RLC (Rotate accumulator left)


An+1←An, A0←A7, CS←A7

RRC (Rotate accumulator right)


A7←A0, CS ←A0, An←An+1

RAL (Rotate accumulator left through carry)


An+1←An, CS←A7, A0←CS

RAR (Rotate accumulator right through carry)


An ←An+1, CS←A0, A7←CS

CMA (Complement the accumulator)


A← A

CMC (Complement the carry)


CS←CS Machine cycles: 1, States: 4, Flags: CS, One-byte instruction

STC (Set the carry)


CS←1 Machine cycles: 1, States: 4, Flags: CS, One-byte instruction

Table : 8085 logical instruction set summary

Comment

Branch Group
JMP 16­bit address (Jump Unconditionally)
PC←Label (16-bit address)

Conditional Jump 16­bit address (Jump Conditionally)


In the conditional jump instruction, the program sequence is transferred to the
memory location specified by the 16-bit address given in the operand based on the
specified flag of the PSW. All conditional jump instructions are given below:

JC 16­bit address (Jump on carry)


PC←16-bit address, jump if CY = 0.

JNC 16­bit address (Jump on no carry)


PC←16-bit address, jump if CY = 0.

JP 16­bit address (Jump on positive)


PC←16-bit address, jump is S = 0.

JM 16­bit address (Jump on minus)


PC←16-bit address jump if S = 1.

JZ 16­bit address (Jump on zero)


PC←16-bit address jump if Z=1.

JNZ 16­bit address (Jump on no zero)


PC←16-bit address jump if CS = 1.

JPE 16­bit address (Jump on even parity)


PC←16-bit address (jump if even parity)

JPO 16­bit address (Jump on odd parity)


PC←16-bit address; the parity status P = 0,

CALL 16­bit address (Unconditional subroutine CALL)


([SP] – 1) ←PCH , ([SP]-2)←PCL,
[SP]←[SP]-2, PC←16 bit address

CALL 16­bit address (CALL Conditionally)


([SP] – 1)←PCH , ([SP]-2)←PCL,
[SP]←[SP]-2, PC←16 bit address

RET (Return from subroutine unconditionally)


PCL←[SP]
PCH←[SP]+1
[SP]←[SP]+2

Conditional Return (Return from subroutine conditionally)


PCL ←[SP]
PCH ←[SP]+1
[SP] ←[SP]+2

PCHL ( Load program counter with H–L contents)


PC←H–L, PCH ←H, PCL ←L

RST 0­7 (Restart)


[SP] – 1 ←PCH, [SP] – 2←PCL
[SP] ←[SP] – 2], [PC] ←8 times n

Interrupt Instructions
The 8085 microprocessor had four additional interrupts. The interrupt instructions
and their restart addresses are
Table: 8085 JUMP instruction set summary

Table: 8085 CALL and Return instruction set summary

Comment

Stack/PUSH and POP Instructions


PUSH B (Push the content of register pair B and C to stack)
[SP] – 1←B
[SP] –2←C,
[SP]←[SP] –2

PUSH D (Push the content of register pair D and E to stack)


[SP] – 1←D
[SP] –2 ← E,
[SP]←[SP] –2

PUSH H (Push the content of register pair H and L to stack)


[SP] – 1←H
[SP] –2←L
[SP]←[SP] –2

PUSH PSW (PUSH accumulator content and flags on stack)


[SP] – 1 ←A
[SP]– 2←PSW (Program Status Word)
[SP] ←[SP] –2

POP B (Pop off stack to register pair B and C)


C←[SP]
B←[SP] +1
[SP] ←[SP] +2

POP D (Pop off stack to register pair D and E)


E←[SP]
D←[SP] + 1
[SP] ←[SP] + 2

POP H (Pop off stack to register pair H and L)


L←[SP]
H←[SP] +1
[SP]←[SP] +2

POP PSW (Pop off stack to accumulator and flags)


PSW←[SP]
A←[SP]+1
[SP]←[SP]+2

XTHL (Exchange H and L with top of stack)


L→[SP]
H↔[SP]+1

SPHL (Copy the contents of H–L register pair to the stack pointer)
[H–L]→[SP].

Table: 8085 Stack/PUSH and POP instruction set summary

Comment

I/O and Machine Control Instructions


Table: 8085 I/O and machine control instructions set summary

Comment
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