Hackathon Report
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***************** Day 2
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LEC (Formality) of picorv_32
Objective
To perform Logic Equivalence Checking (LEC) using Synopsys Formality between the RTL
and synthesized netlist of the PicoRV32 core, ensuring functional correctness after synthesis.
What is LEC using Formality in Synthesis?
LEC (Logic Equivalence Checking) using Formality is a verification process in digital design used
to formally prove that two representations of a circuit are logically equivalent. In the context of
synthesis, LEC ensures that the synthesized netlist is functionally identical to the RTL (Register
Transfer Level) code.
During synthesis, the RTL is optimized and transformed into a gate-level netlist. This
transformation can change the structure of the circuit but should not change its behavior.
LEC verifies that:
RTL (Pre-synthesis) ⇔ Gate-level Netlist (Post-synthesis)
No bugs were introduced during synthesis optimization (like constant propagation,
retiming, etc.).
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Task 1
We first completed the synthesis of the PicoRV32 RTL design to generate a gate-level netlist
using Design Compiler. Once the synthesis was successfully completed, we performed Logic
Equivalence Checking (LEC) using Synopsys Formality to ensure that the synthesized netlist is
functionally equivalent to the original RTL.
Synthesis output and reports
Reports
1. area
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2. power
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3. timing
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Gate level netlist (.vg)
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Task 2
Formality Flow
1. To invoke Synopsys Formality
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1 .csh
2.formality
In order to invoke Synopsys formality, it is advised to transition the shell environment from Bash to C-
shell by executing the command 'csh' in the terminal and then type formality in terminal.
2.Set SVF file in Guidance.
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The svf file is an automated setup file. It helps Formality handle design changes made by other tools in
the design process. Formality uses this file to help match and verify compare points, making it easier to
align designs during verification.
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3.Reference – Insert RTL
1. Begin by selecting the RTL by clicking on the "verilog" button.
2. Once you've chosen the Verilog file, proceed to click on the "Load File" button.
3. Verify on the right side column to ensure that all appropriate Verilog files have been loaded correctly.
Check for any listed files to confirm their proper loading and alignment for further processing.
4.Reference – Set Top of RTL
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5.Implementation – Selecting the netlist (mapped.v or gate level Netlist)
6.Implementation – Selecting the DB files.
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7.Implementation – Set Top design of gate level netlist.
8.Match
9.Verify
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10.Output
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