DEPARTMENT OF ECE

INDUR
INSTITUTE OF ENGINEERING & TECHNOLOGY
SIDDIPET– 502277

LABORATORY MANUAL

ELECTRONIC CIRCUIT ANALYSIS LAB

2nd Year 2nd Sem. ECE
(As per R22 Academic Regulation)
Prepared and verified by

K KIRANMAI

DEPARTMENT
OF
ELECTRONICS AND COMMUNICATION ENGINEERING

BTECH II-II ECA Page 1

DEPARTMENT OF ECE

PREFACE
The Electronic Circuit Analysis Laboratory is designed to provide hands-on experience in
designing, simulating, and analyzing electronic circuits. The course emphasizes power amplifiers,
tuned amplifiers, multivibrators, and sweep circuits. The practical exposure gained through this lab
enhances the understanding of theoretical concepts learned in the Electronic Circuit Analysis course
MULTISIM is very popular software for analyzing electrical and electronics circuits.
MULTISIM can be run on personal computers, it widens the scope for the integration of computer
aided simulation to circuits and implementing the same in the hardware lab also. This approach has
the advantage that the students can compare the results which are obtained in hardware lab with the
results of the MULTISIM models.

Course Objectives:
The main objective of this curriculum/course is to make the students well versed with basic
electronic components and circuits. The students can
Develop Practical Circuit Design Skills: Students will gain practical experience in designing and
analyzing electronic circuits, including power amplifiers, tuned amplifiers, and multivibrators.
Understand Amplifier Characteristics: Students will learn to design various power amplifiers,
such as Class A, B, and C amplifiers, and understand their efficiency, harmonics, and crossover
distortions.
Analyze Frequency Response: The course will enable students to design tuned amplifiers and
assess their Q-factor, helping them understand the behavior of frequency-dependent circuits.
Learn Time-based Circuit Design: Students will gain knowledge of sweep circuits and
multivibrators, understanding their role in time-based applications like signal generation and
modulation.
Hands-on Experience with Advanced Circuit Elements: Students will work with advanced circuit
elements like sampling gates and sweep circuits, learning how these components are used in practical
electronics.

Prerequisite:
Circuit Theory: Knowledge of Ohm’s law, Kirchhoff's voltage and current laws, and the analysis of
resistive and reactive circuits.
Basic Electronic Components: Understanding of the working principles of diodes, transistors (BJT,
FET), capacitors, inductors, and operational amplifiers.
Analog Electronics: Familiarity with small-signal amplifiers, frequency response, and impedance
matching.
Basic Simulation Tools: Experience with circuit simulation software like Multisim, PSPICE, or
equivalent, for the design and verification of circuits.
Course Outcomes:
The combination of lecture and laboratory sessions provides learning opportunities that should
enable the student to do the following upon completion of this course:
Design and analyze power amplifiers such as Class A, Class B, Class C, and Push-Pull amplifiers,
and determine their efficiency.
Design and implement tuned amplifiers and calculate their Q-factor, which is essential in filter and
communication circuit designs.
Construct and evaluate different types of multivibrators (Astable, Monostable, and Bistable) and
sweep circuits, understanding their role in waveform generation and signal processing.
Design and test sampling gates and frequency division circuits, gaining insight into their importance
in digital and communication systems.

BTECH II-II ECA Page 2

DEPARTMENT OF ECE

CODE OF CONDUCT
1. Students should report to the concerned labs as per the time table schedule.
2. Students who turn up late to the labs will in no case be permitted to perform the experiment
scheduled for the day.
3. After completion of the experiment, certification of the concerned staff in-charge in the
observation book is necessary.
4. Continuous Internal Evaluation of a practical subject is done for 40 marks during the
semester as follows: (i) A write-up on day-to-day experiments in the laboratory (in terms of
aim, components/procedure, expected outcome) shall be evaluated for 10 marks (ii) 10 marks
are awarded either for the performance in viva-voce (or) case study presentation (or)
application development (or) poster presentation. (iii) Internal practical examination shall be
conducted by the concerned laboratory teacher for 10 marks. (iv) The remaining 10 marks are
awarded for laboratory project, which consists of the design (or) software/hardware model
presentation (or) app development (or) prototype presentation at the end of the completion of
laboratory course and before semester end practical examination.
5. The Semester End Examination for a practical subject shall be conducted with an external
examiner and the laboratory teacher. The external examiner shall be appointed by the
Principal/Vice-Principal. The Semester End Examination (SEE) for a practical subject shall
be held for 3 hours for a total of 60 marks evaluated as follows: (i) 10 marks for write-up (ii)
15 marks for experiment/program (iii) 15 marks for evaluation of results (iv) 10 marks for
presentation on another experiment/program in the same laboratory course and (v) 10 marks
for viva-voce on concerned laboratory course.
6. Students should bring a note book of about 100 pages and should enter the
readings/observations into the note book while performing the experiment.
7. The record of observations along with the detailed experimental procedure of the experiment
performed in the immediate last session should be submitted and certified by the staff
member in-charge.
8. The components required pertaining to the experiment should be collected from stores in-
charge after duly filling in the requisition form.
9. When the experiment is completed, students should disconnect the setup made by them, and
should return all the components/instruments taken for the purpose.
10. Any damage of the equipment or burn-out of components will be viewed seriously either by
putting penalty or by dismissing the total group of students from the lab for the semester/year.
11. Students should be present in the labs for the total scheduled duration.
12. Students are required to prepare thoroughly to perform the experiment before coming to
Laboratory.
13. Procedure sheets/data sheets provided to the students’ groups should be maintained neatly
and to be returned after the experiment

BTECH II-II ECA Page 3

DEPARTMENT OF ECE

INDEX
Page No.
Sl. No. Name of the Experiment
H/W S/W
1 CLASS A POWER AMPLIFIER 6-9 71-74
2 CLASS B POWER AMPLIFIER 10-13 75-79
3 COMPLEMENTARY SYMMETRY PUSHPULL AMPLIFIER 14-19 80-85
4 CLASS C POWER AMPLIFIER 20-24 86-89
5. SINGLE TUNED AMPLIFIER 25-28 90-94
6 BISTABLE MULTIVIBRATOR 29-32 95-99
7 ASTABLE MULTIVIBRATOR 33-36 100-103

8. MONOSTABLE MULTIVIBRATOR 37-41 104-108

9 SCHMITT TRIGGER WITH LOOP GAINS 42-46 109-113

10 BOOTSTRAP SWEEP CIRCUIT 47-50 114-117

11. MILLER SWEEP CIRCUIT 51-54 118-121

12. CONSTANT CURRENT SWEEP GENERATOR 55-58 122-126

13. SAMPLING GATES 59-61 127-129

14. SCHMITT TRIGGER 62-65 130-133

15. SWEEP CIRCUIT 66-69 134-137

BTECH II-II ECA Page 4

DEPARTMENT OF ECE

HARDWARE

BTECH II-II ECA Page 5

DEPARTMENT OF ECE

EXP. NO.1
CLASS A POWER AMPLIFIER
(HARDWARE)
I.AIM: To Design transformer coupled class A power amplifier and draw the input and output
waveforms find its efficiency

II.TOOLS/ EQUIPMENTS/APPARATUS REQUIRED:

APPARATUS REQUIRED:
Power supply 0-30V 1 No.
CRO 20 MHz 1 No.
Digital multi meter 1 No.
Signal generator 1Hz-1MHz 1 No.
COMPONENTS REQUIRED:
Resistors 33KΩ 1No
560Ω 1No
47KΩ 1No
Capacitors 22uf 1No
100uf 1No
Transistor BC107BP 1No
Transformer 50mH 1No

III.THEORY:
An amplifier where the load is coupled to the output using a transformer is called a
transformer coupled amplifier. Using transformer coupling the efficiency of the amplifier can be
improved to a great extend. The coupling transformer provides good impedance matching between
the output and load and it is the main reason behind the improved efficiency. Impedance matching
means making the output impedance of the amplifier equal to the input impedance of the load and
this is an important criterion for the transfer of maximum power.

BTECH II-II ECA Page 6

DEPARTMENT OF ECE

IV. .CIRCUIT DIAGRAM:

V.PROCEDURE:
1. Connect the circuit as shown in diagram.
2. The input signal of 50mv (p-p) at 1 kHz is applied from function generator and output
terminals are connected to CRO.
3. Adjust the input frequency and note down corresponding output voltages at different
frequencies.
4. Plot the graph; Gain (Db) vs Frequency (Hz).
5. Calculate gain, bandwidth and efficiency

VI.OBSERVATIONS:
Input voltage Vin=50Mv
S.No. Frequency (Hz) Output voltage (Vo) Gain in Db
1 100
2 1K
3 10K
4 100K
5 1M
6 10M
7 100M

BTECH II-II ECA Page 7

DEPARTMENT OF ECE

VII.CALCULATIONS:
Efficiency is defined as the ratio of AC output power to DC input power
DC input power = Vcc x ICQ

AC output power = VP-P2 / 8RL

Input DC power = Vcc x ICQ

Output AC power = Vrms x Irms

= VPP2 / 8RL

OutputACpower
η=
InputDCpower

VIII.NATURE OF GRAPH:
I. Output waveforms

II. Graph

BTECH II-II ECA Page 8

DEPARTMENT OF ECE

IX.INFERENCE:

The efficiency observed is ___________ against theoretical maximum of 50%.

X.PRECAUTIONS:
1.All the connections should be correct.
2.Do not switch ON the power supply unless you have checked the circuit connections as per the
circuit diagram.
3.While doing the experiment do not exceed the ratings of the devices. This may lead to damage
of the devices.

XI.TROUBLE SHOOTING:
1.Check the supply connections.
2.Check the transistor.

XII.RESULTS / CONCLUSIONS:
Thus the frequency response of transformer coupled class-A power amplifier is observed and
calculated output AC power and efficiency.

XIII.EXTENSION:
1.Cass-B amplifier
2.Class-AB amplifier

XIV.APPLICATIONS:
1. This circuit is used for Impedance matching and DC isolation.

XV.QUESTIONS:
1.Differentiate between voltage amplifier and power amplifier
2.Explain impedance matching provided by transformer?
3.What is the maximum theoretical efficiency of this amplifier?
4.What is the range of conduction angle of output current with respective input signal?
5.How is DC and AC power measured in this circuit?
6.For class-A operation how did you locate the Q-point.

BTECH II-II ECA Page 9

DEPARTMENT OF ECE

EXP. NO.2
CLASS B POWER AMPLIFIER
(HARDWARE)
I.AIM: To To Design class B power amplifier and draw the input and output waveforms, find 2nd
order and above harmonics.
II.TOOLS/ EQUIPMENTS/APPARATUS REQUIRED:
APPARATUS REQUIRED:
Power supply 0-30V 1 No.
CRO 20 MHz 1 No.
Digital multi meter 1 No.
Function generator 1Hz-1MHz 1 No.
COMPONENTS REQUIRED:
Resistors 1kΩ, 470Ω 1No
220kΩ, 18kΩ, 1 Ω 2No
Capacitors 10 μ F/ 25 V 2No
Transistor BD 237(npn)) 1No
BD 242C(pnp)) 1No

III.THEORY:
Power amplifiers are designed using different circuit configuration with the sole purpose of
delivering maximum undistorted output power to load. Push-pull amplifiers operating either inClass-
B is class-AB is used in high power audio system with high efficiency. In complementary-symmetry
class-B power amplifier two types of transistors, NPN and PNP are used.
These transistors acts as emitter follower with both emitters connected together. In class-B
power amplifier Q-point is located either in cut-off region or in saturation region. So, that only 180 o
of the input signal is flowing in the output. In complementary-symmetry power amplifier, during the
positive half cycle of input signal NPN transistor conducts and during the negative half cycle PNP
transistor conducts. Since, the two transistors are complement of each other and they are connected
symmetrically so, the name complementary symmetry has come theoretically efficiency of
complementary symmetry power amplifier is 78.5%.

BTECH II-II ECA Page 10

DEPARTMENT OF ECE

IV.CIRCUIT DIAGRAM:

V.PROCEDURE:
6. Connect the circuit as shown in diagram.
7. The input signal of 50mv (p-p) at 1 kHz is applied from function generator and output
terminals are connected to CRO.
8. Adjust the input frequency and note down corresponding output voltages at different
frequencies.
9. Plot the graph; Gain (dB) vs Frequency (Hz).
10. Calculate gain, bandwidth and efficiency

VI. OBSERVATIONS:
Input voltage Vin=50mV
S.No. Frequency (Hz) Output voltage (Vo) Gain in dB
1 100
2 1K
3 10K
4 100K
5 1M
6 10M
7 100M

BTECH II-II ECA Page 11

DEPARTMENT OF ECE

VII.CALCULATIONS:
Efficiency is defined as the ratio of AC output power to DC input power
DC input power = Vcc x ICQ

AC output power = VP-P2 / 8RL

Input DC power = Vcc x ICQ

Output AC power = Vrms x Irms

= VPP2 / 8RL

OutputACpower
η=
InputDCpower
VIII.NATURE OF GRAPH:
III. Output waveforms

IV. Graph

IX.INFERENCE:
The efficiency observed is ___________ against theoretical maximum of 50%.

BTECH II-II ECA Page 12

DEPARTMENT OF ECE

X.PRECAUTIONS:
1.All the connections should be correct.
2.Do not switch ON the power supply unless you have checked the circuit connections as per the
circuit diagram.
3.While doing the experiment do not exceed the ratings of the devices. This may lead to damage
of the devices.

XI.TROUBLE SHOOTING:
1. Check the supply connections.
2. Check the transistor.

XII.RESULTS / CONCLUSIONS:
Thus the frequency response of transformer coupled class-A power amplifier is observed and
calculated output AC power and efficiency.

XIII.EXTENSION:
1.Cass-B amplifier
2.Class-AB amplifier

XIV.APPLICATIONS:
1.This circuit is used for Impedance matching and DC isolation.

XV.QUESTIONS:
1.Differentiate between voltage amplifier and power amplifier
2.Explain impedance matching provided by transformer?
3.What is the maximum theoretical efficiency of this amplifier?
4.What is the range of conduction angle of output current with respective input signal?
5.How is DC and AC power measured in this circuit?
6.For class-A operation how did you locate the Q-point.
7.What are the applications of class-B complementary symmetry amplifier?

BTECH II-II ECA Page 13

DEPARTMENT OF ECE

EXPERIMENT NO: 3

COMPLEMENTARY SYMMETRY PUSHPULL AMPLIFIER

I. AIM:
Prove that the complementary symmetry pushpull amplifier eliminate cross over
distortion.

II. EQUIPMENT REQUIRED:

APPARATUS REQUIRED:
Power supply 0-30V 1 No.
CRO 20 MHz 1 No.
Digital multi meter 1 No.
Function generator 1Hz-1MHz 1 No.
COMPONENTS REQUIRED:
Resistors 1kΩ, 40.2KΩ 1No
10kΩ 2No
Capacitors 100μ F/ 25 V 3No
Transistor BC107(npn)) 1No
BC177(pnp)) 1No
Diodes IN4001 2No

III. THEORY:
The Class B amplifier circuit above uses complimentary transistors for each half of the waveform
and while Class B amplifiers have a much high efficiency than the Class A types, one of the main
disadvantages of class B type push-pull amplifiers is that they suffer from an effect known
commonly as Crossover Distortion.
It takes approximately 0.7 volts (measured from base to emitter) to get a bipolar transistor
to start conducting. In a class B amplifier, the output transistors are not "pre -biased" to an "ON"
state of operation. This means that the part of the output waveform which falls below this 0.7 volt
window will not be reproduced accurately as the transition between the two transistors (when
they are switching over from one to the other), the transistors do not stop or start conducting
exactly at the zero crossover point even if they are specially matched pairs.
The output transistors for each half of the waveform (positive and negative) will each
have a 0.7 volt area in which they will not be conducting resulting in both transistors being
"OFF" at the same time.
A simple way to eliminate crossover distortion in a Class B amplifier is to add two small
voltage sources to the circuit to bias both the transistors at a point slightly above their cut-off
point.. However, it is impractical to add additional voltage sources to the amplifier circuit so pn-
junctions are used to provide the additional bias in the form of silicon diodes.

BTECH II-II ECA Page 14

DEPARTMENT OF ECE

IV. CIRCUIT DIAGRAM:

Class B Power Amplifier circuit where crossover distortion is present

Class B Power Amplifier circuit where crossover distortion is eliminated

BTECH II-II ECA Page 15

DEPARTMENT OF ECE

V. PROCEDURE:
Circuit Setup Without Biasing Diodes (Crossover Distortion Present)
1. Assemble the Class B Push-Pull Amplifier Circuit (without biasing diodes) as per the given
diagram.
2. Connect the Function Generator to the input of the amplifier.
o Set the input signal to a sine wave of frequency 1 kHz and amplitude 1V (peak-to-
peak).
3. Connect the CRO probes to the output terminals of the amplifier.
4. Power ON the circuit and observe the output waveform on the CRO.
5. Sketch the waveform and note the distortion near the zero-crossing points (crossover
distortion).

Circuit Setup With Biasing Diodes (Crossover Distortion Eliminated)

6. Modify the same circuit by adding two biasing diodes (silicon diodes) between the bases of
the complementary transistors.
7. Ensure the diodes are forward-biased to provide a small voltage drop (~0.7V) to pre-bias the
transistors.
8. Reconnect the Function Generator (same settings: 1 kHz, 1Vpp sine wave).
9. Observe the output waveform on the CRO.
10. Compare with the previous waveform and note the reduction/elimination of crossover
distortion

VI. Observations & Comparisons

Condition Output Waveform Observation

Without Biasing Diodes Distorted output near zero-crossing (crossover distortion)
With Biasing Diodes Smooth sinusoidal output without distortion

VII. CALCULATIONS: Crossover Distortion Measurement

To quantify distortion:

1. Total Harmonic Distortion (THD) without biasing:

THD=V22+V32+…V1×100%

(where V1 = fundamental frequency, V2,V3= harmonics)

2. THD with biasing diodes:

o Expected to drop from ~10% (unbiased) to <1% (biased).

BTECH II-II ECA Page 16

 DEPARTMENT OF ECE

VIII. NATURE OF GRAPH:

Output waveform of Complementary symmetry Class B Power Amplifier circuit where

crossover distortion is present

Output waveform of Complementary symmetry Class B Power Amplifier circuit where

crossover distortion is eliminated

IX. Inference
 The experiment demonstrates that without biasing diodes, the Class B push-pull amplifier
suffers from crossover distortion due to the dead zone (~0.7V) where both transistors
remain cut off.
 By introducing biasing diodes, a small pre-bias voltage (~0.7V) is applied, ensuring that the
transistors remain slightly conducting even at zero-crossing, thus eliminating distortion.
 The output waveform with biasing diodes is smoother and distortion-free compared to the
distorted waveform obtained without them.

BTECH II-II ECA Page 17

 DEPARTMENT OF ECE

X. Precautions
1. Correct Polarity:
o Ensure proper orientation of diodes and transistors to avoid reverse biasing.
2. Matching Components:
o Use matched pairs of transistors (NPN & PNP) and diodes for symmetrical
amplification.
3. Input Signal Limitation:
o Keep the input signal amplitude low (~1Vpp) to avoid clipping and overheating.
4. Proper Grounding:
o Use a common ground to minimize noise in the output.
5. Heat Dissipation:
o If the amplifier is driven at high power, use heat sinks to prevent transistor damage.

XI. Troubleshooting
Issue Possible Cause Solution
No Output Signal Loose connections, Power Check wiring, ensure power supply is
supply failure ON
Distorted Output (Even Mismatched transistors, Replace transistors, verify diode
with Diodes) Incorrect biasing biasing
Asymmetrical Waveform Unequal transistor gains, Use matched transistors, test diodes
Faulty diodes with a multimeter
Excessive Noise Poor grounding, Loose Secure connections, use shielded
probes cables
Overheating High input signal, Short Reduce input amplitude, check for
circuit shorts

XII. Results
 Without biasing diodes: The output waveform shows crossover distortion near zero-
crossing points.
 With biasing diodes: The output waveform is clean and distortion-free, confirming the
elimination of crossover distortion.
 Conclusion: The use of biasing diodes in a complementary symmetry push-pull
amplifier effectively removes crossover distortion.

XIII. Extensions
1. Efficiency Measurement:
o Compare efficiency of Class B vs. Class AB operation.
2. Different Biasing Techniques:
o Experiment with resistor biasing or VBE multiplier instead of diodes.
3. Frequency Response Analysis:
o Test the amplifier’s performance at different frequencies (e.g., 100Hz, 10kHz).
4. Thermal Stability Test:
o Observe how temperature affects biasing and distortion.

BTECH II-II ECA Page 18

 DEPARTMENT OF ECE

XIV. Applications
1. Audio Amplifiers (Hi-Fi systems, speakers)
2. Radio Transmitters & Receivers
3. Power Amplification in Communication Systems
4. Signal Processing Circuits
5. Motor Drivers & PWM Controllers

XV. Questions
Theory-Based:
1. What is crossover distortion?
2. How do biasing diodes eliminate crossover distortion?
3. What is the difference between Class B and Class AB amplifiers?
4. Why are complementary transistors used in push-pull amplifiers?
Experiment-Based:
5. What happens if one diode is reversed in the circuit?
6. Can we use resistors instead of diodes for biasing?
7. How does increasing input signal amplitude affect distortion

BTECH II-II ECA Page 19

DEPARTMENT OF ECE

EXPERIMENT NO: 4
CLASS C POWER AMPLIFIER
I. AIM:
To design class C power amplifier and draw the input and output waveforms

II. EQUIPMENT REQUIRED:

APPARATUS REQUIRED:
Power supply 0-30V 1 No.
CRO 20 MHz 1 No.
Digital multi meter 1 No.
Function generator 1Hz-1MHz 1 No.
COMPONENTS REQUIRED:
Resistors 2.2kΩ, 100KΩ, 10KΩ, 560Ω 1No
Capacitors 100μ F/ 25 V 3No
0.1μ F 1No
Transistor BC107(npn)) 1No
Inductor 33mH 1No

III. THEORY

 A tuned amplifier uses a parallel LC tank circuit as its load to amplify signals over a narrow
frequency band.
 Resonant frequency (f₀):

Bandwidth (BW): The range of frequencies where gain ≥ 70.7% of maximum gain (BW = f₂ -
f₁).

 Voltage Gain (Av):

BTECH II-II ECA Page 20

DEPARTMENT OF ECE

IV.CIRCUIT DIAGRAM:

V. PROCEDURE:

1. Set Up the Circuit:

o Connect the LC tank circuit (L, C) to the collector of the transistor.
o Connect the function generator (1Vpp, 1kHz) to the input.
o Connect CRO probes to input (Ch1) and output (Ch2).
2. Find Resonant Frequency (f₀):
o Vary the input frequency until maximum output voltage is observed on CRO.
o Record this frequency as f₀.
3. Measure Bandwidth:
o Increase/decrease frequency until output voltage drops to 70.7% of maximum.
o Note these frequencies as f₂ (upper cutoff) and f₁ (lower cutoff).
o BW = f₂ - f₁.
4. Calculate Gain:
o Measure V₀ (output) and Vᵢ (input) at f₀.
o Compute gain in dB:

BTECH II-II ECA Page 21

DEPARTMENT OF ECE

VI. OBSERVATION TABLE:

S.NO FREQUENCY(Hz) OUTPUT VOLTAGE GAIN (dB)

VOLTAG GAIN Avf=20 log
E (Vo) (Avf=Vo/Vi) (Vo/Vi).

Bandwidth of the CE amplifier = fh-fl HZ

VII. Calculations
1. Resonant Frequency (f₀):

2. Voltage Gain (dB):

3. Bandwidth:
BW=f2−f1

BTECH II-II ECA Page 22

 DEPARTMENT OF ECE

VIII. NATURE OF GRAPH:

IX. INFERENCE
 The maximum gain occurs at resonant frequency (f₀)= ______________
 Bandwidth is narrow, confirming it’s a tuned amplifier= ___________
 Gain drops -3 dB at cutoff frequencies (f₁, f₂)= __________________

X. PRECAUTIONS
 Use exact LC values for accurate f₀.
 Avoid loose connections to prevent frequency drift.
 Measure V₀ precisely at 70.7% for correct BW.

XI. TROUBLESHOOTING
 Solution
 Issue
 Check LC tank circuit connections.
 No output at f₀
 Replace faulty transistor.
 Flat frequency response
 Verify CRO measurements.
 Incorrect BW

BTECH II-II ECA Page 23

 DEPARTMENT OF ECE

XII. RESULT
 Resonant frequency (f₀) = _____ Hz
 Maximum gain = _____ dB
 Bandwidth = _____ Hz

XIII. EXTENSIONS
 Compare single-tuned vs. double-tuned amplifiers.
 Study effect of Q-factor on bandwidth.
 Simulate in Multisim for validation.

XIV. APPLICATIONS
 Radio transmitters/receivers (RF amplification).
 TV tuners.
 Wireless communication systems.

XV. QUESTIONS
 What is a tuned amplifier?
 What is the formula for resonant frequency?
 Difference between single, double, and stagger-tuned amplifiers?

BTECH II-II ECA Page 24

DEPARTMENT OF ECE

EXPERIMENT: 5
SINGLE TUNED VOLTAGE AMPLIFIER
I. AIM

To study the frequency response of a single tuned amplifier and determine its gain, bandwidth, and
quality factor (Q).

I. EQUIPMENT REQUIRED

Apparatus Specification Quantity

Regulated Power Supply 0-20V DC 1
Function Generator 1Hz-10MHz 1
CRO 20MHz 1
Components Value Qty.
Transistor (BC107) - 1
Resistors 220Ω, 1 each
22kΩ,5.6kΩ,10kΩ,
1kΩ
Capacitors 100µF, 10µF, 1nF 1 each

Inductor 1mH 1
Breadboard & Wires - As needed

III. THEORY
 A tuned amplifier uses an LC tank circuit to amplify a narrow band of frequencies.
 Resonant frequency (f₀):


 Bandwidth (BW): Range where gain ≥ 70.7% of maximum (BW = f₂ - f₁).
 Quality Factor (Q):

 Gain in dB:

BTECH II-II ECA Page 25

DEPARTMENT OF ECE

IV. CIRCUIT DIAGRAM

IV. PROCEDURE

1. Circuit Setup:
o Connect the LC tank (1mH + 1nF) to the collector of BC107.
o Set input signal: 50mV, 1kHz sine wave (from function generator).
2. Frequency Sweep:
o Vary frequency from 100Hz to 10MHz, noting output voltage (V₀) at each step.
3. Measure Resonant Frequency (f₀):
o Identify frequency where V₀ is maximum.
4. Determine Bandwidth (BW):
o Find frequencies f₁ and f₂ where V₀ drops to 70.7% of maximum.
5. Calculate Q-Factor:

BTECH II-II ECA Page 26

DEPARTMENT OF ECE

VI.OBSERVATIONS: Input voltage Vin=50mV

S.No. Frequency (Hz) Output voltage (Vo) Gain in dB
1 100
2 1K
3 10K
4 100K
5 1M
6 10M

Bandwidth (BW) = f₂ - f₁ = _____ Hz

Q-Factor = f₀ / BW = _____

VII. CALCULATIONS
1. Resonant Frequency (Theoretical):

2. Gain at f₀:

3. Q-Factor (Experimental):

VIII. GRAPH

BTECH II-II ECA Page 27

DEPARTMENT OF ECE

 X-axis: Frequency (log scale).

 Y-axis: Gain (dB).
 Peak at f₀, sharp roll-off at f₁ and f₂.

IX. INFERENCE
1. Maximum gain occurs at f₀ ≈ _________.
2. Bandwidth ≈ ___________ indicates moderate selectivity.
3. Q ≈_________________confirms effective frequency discrimination.

X. PRECAUTIONS
1. Ensure exact LC values for accurate f₀.
2. Avoid loose connections to prevent frequency drift.
3. Use shielded cables to minimize noise.

XI. TROUBLESHOOTING
Issue Solution
No output at f₀ Check LC tank connections.
Flat frequency response Replace transistor or verify biasing.
High noise Ground all components properly.

XII. RESULTS
 Resonant frequency (f₀) = _____________
 Bandwidth (BW) = ____________
 Q-Factor = _______________________

XIII. EXTENSIONS
1. Double-Tuned Amplifier: Compare bandwidth and selectivity.
2. Q-Factor Optimization: Adjust L/C ratio for higher Q.
3. Multisim Simulation: Validate results virtually.

XIV. APPLICATIONS
1. AM/FM Radio Receivers: Select specific channels.
2. TV Tuners: Filter adjacent channel interference.
3. RF Communication Systems: Narrowband signal amplification.

XV. VIVA QUESTIONS

1. What is the significance of Q-factor?
2. How does Q relate to bandwidth?
3. Why use a tuned amplifier?
4. What happens if L or C is doubled?

BTECH II-II ECA Page 28

 DEPARTMENT OF ECE

EXPERIMENT: 6
BISTABLE MULTI VIBRATOR
(HARDWARE)

I. AIM: To Design a Bistable Multivibrator and analyze the effect of commutating capacitors
and draw the wave forms at base and collector of transistors.

II. EQUIPMENT REQUIRED

Apparatus Specification Quantity

CRO 20MHz (Dual Channel) 1
Function Generator 1Hz–1MHz 1
Power Supply 0–30V DC (Dual) 1
Components Value Qty.
Transistors (BC107) NPN 2
Resistors 1kΩ, 10kΩ, 100kΩ 2 each
Capacitors 0.001µF, 0.33µF,100nf, 330nF 2 each
Diodes (1N4007) - 4
Breadboard - 1

III. THEORY

Key Concepts

1. Bistable Nature:

o Has two stable states (Q1 ON/Q2 OFF or Q1 OFF/Q2 ON).

o Requires external trigger to switch states.
2. Operation:

o Cross-coupled transistors maintain states via positive feedback.

o Triggering: Applied pulse forces transition between states.
3. Commutation Capacitors (Speed-Up Caps):

o Reduce transition time by bypassing resistors during switching.

4. Design Equations:

o Resistor Ratio:

Max Switching Frequency:

BTECH II-II ECA Page 29

 DEPARTMENT OF ECE

IV. CIRCUIT DIAGRAM

V. PROCEDURE

1. Hardware Setup

1. Connect the circuit as per the diagram.

2. Apply VCC = 5V DC.

2. Triggering & Observation

1. Set function generator to 1kHz, 5Vpp square wave.

2. Apply trigger pulses to Set (S) or Reset (R) inputs.
3. Observe VC1, VC2, VB1, VB2 on CRO.

3. Measurements

1. Stable States: Note voltages at collectors.

2. Transition Time: Measure delay using CRO cursors.

BTECH II-II ECA Page 30

 DEPARTMENT OF ECE

VI. OBSERVATIONS

Parameter State 1 (Q1 ON) State 2 (Q2 ON)

VC1 (Volts)
VC2 (Volts)
Transition Time (µs)

VII. CALCULATIONS

1. Theoretical fₘₐₓ:

2. Trigger Pulse Width:

tw≥2.2×R2×C

VIII. EXPECTED WAVEFORMS

BTECH II-II ECA Page 31

 DEPARTMENT OF ECE

IX. INFERENCE

1. Two stable states confirmed by CRO measurements.

2. Trigger pulses successfully force state transitions.
3. Commutation capacitors reduce transition time to ~2µs.

X. PRECAUTIONS

1. Polarity: Ensure correct orientation of diodes/transistors.

XI. TROUBLESHOOTING

Issue Solution
No state transition Check trigger pulse connections
Asymmetric outputs Verify resistor/capacitor values
Slow switching Replace commutation capacitors

XII. RESULTS

1. Stable States Verified: Q1/Q2 toggle with trigger.

2. Transition Time: __________________
3. Max Switching Frequency: _________________________

XIII. EXTENSIONS

1. Frequency Divider: Use as a ÷2 counter.

2. Debounce Circuit: Eliminate switch bouncing.

XIV. APPLICATIONS

1. Digital Memory: Stores 1-bit data.

2. Counters: Basic building block.
3. Pulse Synchronization: Aligns signals in timing circuits.

XV. VIVA QUESTIONS

1. Why are diodes used in the circuit?

2. What happens if commutation caps are removed?

3. How to make a T flip-flop from this circuit?

4. What is the role of R1/R2?

BTECH II-II ECA Page 32

 DEPARTMENT OF ECE

EXPERIMENT NO. 7
ASTABLE MULTIVIBRATOR
I. AIM:
To Design an Astable Multivibrator and draw the wave forms at base and collector of
transistors

II. APPARATUS REQUIRED:

S.No Name of Component/Equipment Specifications Quantity

1 Resistors 3.9KΩ, 100KΩ 2 each
2 CRO (Cathode Ray Oscilloscope) 20MHz 1
3 Function Generator 1MHz 1
4 Connecting Wires - As required
5 DC Regulated Power Supply 0-30V, 1A 1
6 Transistor (BC 107) - 2
7 Capacitor 0.01 µF 2

III. THEORY:

An Astable Multivibrator is a free-running oscillator that continuously switches between two

unstable (quasi-stable) states without any external triggering. It consists of two cross-coupled
transistor amplifier stages with regenerative feedback through capacitors.

 The circuit produces a square wave output.

 The time period of oscillation is given by:

where R=R1=R2 and C=C1=C2

 The frequency of oscillation is:

BTECH II-II ECA Page 33

 DEPARTMENT OF ECE

IV. CIRCUIT DIAGRAM:

V. PROCEDURE:

1. Calculate the theoretical frequency of oscillations using T=1.38RCT=1.38RC.

2. Connect the circuit as per the given diagram.
3. Power ON the circuit and observe the waveforms at both collectors using a CRO.
4. Observe the base and collector waveforms simultaneously.
5. Measure the time period (T) and frequency (f) from the CRO.
6. Compare theoretical and practical values.

VI. OBSERVATIONS:
Parameter Theoretical Value Observed Value
Time Period (T) T=1.38×R×C (Measured from CRO)
Frequency (f) (Measured from CRO)

ON Time (T₁) - -
OFF Time (T₂) - -
Duty Cycle -

BTECH II-II ECA Page 34

 DEPARTMENT OF ECE

VII. CALCULATIONS (THEORITICAL)

VIII. NATURE OF GRAPH:

IX. INFERENCE:

1. The Astable Multivibrator generates a continuous square wave without any external trigger.
2. The frequency depends on RC values.
3. The duty cycle is approximately 50% if R1=R2R1=R2 and C1=C2C1=C2.

BTECH II-II ECA Page 35

 DEPARTMENT OF ECE

X. PRECAUTIONS:

1. Ensure correct polarity of components (transistors, capacitors).

2. Avoid loose connections to prevent erratic waveforms.
3. Use proper CRO settings for accurate measurements.

XI. TROUBLESHOOTING:

Problem Possible Cause Solution

No output Loose connections, wrong transistor Check connections and transistor
waveform biasing biasing

Distorted Capacitor leakage, incorrect resistor Replace capacitors, verify resistor

waveform values values

XII. RESULTS:

 Theoretical Frequency = 725 Hz

 Observed Frequency = _____ Hz
 The Astable Multivibrator successfully generated a square wave with a duty cycle of
approximately 50%.

XIII. EXTENSIONS:

1. Modify the circuit to vary the duty cycle using different RC values.
2. Use a potentiometer to manually adjust the frequency.

XIV. APPLICATIONS:

1. Used in clock pulse generation in digital circuits.

2. Employed in LED flashers and tone generators.
3. Acts as a frequency modulator in communication systems.

XV. QUESTIONS:

1. Define stable state.

2. Define quasi-stable state.

3. Why is the Astable Multivibrator called "free-running"?

BTECH II-II ECA Page 36

 DEPARTMENT OF ECE

EXPERIMENT NO-8:
MONOSTABLE MULTIVIBRATOR

I. AIM:
To observe the stable state and quasi-stable state voltages in a monostable multivibrator
circuit.

II. APPARATUS REQUIRED

S.No Component/Equipment Specifications Quantity

1 Resistors 1KΩ, 68KΩ, 2.2KΩ, 1.5KΩ 1 each
2 CRO (Cathode Ray Oscilloscope) 20MHz 1
3 Function Generator 1MHz 1
4 Connecting Wires - As required
5 DC Regulated Power Supply 0-30V, 1A 1
6 Transistors BC107 2
7 Capacitors 1µF 2
8 Diode IN4007 1

III. THEORY

A monostable multivibrator has:

 One stable state (default state).

 One quasi-stable state (temporary state triggered externally).

Key Concepts:

1. Stable State:

o One transistor (Q1) is in cut-off, the other (Q2) is in saturation.

2. Quasi-Stable State:

o Triggering pulse flips the states temporarily.

o Automatically returns to stable state after a time delay (T = 0.693RC).
3. Applications:

o Pulse width modulation, timers, and delay circuits.

BTECH II-II ECA Page 37

 DEPARTMENT OF ECE

IV. CIRCUIT DIAGRAM

V. PROCEDURE

1. Circuit Assembly:

o Connect components as per the circuit diagram.

o Verify stable state voltages (Q1 OFF, Q2 ON).
2. Triggering:

o Apply 2Vpp, 1KHz square wave from the function generator.

3. Observations (CRO):

o Base Voltages (Vb1, Vb2):

 Vb1: Sudden spike during trigger, then exponential decay.

 Vb2: Drops to negative during quasi-stable state.
o Collector Voltages (Vc1, Vc2):

 Vc1: Switches from VCC to 0V during quasi-stable state.

 Vc2: Switches from 0V to VCC during quasi-stable state.
4. Measurements:

o Pulse Width (T): Measure on CRO and compare with T = 0.693RC.

BTECH II-II ECA Page 38

DEPARTMENT OF ECE

VI. OBSERVATIONS

Parameter Theoretical Value Observed Value

Pulse Width (T) 0.693 × R × C ______________

Quasi-Stable Duration Calculated T ______________

VII. CALCULATIONS

VIII. NATURE OF GRAPH

BTECH II-II ECA Page 39

 DEPARTMENT OF ECE

IX. INFERENCE

Stable State Confirmed:

In the absence of a trigger, the circuit remains in its default stable state (Q1 OFF, Q2 ON), as
observed via CRO.

Quasi-Stable State Duration:

The measured pulse width (T ≈ 47.1ms) matches the theoretical value (T = 0.693RC),
validating the RC time constant’s role.

X. PRECAUTIONS

1. Double-check polarity of capacitors and diodes.

2. Avoid exceeding VCC = 12V (BC107 max rating).
3. Minimize noise by using short, clean connections.

XI. TROUBLESHOOTING

Issue Solution
No output pulse Check trigger signal & transistor biasing.

Pulse width too short Verify RC values (68KΩ + 1µF).

Distorted waveforms Ground connections properly.

XII. RESULT

The stable state (Q1 OFF, Q2 ON) and quasi-stable state (Q1 ON, Q2 OFF for T = 47.1ms) were
successfully observed.

BTECH II-II ECA Page 40

 DEPARTMENT OF ECE

XIII. EXTENSIONS TO THE EXPERIMENT

1. Variable Pulse Width Control

 Modification: Replace the fixed capacitor (1µF) with a variable capacitor (1-10µF) or use
a potentiometer (100KΩ) in series with R (68KΩ).
 Objective: Manually adjust the quasi-stable state duration (T = 0.693RC) and observe
changes on the CRO.
 Application: Customizable timers for delay circuits.

XIV. APPLICATIONS

1. Timers (e.g., delay circuits).

2. Pulse Width Modulation (PWM).
3. Debouncing switches.

XV. QUESTIONS & ANSWERS

1. What are other names for a monostable multivibrator?

2. Which triggering is used?

3. Define transition time.

BTECH II-II ECA Page 41

DEPARTMENT OF ECE

EXPERIMENT NO-9:
SCHMITT TRIGGER WITH LOOP GAINS
(HARDWARE)
I. AIM:

Draw the response of Schmitt trigger for gain of greater than and less than one and to study its
behavior under different loop gain conditions.

II. EQUIPMENT REQUIRED:

S.No Component Specifications Quantity

1 Resistors 100Ω, 470Ω, 4.7kΩ, 10kΩ, 2.2kΩ As needed
2 Capacitor 0.01 µF 1
3 Transistor BC107 (NPN) 2
4 Function Generator 1 MHz 1
5 Oscilloscope (CRO) 20 MHz 1
6 Power Supply DC 0–30V, 1A 1
7 Connecting Wires — As req.
8 Breadboard — 1

III. THEORY:

A Schmitt Trigger is a comparator with positive feedback that converts an analog input (like a sine
wave) into a digital output (like a square wave) using hysteresis.

 UTP (Upper Threshold Point): Input voltage at which output turns ON

 LTP (Lower Threshold Point): Input voltage at which output turns OFF

Using two transistors, we achieve hysteresis by feeding back the output from one transistor to the
base of the other.

BTECH II-II ECA Page 42

DEPARTMENT OF ECE

IV. CIRCUIT DIAGRAM:

WITH GAIN > 1, THE SCHMITT TRIGGER DIAGRAM

WITH GAIN < 1, THE SCHMITT TRIGGER DIAGRAM

BTECH II-II ECA Page 43

DEPARTMENT OF ECE

V. PROCEDURE:

1. Assemble the circuit on a breadboard as per the diagram.

2. Set power supply to +12V.
3. Connect a sine wave (1kHz, 10Vpp) from the function generator to the base of Q2.
4. Observe both input and output on CRO channels.
5. Vary input amplitude and note switching points (UTP, LTP).
6. Change RE and Rc values to simulate different loop gains and repeat.

VI. OBSERVATIONS:
Parameter High Gain Low Gain
Rc1, Rc2 4.7kΩ 1kΩ
RE 470Ω 2.2kΩ
Output waveform Clean square wave Distorted sine
Hysteresis Present Absent
UTP (approx) +2V —
LTP (approx) –2V —

VII. CALCULATIONS:

BTECH II-II ECA Page 44

DEPARTMENT OF ECE

VIII. NATURE OF GRAPH:

WITH GAIN > 1, THE SCHMITT TRIGGER INPUT AND OUTPUT WAVEFORMS

WITH GAIN < 1, THE SCHMITT TRIGGER INPUT AND OUTPUT WAVEFORMS

BTECH II-II ECA Page 45

DEPARTMENT OF ECE

IX. INFERENCE:

 With gain > 1, the Schmitt Trigger behaves as expected, providing noise immunity and clear
switching.
 With gain < 1, feedback is weak, and the system cannot switch reliably — confirming the
importance of positive feedback.

X. PRECAUTIONS:

 Verify transistor pinouts.

 Ensure correct power polarity.
 Use a clean power supply (low ripple).
 Avoid parallax errors while reading CRO.
 Make tight, proper connections.

XI. TROUBLESHOOTING:

Problem Cause Fix

No output Power supply missing Check Vcc
Flickering output Low gain / weak feedback Reduce RE, increase Rc
No switching Incorrect input frequency Set generator to 1kHz

XII. RESULT:

The Schmitt Trigger was constructed and tested. It successfully converted a sine wave into a square
wave when loop gain > 1 and loop gain< 1.

XIII. EXTENSIONS:

 Use with photodiodes for light threshold detectors.

 Add hysteresis to analog sensors to prevent oscillation.
 Implement with op-amps for precision triggers.

XIV. APPLICATIONS:

 Signal cleaning and waveform shaping

 Switch debouncing
 Digital logic input conditioning
 ADC front-end signal conditioners

XV. VIVA QUESTIONS:

1. What is hysteresis in a Schmitt Trigger?

2. Define UTP and LTP.
3. What happens when loop gain < 1?
4. What is the role of the feedback resistor?
5. How does Schmitt Trigger differ from a basic comparator?

BTECH II-II ECA Page 46

DEPARTMENT OF ECE

EXPERIMENT NO-10:
BOOTSTRAP SWEEP CIRCUIT
(HARDWARE)

I. AIM:

. Design a Bootstrap sweep circuit using BJT and draw its output time base waveform.

II. EQUIPMENT REQUIRED:

Component Specifications Quantity

Resistors 100kΩ, 6.3kΩ, 10kΩ 1 each
Capacitors 0.1μF, 10μF, 100μF 1 each
Diode IN4007 1
Transistors 2N2369 (NPN) 2
Breadboard — 1
DC Power Supply 0–30V 1
CRO 20 MHz 1
Signal Generator 1Hz – 1MHz (square wave) 1
Connecting Wires — As needed

III. THEORY:

The Bootstrap Sweep Circuit produces a linear voltage ramp (positive-going sweep) used as a time-
base waveform in oscilloscopes and function generators.

 Q1 acts as a switch controlled by a gating waveform.

 Q2 functions as an emitter follower, charging the timing capacitor.
 When the gate pulse turns Q1 OFF, the capacitor starts charging via a constant current path.
 The diode ensures positive feedback during the sweep, enhancing linearity.

BTECH II-II ECA Page 47

DEPARTMENT OF ECE

IV. CIRCUIT DIAGRAM:

V. PROCEDURE:

1. Connect the circuit as per the circuit diagram.

2. Apply a square wave (gating waveform) to the base of Q1.
3. Power the circuit with a +15V DC supply.
4. Connect the CRO probe to the emitter of Q2 (output node).
5. Observe the sweep waveform on CRO.
6. Vary gate pulse width (Tg) and observe changes in sweep duration and amplitude.

VI. OBSERVATIONS:

Parameter Measured Value

Sweep amplitude VsV_sVs ~8V (Case 1), ~15V (Case 2)
Sweep interval TsT_sTs 1 ms (Case 1), 2 ms (Case 2)
Retrace time TrT_rTr Negligible (ideal)
Output waveform Positive-going ramp

BTECH II-II ECA Page 48

DEPARTMENT OF ECE

VII. CALCULATIONS:

VIII. NATURE OF GRAPH:

BTECH II-II ECA Page 49

DEPARTMENT OF ECE

IX. INFERENCE:

 The bootstrap sweep circuit generates a linear sweep voltage.

 Sweep amplitude and duration are controlled by RC time constant.
 The output closely matches the theoretical waveform under ideal conditions.

X. PRECAUTIONS:

 Check transistor pinouts before wiring.

 Ensure correct polarity for diode and capacitors.
 Use clean DC power and avoid loose connections.
 CRO probe must be grounded correctly.

XI. TROUBLESHOOTING:

Problem Cause Fix

No sweep observed Gate waveform missing Check signal generator
Non-linear sweep Faulty capacitor or diode Replace component
Reverse sweep Wrong transistor connection Verify circuit connections

XII. RESULT:

The Bootstrap Sweep Circuit was successfully implemented, and a positive-going linear sweep
waveform was obtained as per the design.

XIII. EXTENSIONS:

 Replace BJTs with MOSFETs for higher speed.

 Use op-amp based bootstrap for better linearity.
 Apply to horizontal deflection system in CRO.

XIV. APPLICATIONS:

 Oscilloscope time base circuits

 Radar and sonar systems
 Signal modulation and waveform synthesis
 Digital-to-analog time conversion

XV. VIVA QUESTIONS:

1. Define (a) Voltage time base generator, (b) current time base generator (c) linear time base
generator.
2. What is the relation between the slope error, displacement error and transmission error?

3. What are the various methods of generating time base wave-form?

4. Which amplifier is used in Boot-strap time base generator?

BTECH II-II ECA Page 50

DEPARTMENT OF ECE

EXPERIMENT NO-11:
MILLER SWEEP CIRCUIT
(HARDWARE)

I. AIM:

To Design a Miller sweep circuit using BJT and draw its output time base waveform

II. EQUIPMENT REQUIRED:

Component Specification Quantity

Resistors 100kΩ, 1kΩ 1 each
Capacitors 0.1μF, 10μF 1 each
Transistors BC107 (NPN) 2
Breadboard — 1
Power Supply 0–30V DC 1
Function Generator 1Hz–1MHz (square wave) 1
CRO 20 MHz 1
Connecting Wires — As needed

III. THEORY:

The Miller Sweep Generator is a type of time-base generator which produces a negative-going
ramp (sweep). The circuit uses:

 Q1 as a switching transistor to control the gating.

 Q2 as a common-emitter amplifier (inverting amplifier with high gain).

Working Principle:

 Initially, Q1 is ON, Q2 is OFF, and the output is at VCC

 A negative gate pulse at Q1 turns it OFF, and Q2 turns ON.
 Capacitor C discharges slowly through resistor R, causing a linear drop in collector voltage
of Q2 (negative ramp).
 The sweep time TS depends on the RC time constant.

Ts=R⋅C

BTECH II-II ECA Page 51

DEPARTMENT OF ECE

IV. CIRCUIT DIAGRAM:

V. PROCEDURE:

1. Connect the circuit as per the diagram on the breadboard.

2. Set the DC power supply to +15V.
3. Apply a negative-going square wave at Q1 base (gate).
4. Observe the output waveform on CRO from Q2 collector.
5. Adjust RC values and observe changes in sweep time.
6. Record and compare theoretical and experimental results.

VI. OBSERVATIONS:

Parameter Value

Supply Voltage (Vcc) +15V

Sweep Duration (Ts) ~1ms

Sweep Amplitude (Vs) ~10–12V

Output Waveform Negative Ramp

Slope Error (es) Minimal

BTECH II-II ECA Page 52

DEPARTMENT OF ECE

VII. CALCULATIONS:

VIII. NATURE OF GRAPH:

BTECH II-II ECA Page 53

DEPARTMENT OF ECE

IX. INFERENCE:

The Miller Sweep Circuit successfully generates a negative linear ramp waveform as expected.
The waveform matches theoretical behavior with minor slope error.

X. PRECAUTIONS:

 Check transistor pinouts and polarity.

 Ensure square wave input is properly timed.
 Avoid capacitor polarity errors.
 Use proper grounding for CRO and function generator.

XI. TROUBLESHOOTING:

Problem Likely Cause Fix

No ramp observed Incorrect gate signal Verify signal generator

Nonlinear ramp Faulty capacitor or wrong RC Replace or recalculate values

Output stuck high Q2 not switching Check transistor orientation

XII. RESULT:

The Miller Sweep Circuit was successfully constructed. A negative-going sweep was observed and
measured, validating circuit design.

XIII. EXTENSIONS:

 Convert to bidirectional ramp generator.

 Add transistorized retrace control.
 Use MOSFET for Q1 for faster switching.

XIV. APPLICATIONS:

 CRO time base generators

 Sawtooth waveform generators
 Radar sweep systems
 TV raster scanning

XV. VIVA QUESTIONS:

1. Which amplifier is used in Miller sweep circuit?

2. What type of sweep is generated?
3. Advantage over bootstrap circuit?
4. Slope error formula?
5. Input needed for linear sweep?.
6. Time base waveform generation methods?
7. When do we get sawtooth waveform?
8. Which error is most dominant?

BTECH II-II ECA Page 54

DEPARTMENT OF ECE

EXPERIMENT NO-12:
CONSTANT CURRENT SWEEP GENERATOR
(HARDWARE)

I. AIM: To Design a constant current sweep generator and draw input and output waveforms

II. EQUIPMENT REQUIRED

Component Specifications Quantity

NPN Transistor BC547 / 2N2222 1
Inductor 10 mH 1
Resistor (Rd) 1 kΩ 1
Diode 1N4007 1
DC Power Supply 0 – 30 V 1
Signal Generator 1 Hz – 1 MHz 1
CRO / DSO 20 MHz 1
Breadboard & Wires — Required

III. THEORY

BTECH II-II ECA Page 55

DEPARTMENT OF ECE

IV. CIRCUIT DIAGRAM

V. PROCEDURE (HARDWARE)

1. Connect the transistor (BC547) with the emitter to ground and base to a function generator
via a resistor (~10kΩ).
2. Connect collector to inductor (10 mH) in series with Rd (1 kΩ).
3. Place diode (1N4007) in reverse polarity to protect transistor during inductor discharge.
4. Apply +15V DC at collector supply (Vcc).
5. Apply square wave (~1 kHz, 5V) at the base of the transistor.
6. Observe collector voltage and inductor current waveforms on the CRO.

VI. OBSERVATIONS

Parameter Observed Value

Vcc 15 V
Input frequency 1 kHz
Sweep time (Ts) ~5 ms
i_L ramp rate 15V10mH=1.5A/ms\frac{15V}{10mH} = 1.5A/ms10mH15V=1.5A/ms
Collector voltage Falls to V_CE(sat) ~ 0.2V

BTECH II-II ECA Page 56

DEPARTMENT OF ECE

VII. CALCULATIONS

VIII. NATURE OF GRAPH

IX. INFERENCE

The transistor sweep generator effectively produces a linear current ramp across the inductor when
gated ON, and a natural exponential decay after. The collector voltage waveform complements this
behavior and matches theoretical expectations.

BTECH II-II ECA Page 57

DEPARTMENT OF ECE

X. PRECAUTIONS

 Ensure correct polarity of diode.

 Do not exceed inductor current rating.
 Use suitable base resistor to limit base current.

XI. TROUBLESHOOTING

Problem Solution
No sweep observed Check base drive signal
High collector voltage drop Check transistor biasing
Output spikes Ensure diode is properly oriented
CRO signal not visible Trigger properly on base signal

XII. RESULT

The current sweep generator was successfully constructed. A linear current ramp and corresponding
voltage drop were observed, matching the theoretical waveforms.

XIII. EXTENSIONS

 Use op-amp controlled transistor for controlled sweep rate.

 Integrate with DAC to convert ramp to digital sweep.
 Add comparator to create a current-controlled pulse generator.

XIV. APPLICATIONS

 Radar and LIDAR scanning

 CRT-based time base circuits
 Motor control with ramp-up current
 Function generators
 SMPS and analog waveform synthesis

XV. VIVA QUESTIONS

1. What is the function of the diode?

2. What kind of sweep is generated?
3. Why is the collector voltage low during sweep?
4. What affects the linearity of the sweep?
5. What is the time constant of decay?
6. What waveform is expected at the collector.

BTECH II-II ECA Page 58

DEPARTMENT OF ECE

EXPERIMENT NO-13:
SAMPLING GATE
(HARDWARE)

I. AIM

To Design unidirectional and bidirectional sampling gates

II. EQUIPMENT REQUIRED

S. No. Components Specifications

1 Resistors 1 kΩ, 10 kΩ
2 Capacitor 0.047 µF
3 Diode 1N4007
4 Function Generator 0–20 MHz
5 Cathode Ray Oscilloscope (CRO) Dual channel
6 Connecting Wires —
7 Breadboard —

III. THEORY

A sampling gate is an analog switching circuit that allows a portion of an analog input signal to pass
through only during a specific time interval, defined by a control signal. In ideal conditions:

 The output = input during the gate-ON (sampling) interval.

 The output = 0 when the gate is OFF.

The control signal is typically a square wave. Practical implementations often use diodes to allow or
block signal flow, depending on the control input.

IV. CIRCUIT DIAGRAM

V. PROCEDURE

1. Connect the components on the breadboard as per the circuit diagram.

BTECH II-II ECA Page 59

DEPARTMENT OF ECE

2. Connect:
o Signal Input (sinusoidal): 1 kHz, 5 Vpp.
o Control Input (square wave): 1 kHz, 5 Vpp.
3. Observe the output waveform on the CRO.
4. Vary the input frequency and amplitude while keeping the control signal fixed.
5. Repeat by varying the control signal and keeping the input fixed.
6. Record observations of the output waveform for each variation.

VI. OBSERVATIONS (HARDWARE)

Signal Input Control Input Output (Observed on CRO)

1 kHz sine, 5 Vpp 1 kHz square, 5 Vpp Gated portions of sine appear
500 Hz sine 1 kHz square Sine appears only during HIGH control
1 kHz sine 2 kHz square Shorter sampling windows seen
2 kHz sine 1 kHz square Multiple cycles sampled

VII. CALCULATIONS

VIII. NATURE OF GRAPH

IX. INFERENCE

The diode-based sampling gate effectively allows signal transmission only during the HIGH period
of the control signal, thus successfully replicating the ideal sampling gate behavior.

BTECH II-II ECA Page 60

DEPARTMENT OF ECE

X. PRECAUTIONS

1. Connect diode in correct orientation (anode/cathode).

2. Match amplitude levels of signal and control.
3. Use clean power supply to avoid distortions.
4. Avoid loose connections or floating grounds.

XI. TROUBLESHOOTING

Issue Cause Solution

No output seen Diode reverse biased Check diode orientation
Signal not sampled correctly Mismatched voltage levels Adjust signal and control amplitude
Distorted waveform Incorrect frequency setting Match signal and control timings

XII. RESULT

The sampling gate circuit using a diode was constructed and tested successfully. Output
waveform matched theoretical expectations during sampling intervals.

XIII. EXTENSIONS

 Implement multiple input sampling gates.

 Use FETs or analog switches instead of diode.
 Convert to digital control using microcontrollers.

XIV. APPLICATIONS

1. Analog multiplexers
2. D/A converters
3. Sample-and-hold circuits
4. Chopper-stabilized amplifiers
5. Sampling oscilloscopes

XV. QUESTIONS (Viva)

1. What is a sampling gate?

2. What does the control signal do in this circuit?
3. What is another name for a control signal?
4. Differentiate between logic gate and sampling gate.
5. Why do we need sampling gates?
6. What if the diode is reversed?
7. What is the function of the capacitor in the circuit?

BTECH II-II ECA Page 61

DEPARTMENT OF ECE

EXPERIMENT NO-14:
SCHMITT TRIGGER
(HARDWARE)

I. AIM:

To Prove practically Schmitt Trigger generates square wave

II. EQUIPMENT REQUIRED:

S.No Component / Equipment Specifications Quantity

1 Resistors 100Ω 1
6.8KΩ 1
3.9KΩ 1
3.3KΩ 1
2.2KΩ 2
2 CRO 20 MHz 1
3 Function Generator 1 MHz 1
4 Connecting Wires - As Required
5 DC Regulated Power Supply 0-30V, 1A 1
6 Transistors BC107 2
7 Capacitor 0.01 µF 1

III. THEORY:

A Schmitt Trigger is a bistable multivibrator that uses positive feedback to introduce hysteresis.
This hysteresis means the circuit has two threshold voltages:

 UTP (Upper Threshold Point)

 LTP (Lower Threshold Point)

This allows the circuit to convert a slowly varying input (like a sine wave) into a sharply defined
digital output (square wave), thus eliminating noise and making it useful in signal conditioning
applications.

It typically uses two transistors connected in a regenerative feedback loop. When the input crosses
UTP, the output flips state; it flips back only when the input crosses LTP in the reverse direction.

BTECH II-II ECA Page 62

DEPARTMENT OF ECE

IV. CIRCUIT DIAGRAM:

V. PROCEDURE:

1. Connect the circuit as per the diagram using the specified resistor and transistor values.
2. Apply a sine wave of 10 V peak-to-peak and 1 kHz frequency from the function generator to
the input.
3. Connect the input and output to the CRO using Channel 1 and Channel 2 respectively.
4. Observe and record the voltages at which the output switches (UTP and LTP).
5. Sketch the input sine wave and the resulting square wave on a time vs voltage graph.

VI. OBSERVATIONS:

Parameter Value
Input signal type Sine wave
Input signal amplitude 10 Vpp
Frequency 1 kHz
UTP (Upper Threshold) ~3.5 V (example)
LTP (Lower Threshold) ~1.2 V (example)
Output signal type Square wave

BTECH II-II ECA Page 63

DEPARTMENT OF ECE

VII. CALCULATIONS:

VIII. NATURE OF GRAPH:

IX. INFERENCE:

 A sine wave input is successfully converted into a square wave output using the Schmitt
Trigger.
 Hysteresis in the circuit prevents false triggering due to noise.

X. PRECAUTIONS:

1. Ensure transistor pin configuration (E-B-C) is correct.

2. Keep connections tight and avoid loose ends.
3. Use appropriate oscilloscope probe settings.
4. Observe correct polarity of capacitor.

BTECH II-II ECA Page 64

DEPARTMENT OF ECE

XI. TROUBLESHOOTING:

Problem Solution
No output observed Check transistor orientation & Vcc
No square waveform Confirm sine wave amplitude is sufficient
Output distorted Recheck resistor values, probe grounds

XII. RESULT:

A Schmitt trigger circuit was successfully constructed. The circuit converted the sine wave input to a
square wave output, demonstrating its bistable behavior and threshold switching.

XIII. EXTENSIONS:

 Use op-amp-based Schmitt Trigger for greater stability.

 Implement digitally using CMOS or TTL ICs.
 Use variable resistors to study hysteresis behavior dynamically.

XIV. APPLICATIONS:

1. Signal Conditioning
2. Noise Elimination
3. Wave Shaping
4. Pulse Generators
5. Comparator Circuits
6. Zero-Crossing Detectors

XV. VIVA QUESTIONS:

1. What is the other name of the Schmitt Trigger?

2. What are the applications of the Schmitt Trigger?
3. Define UTP and LTP?

BTECH II-II ECA Page 65

DEPARTMENT OF ECE

EXPERIMENT NO-15:
SWEEP CIRCUIT
(HARDWARE)

I. AIM:
To design Frequency division with sweep circuit

II. EQUIPMENT REQUIRED:

S. No Component Specification Quantity

1 Unijunction Transistor 2N2646 or equivalent 1
2 Resistors 1 kΩ, 10 kΩ 1 each
3 Capacitor 0.1 µF, 0.47 µF 1 each
4 DC Power Supply +15V 1
5 CRO / DSO 20 MHz 1
6 Breadboard — 1
7 Connecting Wires — As needed

III. THEORY:

BTECH II-II ECA Page 66

DEPARTMENT OF ECE

IV. CIRCUIT DIAGRAM:

V. PROCEDURE (Hardware)

1. Assemble the circuit as per the diagram.

2. Set the power supply to +15V.
3. Choose suitable values (e.g., R = 100 kΩ, C = 0.47 µF).
4. Connect CRO across resistor at base1 (B1) to observe output waveform.
5. Power ON the circuit and observe voltage waveform.
6. Measure T (sweep period) and calculate f (sweep frequency).
7. Vary R or C to observe change in frequency.

VI. OBSERVATIONS:

Component Value
R 100 kΩ
C 0.47 µF
VBB +15V
η (Eta) 0.65
Measured T ≈ 38 ms
Measured f ≈ 26 Hz

BTECH II-II ECA Page 67

DEPARTMENT OF ECE

VII. CALCULATIONS:

VIII. NATURE OF GRAPH (From CRO):

IX. INFERENCE:

 The waveform confirms typical UJT oscillator operation.

 Sweep period is independent of VCC, depends only on R, C, and η.
 Frequency can be controlled by tuning R or C.

BTECH II-II ECA Page 68

DEPARTMENT OF ECE

X. PRECAUTIONS:

1. Ensure correct pinout for UJT (Emitter, B1, B2).

2. Discharge capacitor before each connection.
3. Connect CRO probes with proper grounding.
4. Use appropriate resistor and capacitor rating for desired timing.

XI. TROUBLESHOOTING:

Problem Cause Solution

No waveform Incorrect pin configuration Check UJT datasheet
Distorted output Capacitor value too low Use higher C
Oscillation too fast R too low or C too low Use higher RC combination
No trigger pulses UJT not turning ON Check VBB and component health

XII. RESULT:

UJT relaxation oscillator successfully constructed and tested.

Output sweep waveform observed and measured sweep frequency matches theoretical calculations.

XIII. EXTENSIONS:

 Use the oscillator to trigger SCRs or Triacs.

 Replace R with variable resistor for sweep tuning.
 Chain with other logic blocks for pulse generation circuits.

XIV. APPLICATIONS:

1. Sawtooth or ramp waveform generator

2. Trigger pulse generator
3. Time-delay circuits
4. Switching applications
5. Wave-shaping circuits

XV. VIVA QUESTIONS:

1. What is the function of a UJT?

2. What is intrinsic stand-off ratio (η)?.
3. What are V_P and V_V?
4. Why is output taken from B1?

BTECH II-II ECA Page 69

DEPARTMENT OF ECE

SOFTWARE

BTECH II-II ECA Page 70

DEPARTMENT OF ECE

EXP. NO.1
CLASS A POWER AMPLIFIER
(SOFTWARE)
I.AIM: To Design transformer coupled class A power amplifier and draw the input and output
waveforms find its efficiency by using multisim software.

II.TOOLS/ EQUIPMENTS/APPARATUS REQUIRED:

I. Software tool :Multisim
APPARATUS REQUIRED:
Power supply 0-30V 1 No.
CRO 20 MHz 1 No.
Digital multi meter 1 No.
Signal generator 1Hz-1MHz 1 No.
COMPONENTS REQUIRED:
Resistors 33KΩ 1No
560Ω 1No
47KΩ 1No
Capacitors 22uf 1No
100uf 1No
Transistor BC107BP 1No
Transformer 50mH 1No

III.THEORY:
Power amplifiers are mainly used to deliver more power to the load. To deliver more Power it
requires large input signals, so generally power amplifiers are preceded by a series of voltage
amplifiers. In class-A power amplifiers, Q-point is located in the middle of DC-load line. So output
current flows for complete cycle of input signal. Under zero signal condition, maximum power
dissipation occurs across the transistor. As the input signal amplitude increases power dissipation
reduces.
For all values of input signal, the transistor remains in the active region and never enters into
cut-off or saturation region. When an a.c signal is applied, the collector voltage varies sinusoidally
hence the collector current also varies sinusoidally. The collector current flows for 360 o (full cycle)
of the input signal. i e the angle of the collector current flow is 360o.

BTECH II-II ECA Page 71

DEPARTMENT OF ECE

IV.CIRCUIT DIAGRAM:

V.PROCEDURE:
1. Open Multisim Software to design Common Emitter amplifier circuit
2. Select on New editor window and place the required component on the circuit window.
3. Make the connections using wire and set oscillator, (FG) frequency & amplitude.
4. Check the connections and the specification of components value properly.
5. Go for simulation using Run Key observe the output waveforms on CRO
6. Indicate the node names and go for AC Analysis with the output node
7. Observe the Ac Analysis and draw the magnitude response curve
8. Calculate the bandwidth of the amplifier
VI.OBSERVATIONS: Input voltage VI=50mV
S.No. Frequency(Hz) Gain in dB
1 1
2 10
3 100
4 1K
5 10K
6 100K
7 1M
8 10M
9 100M

BTECH II-II ECA Page 72

DEPARTMENT OF ECE

VII.CALCULATION:
1. Maximum gain in dB =
2. 3dB gain =
3. Lower cutoff frequency f1 =
4. Upper cutoff frequency f2 =
5. Bandwidth f2-f1 =

DC input power Pin (d.c) = VCC*ICQ

AC output power Po(a.c) =

% of efficiency = *100

VIII.NATURE OF GRAPH:
I. Output waveform

II. Frequency response

III. Graph

BTECH II-II ECA Page 73

DEPARTMENT OF ECE

IX.INFERENCE:
1. The efficiency observed is ___________ against theoretical maximum of 25%.
2. From the frequency response curve the following results are calculated
Maximum gain in dB =
3dB gain =
Lower cutoff frequency f1 =
Upper cutoff frequency f2 =
Bandwidth f2-f1 =

X.PRECAUTIONS:
1. All the connections should be correct.
2. Make sure while selecting the emitter, base and collector terminals of the transistor.

XI.TROUBLE SHOOTING:
1. Check the supply connections.

XII.RESULTS / CONCLUSIONS
Thus the frequency response of class-A amplifier is verified and band width, efficiency is
calculated.

XIII.EXTENSION:
1. Class a amplifier with transformer load

XIV.APPLICATIONS:
1. This is used for low power linear applications in audio and wideband RF range, where high
efficiency is not required.

XV.QUESTIONS:
1. Explain class A operation?
2. What is phase shift of input and output signals in class A operation.
3. What is the efficiency of class A power amplifier?
4. Distinguish class A and class B operations
5. Differentiate between voltage amplifier and power amplifier
6. Why power amplifiers are considered as large signal amplifier?
7. What are the different types of class-A power amplifiers available?
8. When does maximum power dissipation happen in this circuit?

BTECH II-II ECA Page 74

DEPARTMENT OF ECE

EXP.NO.-2
CLASS B POWER AMPLIFIER
(SOFTWARE)
I.AIM: To Design class B power amplifier and draw the input and output waveforms, find 2nd order
and above harmonics.

II.TOOLS/ EQUIPMENTS/APPARATUS REQUIRED:

I. Software tool: Multisim

APPARATUS REQUIRED:
Power supply 0-30V 1 No.
CRO 20 MHz 1 No.
Digital multi meter 1 No.
Function generator 1Hz-1MHz 1 No.
COMPONENTS REQUIRED:
Resistors 1kΩ, 470Ω 1No
220kΩ, 18kΩ, 1 Ω 2No
Capacitors 10 μ F/ 25 V 2No
Transistor BD 237(npn)) 1No
BD 242C(pnp)) 1No

III.THEORY:
Power amplifiers are designed using different circuit configuration with the sole purpose of
delivering maximum undistorted output power to load. Push-pull amplifiers operating either inClass-
B is class-AB is used in high power audio system with high efficiency. In complementary-symmetry
class-B power amplifier two types of transistors, NPN and PNP are used.
These transistors acts as emitter follower with both emitters connected together. In class-B
power amplifier Q-point is located either in cut-off region or in saturation region. So, that only 180 o
of the input signal is flowing in the output. In complementary-symmetry power amplifier, during the
positive half cycle of input signal NPN transistor conducts and during the negative half cycle PNP
transistor conducts. Since, the two transistors are complement of each other and they are connected
symmetrically so, the name complementary symmetry has come theoretically efficiency of
complementary symmetry power amplifier is 78.5%.

BTECH II-II ECA Page 75

DEPARTMENT OF ECE

IV.CIRCUIT DIAGRAM:

V.PROCEDURE:
1. Open Multisim Software to design Common Emitter amplifier circuit
2. Select on New editor window and place the required component on the circuit window.
3. Make the connections using wire and set oscillator, (FG) frequency & amplitude.
4. Check the connections and the specification of components value properly.
5. Go for simulation using Run Key observe the output waveforms on CRO
6. Indicate the node names and go for AC Analysis with the output node
7. Observe the Ac Analysis and draw the magnitude response curve
8. Calculate the bandwidth and efficiency of the amplifier

VI.OBSERVATIONS: Input voltage VI=50mV

S.No. Frequency(Hz) Gain in dB
1 1
2 10
3 100
4 1K
5 10K
6 100K
7 1M
8 10M
9 100M

BTECH II-II ECA Page 76

DEPARTMENT OF ECE

VII.CALCULATION:
1. Maximum gain in dB =
2. 3dB gain =
3. Lower cutoff frequency f1 =
4. Upper cutoff frequency f2 =
5. Bandwidth f2-f1 =
IC =IC1+IC2/2

ICQ =

DC input power Pin(d.c) = VCC*ICQ

AC output power Po(a.c) =

% of efficiency = *100

VIII.NATURE OF GRAPH:
I. Output waveform

II. Frequency response

BTECH II-II ECA Page 77

DEPARTMENT OF ECE

III. Graph

IX.INFERENCE:
1. The efficiency observed is ___________ against theoretical maximum of 78.5%.
2. From the frequency response curve the following results are calculated
Maximum gain in dB =
3dB gain =
Lower cutoff frequency f1 =
Upper cutoff frequency f2 =
Bandwidth f2-f1 =

X.PRECAUTIONS:
1. All the connections should be correct.
2. Make sure while selecting the emitter, base and collector terminals of the transistor.
3. Use matched pair NPN & PNP transistors for this experiments

XI.TROUBLE SHOOTING:
1. Check the supply connections.

XII.RESULTS / CONCLUSION:
1. Thus the frequency response of a class B complementary symmetry power amplifier is
designed and band width is calculated.

XIII.EXTENSION:
1. Class B amplifier with transformer load to drive high power loads.

BTECH II-II ECA Page 78

DEPARTMENT OF ECE

XIV.APPLICATIONS:
1. Audio power amplifiers
2. Public address systems
3. Radio power amplifiers

XV.QUESTIONS:
1. Differentiate between voltage amplifier and power amplifier?
2. Explain impedance matching provided by transformer?
3. Under what condition power dissipation is maximum for transistor in this circuit?
4. What is the maximum theoretical efficiency?
5. Sketch current waveform in each transistor with respective input signal?
6. What is the theoretical efficiency of the complementary stage amplifier?
7. How do you measure DC and AC output of this amplifier?
8. Is this amplifier working in class A or B?
9. How can you reduce cross over distortion?

BTECH II-II ECA Page 79

DEPARTMENT OF ECE

EXPERIMENT NO: 3

COMPLEMENTARY SYMMETRY PUSHPULL AMPLIFIER

(SOFTWARE)

I. AIM:
To simulate and analyze a complementary symmetry push-pull amplifier in Multisim,
demonstrating the elimination of crossover distortion using biasing diodes.

II. TOOLS & EQUIPMENT REQUIRED: MULTISIM

APPARATUS REQUIRED:
Power supply 0-30V 1 No.
CRO 20 MHz 1 No.
Digital multi meter 1 No.
Function generator 1Hz-1MHz 1 No.
COMPONENTS REQUIRED:
Resistors 1kΩ, 40.2KΩ 1No
10kΩ 2No
Capacitors 100μ F/ 25 V 3No
Transistor BC107(npn)) 1No
BC177(pnp)) 1No
Diodes IN4001 2No

III. THEORY:
The Class B amplifier circuit above uses complimentary transistors for each half of the waveform
and while Class B amplifiers have a much high efficiency than the Class A types, one of the main
disadvantages of class B type push-pull amplifiers is that they suffer from an effect known
commonly as Crossover Distortion.
It takes approximately 0.7 volts (measured from base to emitter) to get a bipolar transistor
to start conducting. In a class B amplifier, the output transistors are not "pre -biased" to an "ON"
state of operation. This means that the part of the output waveform which falls below this 0.7 volt
window will not be reproduced accurately as the transition between the two transistors (when
they are switching over from one to the other), the transistors do not stop or start conducting
exactly at the zero crossover point even if they are specially matched pairs.
The output transistors for each half of the waveform (positive and negative) will each
have a 0.7 volt area in which they will not be conducting resulting in both transistors being
"OFF" at the same time.
A simple way to eliminate crossover distortion in a Class B amplifier is to add two small
voltage sources to the circuit to bias both the transistors at a point slightly above their cut-off
point.. However, it is impractical to add additional voltage sources to the amplifier circuit so pn-
junctions are used to provide the additional bias in the form of silicon diodes.

BTECH II-II ECA Page 80

DEPARTMENT OF ECE

IV. CIRCUIT DIAGRAM:

Class B Power Amplifier circuit where crossover distortion is present

Class B Power Amplifier circuit where crossover distortion is eliminated

BTECH II-II ECA Page 81

DEPARTMENT OF ECE

V. PROCEDURE:
1. Open Multisim and Create a New Design
 Launch Multisim 14+.
 Click File → New → Blank Design.

2. Place Components

Use the Component Browser (Ctrl+W) to add:

Component Search Term Parameters

NPN Transistor BC107 or 2N2222 Default (β ≈ 100)
PNP Transistor BC177 or 2N2907 Default (β ≈ 100)
Diodes 1N4001 Forward voltage = 0.7V
Resistors 1kΩ, 10kΩ, 40.2kΩ -
Capacitors 100µF Polarized (25V)
Function Generator FG 1kHz, 1Vpp Sine Wave
Oscilloscope Oscilloscope Dual-channel
Power Supplies VCC and VEE +12V and -12V
3. Circuit Connections

For Unbiased Circuit (Distortion):

 Connect transistors without diodes (see diagram below).

 Link emitter of BC107 to emitter of BC177 (output node).

For Biased Circuit (No Distortion):

 Add two 1N4001 diodes between the bases of BC107 and BC177.
 Ensure diodes are forward-biased (anodes toward NPN base).

4. Wire the Circuit

 Input: Connect function generator to bases via capacitors.
 Output: Link emitters to load resistor (8Ω) and ground.
 Power: Connect VCC to collectors and VEE to ground.

5. Simulation Settings
1. Click Simulate → Run.
2. Use the Oscilloscope to view input (Channel A) and output (Channel B).
3. For THD Analysis:
o Go Simulate → Analyses → Distortion Analysis.
o Set frequency range: 1Hz to 10kHz.

VI. Observations & Comparisons

Condition Output Waveform Observation

Without Biasing Diodes Distorted output near zero-crossing (crossover distortion)
With Biasing Diodes Smooth sinusoidal output without distortion

BTECH II-II ECA Page 82

 DEPARTMENT OF ECE

VII. CALCULATIONS: Crossover Distortion Measurement

To quantify distortion:

3. Total Harmonic Distortion (THD) without biasing:

THD=V22+V32+…V1×100%

(where V1V = fundamental frequency, V2,V3= harmonics)

4. THD with biasing diodes:

o Expected to drop from ~10% (unbiased) to <1% (biased).

VIII. NATURE OF GRAPH:

Output waveform of Complementary symmetry Class B Power Amplifier circuit where

crossover distortion is present

Output waveform of Complementary symmetry Class B Power Amplifier circuit where

crossover distortion is eliminated

BTECH II-II ECA Page 83

DEPARTMENT OF ECE

IX. Inference

 Without Biasing Diodes:

Multisim simulation clearly shows flat spots in the output waveform at zero-crossings due to
the 0.7V dead zone, matching theoretical crossover distortion (THD ~10% in FFT analysis).
 With Biasing Diodes:
Simulation confirms distortion elimination as diodes provide 1.4V pre-bias, ensuring smooth
transitions (THD <1%). The output waveform becomes a clean sine wave.
 Key Insight:
Multisim’s virtual oscilloscope and distortion analyzer quantitatively prove that diode
biasing shifts operation from Class B to Class AB, eliminating distortion while maintaining
~65% efficiency.

X. Precautions for Multisim Simulation

 Component Models:
 Use accurate transistor models (e.g., BC107/BC177 or 2N2222/2N2907 pairs).
 Verify diode parameters (Vf=0.7V in 1N4001 properties).
 Grounding:
 Ensure all grounds are connected to the same reference node.
 Simulation Settings:
 Set "Initial conditions" to "User-defined" to avoid transient errors.
 Use "Interactive Simulation" mode for real-time adjustments.
 Probing:
 Place voltage probes at input/output nodes for clarity.

XI. Troubleshooting in Multisim

 Multisim-Specific Fix
 Issue
 Check if "Run/Stop Simulation" is activated (▶ button).
 No Output Waveform
 Verify diode direction (anode toward NPN base).
 Distorted Output
 Right-click → "Place Node" to fix disconnected wires.
 Floating Node Error

XII. Results (Simulation Data)

Parameter Without Diodes With Diodes

Output Waveform
THD (FFT) 8.2% 0.5%
Voltage Gain 3.1 3.0
Efficiency 72% (theoretical) 68% (due to Ibias)

BTECH II-II ECA Page 84

 DEPARTMENT OF ECE

XIII. Extensions (Multisim Experiments)

1. Thermal Analysis:
o Use "Temperature Sweep" (Simulate → Analyses) to observe bias stability.
2. Frequency Response:
o Run AC Analysis (1Hz–1MHz) to plot gain vs. frequency.
3. Alternative Biasing:
o Replace diodes with a VBE multiplier (2 resistors + transistor) and compare THD.
4. Load Variation:
o Test with RL = 4Ω and 16Ω to study power delivery.

XIV. Applications (Simulation-Validated)

1. Audio Amplifiers:
o Multisim confirms <1% THD, making it suitable for hi-fi systems.
2. RF Power Stages:
o Simulated efficiency >65% validates use in transmitters.
3. Motor Drivers:
o Push-pull operation handles bidirectional current (test with PWM input).

XV. Viva Questions

Theory:
1. Why does Multisim show flat spots without diodes?

2. How do diodes improve THD in simulation?

Simulation-Specific:
3. What happens if you reverse diodes in Multisim?
4. How to measure efficiency in Multisim?
5. Why does THD increase at high frequencies?

BTECH II-II ECA Page 85

DEPARTMENT OF ECE

EXPERIMENT NO. 4:
CLASS C POWER AMPLIFIER
(SOFTWARE)

I.AIM:
To design a Class C power amplifier in Multisim, analyze its input/output waveforms, and determine
resonant frequency (f₀) and bandwidth.

II.TOOLS/ EQUIPMENTS/APPARATUS REQUIRED:

Software tool :Multisim

APPARATUS REQUIRED:
Power supply 0-30V 1 No.
CRO 20 MHz 1 No.
Digital multi meter 1 No.
Function generator 1Hz-1MHz 1 No.
COMPONENTS REQUIRED:
Resistors 2.2kΩ, 100KΩ, 10KΩ, 560Ω 1No
Capacitors 100μ F/ 25 V 3No
0.1μ F 1No
Transistor BC107(npn)) 1No
Inductor 33mH 1No

III. THEORY

 A tuned amplifier uses a parallel LC tank circuit as its load to amplify signals over a narrow
frequency band.
 Resonant frequency (f₀):

Bandwidth (BW): The range of frequencies where gain ≥ 70.7% of maximum gain (BW = f₂
- f₁).

 Voltage Gain (Av):

BTECH II-II ECA Page 86

DEPARTMENT OF ECE

V. CIRCUIT DIAGRAM (MULTISIM)

VI. PROCEDURE (MULTISIM & HARDWARE)

1. Multisim Simulation
1. Build the Circuit:
o Place BC107, LC tank, and probes.
o Set function generator: 1Vpp, 1kHz sine wave.
2. Run Simulation:
o Use Interactive Simulation mode.
3. Measure f₀:
o Vary frequency until output peaks (use Frequency Sweep).
4. Find BW:
o Identify frequencies where Vo=0.707×VmaxVo=0.707×Vmax.

2. Hardware Verification
 Replicate the circuit on a breadboard.
 Compare results with Multisim.

VI. OBSERVATION TABLE:

Simulation Data Table
Frequency (Hz) V₀ (V) Gain (dB)
f₁ (Lower cutoff)
f₀ (Resonant)
f₂ (Upper cutoff)

BTECH II-II ECA Page 87

 DEPARTMENT OF ECE

VII. CALCULATIONS
4. Resonant Frequency (f₀):

5. Voltage Gain (dB):

6. Bandwidth:
BW=f2−f1
VIII. NATURE OF GRAPH:

IX. INFERENCE
 Multisim Results:
o Peak gain at f₀ ≈ _________.
o BW ≈ ________________
 Hardware vs. Simulation:
o <5% deviation acceptable; discrepancies due to component tolerances.

X. PRECAUTIONS
1. In Multisim:
o Ensure "Real Component Models" are enabled.
o Set "Initial Conditions" to User-Defined.
2. In Hardware:
o Use shielded cables to reduce noise.
o Verify transistor biasing.

BTECH II-II ECA Page 88

 DEPARTMENT OF ECE

XI. TROUBLESHOOTING

Issue Multisim Fix Hardware Fix

No output at f₀ Check LC connections Replace faulty transistor
Flat frequency response Adjust Q-factor (change R in LC tank) Verify inductor quality

XII. RESULTS

Parameter Multisim Value Hardware Value

Resonant frequency (f₀)
Bandwidth (BW)

XIII. EXTENSIONS
1. Multisim Advanced Analysis:
o Temperature Sweep: Test thermal stability.
o Monte Carlo Analysis: Study component tolerance effects.
2. Harmonic Distortion Analysis:
o Use FFT tool to measure THD.

XIV. APPLICATIONS
1. RF Transmitters:
o Efficient amplification at carrier frequencies.
2. TV Tuners:
o Selective frequency amplification.

XV. QUESTIONS
Multisim-Specific:
1. How to measure THD in Multisim?.
2. Why does simulated BW differ from theory?
3. Why is Class C unsuitable for audio?

BTECH II-II ECA Page 89

DEPARTMENT OF ECE

EXPERIMENT: 5
SINGLE TUNED VOLTAGE AMPLIFIER
(SOFTWARE)
I. AIM

To design and simulate a single tuned voltage amplifier in Multisim, analyze its frequency response
characteristics, and determine: Voltage gain, Bandwidth (BW)m, Quality factor (Q), Resonant
frequency (f₀)

II.TOOLS/ EQUIPMENTS/APPARATUS REQUIRED:

Software tool :Multisim

Apparatus Specification Quantity

Regulated Power Supply 0-20V DC 1
Function Generator 1Hz-10MHz 1
CRO 20MHz 1
Components Value Qty.
Transistor (BC107) - 1
Resistors 220Ω, 1 each
22kΩ,5.6kΩ,10kΩ,
1kΩ
Capacitors 100µF, 10µF, 1nF 1 each

Inductor 1mH 1
Breadboard & Wires - As needed

III. THEORY
 A tuned amplifier uses an LC tank circuit to amplify a narrow band of frequencies.
 Resonant frequency (f₀):


 Bandwidth (BW): Range where gain ≥ 70.7% of maximum (BW = f₂ - f₁).
 Quality Factor (Q):

 Gain in dB:

BTECH II-II ECA Page 90

 DEPARTMENT OF ECE

IV. CIRCUIT DIAGRAM

VII. PROCEDURE

1. Circuit Construction:
Build circuit with BC107, LC tank, and biasing network

Connect function generator (50mV) and oscilloscope probes

2. AC Analysis Setup:
Go to Simulate → Analyses → AC Sweep

Settings: 100Hz to 10MHz, logarithmic scale, 1000 points

3. Measurement Steps:
Run simulation and observe Bode plot

Identify f₀ at peak gain point

Determine f₁ and f₂ at -3dB points

Calculate Q = f₀/BW

4. Waveform Analysis:
Use transient analysis to view input/output at f₀

Verify phase relationship (0° at resonance)

BTECH II-II ECA Page 91

DEPARTMENT OF ECE

VI.OBSERVATIONS: Input voltage Vin=50mV

S.No. Frequency (Hz) Output voltage (Vo) Gain in dB
1 100
2 1K
3 10K
4 100K
5 1M
6 10M

Bandwidth (BW) = f₂ - f₁ = _____ Hz

Q-Factor = f₀ / BW = _____

VII. CALCULATIONS
1. Resonant Frequency (Theoretical):

2. Gain at f₀:

3. Q-Factor (Experimental):

VIII. GRAPH

BTECH II-II ECA Page 92

 DEPARTMENT OF ECE

IX. INFERENCE
1. Frequency Response:

o Maximum gain of 32dB occurs at 159kHz

o Bandwidth = 15kHz indicates moderate selectivity
2. Quality Factor:

o Q ≈ 10.6 confirms good frequency discrimination

o Can be improved by reducing resistive losses
3. Phase Characteristics:

o Zero phase shift at f₀

o Increasing lag/lead away from resonance

X. PRECAUTIONS (MULTISIM SPECIFIC)

1. Component Models:

o Use accurate transistor models (BC107 instead of generic NPN)

o Include parasitic capacitances for high-frequency accuracy
2. Simulation Settings:

o Set "Initial Conditions" to User Defined

o Use "Real Components" option for practical results
3. Measurement:

o Allow simulation to stabilize before taking readings

o Use fine resolution near resonant frequency

XI. TROUBLESHOOTING GUIDE

Issue Multisim Solution
No resonance peak Check LC connections; verify values

Flat frequency response Increase Q by reducing R in tank

Simulation errors Reduce time step; check ground connections

XII. RESULTS
Parameter Simulated Value Theoretical Value
Resonant frequency

Bandwidth

Quality Factor (Q)

Maximum Gain

BTECH II-II ECA Page 93

 DEPARTMENT OF ECE

XIII. EXTENSIONS
1. Double-Tuned Amplifier:

o Simulate two coupled LC tanks for wider bandwidth

o Compare selectivity with single-tuned version
2. Q Optimization:

o Parameter sweep of L/C values

o Study effect on bandwidth and gain
3. Non-Ideal Analysis:

o Add 5% component tolerances (Monte Carlo analysis)

o Include parasitic resistances

XIV. APPLICATIONS
1. Radio Receivers:

o Channel selection in AM/FM radios

o Typical Q range: 50-100 for good selectivity
2. TV Tuners:

o UHF/VHF signal amplification

o Requires stable Q against temperature variations
3. RF Communication:

o Used in transmitter output stages

XV. VIVA QUESTIONS

1. What does Q=10 imply practically?

2. How to increase Q without changing L/C?

3. Why does simulated BW differ from ideal calculation?

4. How to measure phase shift in Multisim?

5. What happens if we use Q=50?

BTECH II-II ECA Page 94

 DEPARTMENT OF ECE

EXPERIMENT: 6
BISTABLE MULTI VIBRATOR
(SOFTWARE)

I. AIM: To simulate a bistable multivibrator in Multisim, analyze its stable states, and study the
effect of commutating capacitors on switching speed.

II. TOOLS/ EQUIPMENTS/APPARATUS REQUIRED:

Software tool :Multisim
Apparatus Specification Quantity
CRO 20MHz (Dual Channel) 1
Function Generator 1Hz–1MHz 1
Power Supply 0–30V DC (Dual) 1
Components Value Qty.
Transistors (BC107) NPN 2
Resistors 1kΩ, 10kΩ, 100kΩ 2 each
Capacitors 0.001µF, 0.33µF,100nf, 330nF 2 each
Diodes (1N4007) - 4
Breadboard - 1

III. THEORY

1. Bistable Nature:

o Has two stable states (Q1 ON/Q2 OFF or Q1 OFF/Q2 ON).

o Requires external trigger to switch states.
2. Operation:Cross-coupled transistors maintain states via positive feedback.Triggering: Applied
pulse forces transition between states.

3. Commutation Capacitors (Speed-Up Caps):Reduce transition time by bypassing resistors during

switching.

4. Design Equations:Resistor Ratio:

Max Switching Frequency:

BTECH II-II ECA Page 95

 DEPARTMENT OF ECE

II. CIRCUIT DIAGRAM

V. PROCEDURE

1. Build the Circuit:

o Place components and connect as per schematic.

o Set VCC = 5V.
2. Triggering Setup:

o Connect function generator (1kHz, 5Vpp square wave) to trigger input.

3. Run Analyses:

o Transient Analysis: Observe VC1, VC2, VB1, VB2 waveforms.

o Parameter Sweep: Vary commutation capacitor (0.01µF to 1µF) to study effect on
transition time.
4. Measurements:

o Use cursors to measure:

 Stable state voltages (VC1, VC2).

 Transition time (tᵣ)

BTECH II-II ECA Page 96

 DEPARTMENT OF ECE

VI. OBSERVATIONS

Parameter State 1 (Q1 ON) State 2 (Q2 ON)

VC1 (Volts)
VC2 (Volts)
Transition Time (µs)

VII. CALCULATIONS

3. Theoretical fₘₐₓ:

4. Trigger Pulse Width:

tw≥2.2×R2×C

VIII. EXPECTED WAVEFORMS

BTECH II-II ECA Page 97

 DEPARTMENT OF ECE

 Top: Trigger pulse (Square wave).

 Middle: VC1 (Switches between 0V and VCC).
 Bottom: VC2 (Complementary to VC1).

IX. INFERENCE

1. Two stable states confirmed (VC1/VC2 are complementary).

2. Commutation caps reduce transition time by 86% (2µs vs. 15µs).
3. Max switching frequency matches theoretical prediction (55kHz).

X. PRECAUTIONS (MULTISIM-SPECIFIC)

1. Component Models:

o Use realistic transistor models (BC107 instead of generic NPN).

2. Grounding:

o Ensure all grounds are connected to same node.

XI. TROUBLESHOOTING

Issue Multisim Fix

No state transition Check trigger pulse connections

Asymmetric outputs Verify resistor values (10kΩ/100kΩ)

Simulation errors Reduce time step in transient analysis

XII. RESULTS

Parameter Simulated Value

Transition Time

Max Switching Freq.

Stable State Voltages

BTECH II-II ECA Page 98

 DEPARTMENT OF ECE

XIII. EXTENSIONS

1. Frequency Divider:

o Connect output to another bistable for ÷4 counter.

2. Monte Carlo Analysis:

o Study effect of component tolerances on switching speed.

XIV. APPLICATIONS

1. Digital Memory: Stores 1-bit data in CPUs.

2. Debounce Circuits: Eliminates switch noise in input devices.
3. Pulse Synchronization: Aligns signals in communication systems.

XV. XIV. VIVA QUESTIONS

1. How to measure transition time in Multisim?

2. What happens if commutation caps are increased to 1µF?

3. Why are diodes used across resistors?

4. How to convert this to a T flip-flop?

BTECH II-II ECA Page 99

 DEPARTMENT OF ECE

EXPERIMENT NO. 7
ASTABLE MULTIVIBRATOR
(SOFTWARE)
I. AIM:
To design an Astable Multivibrator using Multisim simulation, observe the waveforms at the
base and collector of transistors, and analyze the frequency and duty cycle.
II. TOOLS/ EQUIPMENTS/APPARATUS REQUIRED:
Software tool :Multisim

S.No Name of Component/Equipment Specifications Quantity

1 Resistors 3.9KΩ, 100KΩ 2 each
2 CRO (Cathode Ray Oscilloscope) 20MHz 1
3 Function Generator 1MHz 1
4 Connecting Wires - As required
5 DC Regulated Power Supply 0-30V, 1A 1
6 Transistor (BC 107) - 2
7 Capacitor 0.01 µF 2

III. THEORY:

An Astable Multivibrator is a free-running oscillator that continuously switches between two

unstable (quasi-stable) states without any external triggering. It consists of two cross-coupled
transistor amplifier stages with regenerative feedback through capacitors.

 The circuit produces a square wave output.

 The time period of oscillation is given by:

where R=R1=R2 and C=C1=C2

 The frequency of oscillation is:

BTECH II-II ECA Page 100

DEPARTMENT OF ECE

IV. CIRCUIT DIAGRAM:

V. PROCEDURE:

Design Calculation:

a. Calculate theoretical frequency using T=1.38×R×CT=1.38×R×C.

b. For R=100KΩ, C=0.01µF
Simulation Steps:

c. Open Multisim and construct the circuit.

d. Set power supply to 5V or 12V.
e. Run transient analysis and observe waveforms.
f. Measure ON time (T₁), OFF time (T₂), and frequency (f) using oscilloscope cursors.
VI. OBSERVATIONS:

Parameter Theoretical Value Simulated Value

Time Period (T) 1.38 ms _____ ms

Frequency (f) 725 Hz _____ Hz

ON Time (T₁) 0.69 ms _____ ms

OFF Time (T₂) 0.69 ms _____ ms

Duty Cycle (D) 50% _____ %

BTECH II-II ECA Page 101

 DEPARTMENT OF ECE

VII. CALCULATIONS:

VIII. NATURE OF GRAPH:

IX. INFERENCE:

1. The circuit generates square waves without external triggering.

2. Frequency matches theoretical calculations if components are ideal.
3. Duty cycle ≈ 50% when R1=R2R1=R2 and C1=C2C1=C2.

BTECH II-II ECA Page 102

 DEPARTMENT OF ECE

X. PRECAUTIONS:

1. Ensure correct transistor biasing (NPN vs PNP).

2. Verify capacitor polarity (if electrolytic).
3. Use proper oscilloscope settings (time/div, voltage/div).

XI. TROUBLESHOOTING:

Problem Possible Cause Solution

No oscillation Wrong transistor connections Check base-emitter-collector wiring

Unequal ON/OFF times Mismatched R or C values Ensure R1=R2R1=R2, C1=C2C1=C2

Distorted waveform Incorrect power supply Verify voltage (5V-12V)

XII. RESULTS:

 Theoretical Frequency: 725 Hz

 Simulated Frequency: _____ Hz
 Duty Cycle: ≈ 50%
 Conclusion: The Astable Multivibrator successfully generated square waves in Multisim.

XIII. EXTENSIONS:

1. Variable Duty Cycle: Replace resistors with potentiometers.

2. Frequency Modulation: Replace capacitors with a varactor diode.

XIV. APPLICATIONS:

1. Clock Generators in digital circuits.

2. LED Flashers & Tone Generators.
3. Pulse Width Modulation (PWM).

XV. QUESTIONS:

1. What is the role of capacitors in an Astable Multivibrator?

2. How can you modify the circuit to get a 30% duty cycle?

BTECH II-II ECA Page 103

DEPARTMENT OF ECE

EXPERIMENT NO-8:
MONOSTABLE MULTIVIBRATOR
(SOFTWARE)

I. AIM:
To simulate and analyze the stable and quasi-stable states of a monostable multivibrator using
BC107 transistors and verify the pulse width (T = 0.693RC).

II. TOOLS/ EQUIPMENTS/APPARATUS REQUIRED:

Software tool :Multisim
Component Multisim Part Number Value/Type
Transistors BC107 NPN BJT
Resistors R1, R2, R3, R4 1KΩ, 68KΩ, 2.2KΩ, 1.5KΩ
Capacitors C1, C2 1µF (Electrolytic)
Diode D1 1N4007
Power Supply V1 12V DC
Function Generator XFG1 1KHz, 2Vpp Square Wave
Oscilloscope XSC1 4-Channel

III. CIRCUIT DIAGRAM IN MULTISIM

BTECH II-II ECA Page 104

 DEPARTMENT OF ECE

IV. THEORY

 A monostable multivibrator has: One stable state (default state). One quasi-stable
state (temporary state triggered externally).
 Key Concepts:
Stable State: One transistor (Q1) is in cut-off, the other (Q2) is in saturation.
Quasi-Stable State: Triggering pulse flips the states temporarily. Automatically returns
to stable state after a time delay (T = 0.693RC).
 Applications:
Pulse width modulation, timers, and delay circuits.

V. SIMULATION PROCEDURE
1. Circuit Setup:
Built the circuit in Multisim as per the schematic.
2. Set power supply VCC = 12V.
3. Trigger Signal:
Configured function generator: 2Vpp, 1KHz square wave.
4. Oscilloscope Probes:
Channel A: Q1 Base (Vb1)
Channel B: Q2 Base (Vb2)
Channel C: Q1 Collector (Vc1)
Channel D: Q2 Collector (Vc2)

VI. OBSERVATIONS

A. Stable State (No Trigger)

 Q1:

o Vb1: ~0V (Cut-off)

o Vc1: 12V (High)
 Q2:

o Vb2: ~0.7V (Saturation)

o Vc2: ~0.2V (Low)

B. Quasi-Stable State (After Trigger)

Parameter Observation

Pulse Width (T) 47.1ms (Matches T = 0.693 × 68KΩ × 1µF)

Vb1 Exponential decay from 12V → 0V

Vc1 Drops to 0V for duration T

Vb2 Negative spike during trigger

Vc2 Rises to 12V for duration T

BTECH II-II ECA Page 105

 DEPARTMENT OF ECE

VII. CALCULATIONS

Theoretical Pulse Width:

T=0.693×R×C=0.693×68×103×1×10−6=47.1ms

VIII. NATURE OF GRAPH

IX. INFERENCE

Successful Simulation of Monostable Operation

The Multisim circuit correctly demonstrated the stable state (Q1 OFF, Q2 ON) and quasi-
stable state (Q1 ON, Q2 OFF) when triggered.

The automatic return to stable state after the delay period was observed, matching
theoretical behavior.

BTECH II-II ECA Page 106

 DEPARTMENT OF ECE

X. PRECAUTIONS

1. Circuit Setup

Component Values:

Double-check resistor and capacitor values (e.g., 68KΩ, 1µF) to ensure correct timing.

Transistor Models:

Use accurate BC107 models from Multisim’s library (or custom SPICE models if available).

2. Simulation Settings

Time Step:

Set a small enough time step (e.g., 1µs) to capture fast transitions accurately.

Initial Conditions:

Ensure the simulation starts with Q1 OFF and Q2 ON (stable state).

XI. TROUBLESHOOTING

Issue Solution in Multisim

No output pulse Check diode polarity & trigger signal.

Pulse width mismatch Verify RC values in the circuit.

Distorted waveforms Adjust ground references.

XII. RESULTS

1. Stable State Verified: Q1 (OFF), Q2 (ON) in default.

2. Quasi-Stable State:

o Duration = 47.1ms (Matches theory).

o Automatic return to stable state observed.

BTECH II-II ECA Page 107

 DEPARTMENT OF ECE

XIII. EXTENSIONS

1. Variable Pulse Width:

o Replaced C1 with 10µF → T increased to 470ms.

2. LED Indicators:

o Added virtual LEDs to collectors → Visual state confirmation.

XIV. APPLICATIONS

1. Timer Circuits: Simulated delay for relay control.

2. PWM Generation: Verified using variable RC.

XV. QUESTIONS & ANSWERS

Q1. Other names for monostable multivibrator?

Q2. Triggering type used?

Q3. Define transition time.

BTECH II-II ECA Page 108

DEPARTMENT OF ECE

EXPERIMENT NO-9:
SCHMITT TRIGGER WITH LOOP GAINS
(SOFTWARE)

I. AIM:

To simulate a transistor-based Schmitt Trigger in Multisim, study its response to sine wave input,
and observe the effect of changing loop gain.

II. TOOLS/ EQUIPMENTS/APPARATUS REQUIRED:

Software tool :Multisim

Component Value
NPN Transistor BC107 / 2N3904
Resistors 470Ω, 2.2kΩ, 4.7kΩ, 1kΩ, 10kΩ, 22kΩ
Capacitor 0.01 µF
Function Gen 1kHz, 10Vpp
Power Supply +12V
Ground —
Oscilloscope Dual channel

III. THEORY:

A Schmitt Trigger is a comparator with positive feedback that converts an analog input (like a sine
wave) into a digital output (like a square wave) using hysteresis.

 UTP (Upper Threshold Point): Input voltage at which output turns ON

 LTP (Lower Threshold Point): Input voltage at which output turns OFF

Using two transistors, we achieve hysteresis by feeding back the output from one transistor to the
base of the other

BTECH II-II ECA Page 109

DEPARTMENT OF ECE

IV. CIRCUIT DIAGRAM:

WITH GAIN > 1, THE SCHMITT TRIGGER DIAGRAM

WITH GAIN < 1, THE SCHMITT TRIGGER DIAGRAM

BTECH II-II ECA Page 110

DEPARTMENT OF ECE

V. PROCEDURE:

1. Open Multisim and place 2 NPN transistors.

2. Build biasing network for Q1 using R1 = 10kΩ, R2 = 4.7kΩ.
3. Connect collector resistors Rc1 and Rc2 = 4.7kΩ (high gain), 1kΩ (low gain).
4. Add RE = 470Ω (for high gain) or 2.2kΩ (for low gain).
5. Place Rf = 10kΩ from Q2 collector to Q1 base.
6. Connect a 1kHz sine wave (±5V) via a 0.01µF capacitor to Q2 base.
7. Power the circuit with +12V.
8. Use Oscilloscope to view input and output.
9. Run Transient Analysis for 10 ms.

VI. OBSERVATIONS:

Parameter High Gain Low Gain

Rc1, Rc2 4.7kΩ 1kΩ
RE 470Ω 2.2kΩ
Output waveform Square wave Non-switching
Hysteresis Present Weak/Absent

VII. CALCULATIONS:

BTECH II-II ECA Page 111

DEPARTMENT OF ECE

VIII. NATURE OF GRAPH:

WITH GAIN > 1, THE SCHMITT TRIGGER INPUT AND OUTPUT WAVEFORMS

WITH GAIN < 1, THE SCHMITT TRIGGER INPUT AND OUTPUT WAVEFORMS

BTECH II-II ECA Page 112

DEPARTMENT OF ECE

IX. INFERENCE:

Simulation confirms theoretical understanding:

 Loop gain > 1 → working Schmitt Trigger.

 Loop gain < 1 → loss of bistability.

X. PRECAUTIONS:

 Ensure all grounds are connected.

 Check transistor orientation.
 Adjust function generator amplitude to avoid clipping.

XI. TROUBLESHOOTING:

Problem Cause Fix

Output not toggling Low gain Reduce RE, increase Rc
No output Missing supply Add 12V Vcc
Flat output Incorrect signal input Set FG to 1kHz, ±5V

XII. RESULT:

The Schmitt Trigger was successfully simulated in Multisim, validating circuit theory and hysteresis
behavior.

XIII. EXTENSIONS:

 Simulate with op-amps.

 Add noise to input to test noise rejection.
 Explore auto-reset hysteresis with capacitors.

XIV. APPLICATIONS:

 Digital interfacing for analog sensors

 Zero-crossing detectors
 Pulse generation
 Switch debouncing

XV. VIVA QUESTIONS:

1. Why does gain < 1 fail in Schmitt Triggers?

2. Can Schmitt Triggers work with op-amps?
3. What is the effect of increasing RE?
4. What is the role of feedback in hysteresis?
5. How is Schmitt Trigger used in ADC circuits?

BTECH II-II ECA Page 113

DEPARTMENT OF ECE

EXPERIMENT NO-10:
BOOTSTRAP SWEEP CIRCUIT
(SOFTWARE)
I. AIM:

To simulate a Bootstrap Sweep Circuit in Multisim and observe the sweep waveform under ideal
and practical conditions.

II. COMPONENTS IN MULTISIM:

Component Value/Type
NPN Transistor 2N2369 (x2)
Resistors 100kΩ, 10kΩ, 5.6kΩ
Capacitors 0.1μF, 10μF, 100μF
Diode 1N4007
Function Generator Square wave, 1kHz
DC Power Supply +15V
CRO Dual channel
Ground —

III. THEORY:

The Bootstrap Sweep Circuit produces a linear voltage ramp (positive-going sweep) used as a time-
base waveform in oscilloscopes and function generators.

 Q1 acts as a switch controlled by a gating waveform.

 Q2 functions as an emitter follower, charging the timing capacitor.
 When the gate pulse turns Q1 OFF, the capacitor starts charging via a constant current path.
 The diode ensures positive feedback during the sweep, enhancing linearity.

The Bootstrap technique uses positive feedback to maintain voltage across the timing capacitor,
improving sweep linearity. A unity-gain emitter follower (Q2) buffers the output.

BTECH II-II ECA Page 114

DEPARTMENT OF ECE

IV. CIRCUIT DIAGRAM:

V. PROCEDURE:

1. Open NI Multisim and place components.

2. Connect transistors, resistors, and capacitors as per design.
3. Connect 15V DC supply to collector circuits.
4. Apply 1kHz square wave to base of Q1.
5. Run transient analysis for 5ms duration.
6. Observe sweep waveform on oscilloscope.

VI. OBSERVATIONS:

Parameter Value
Sweep amplitude ~8V to ~15V
Sweep duration 1–2ms
Retrace time Very short
Sweep shape Linear ramp

BTECH II-II ECA Page 115

DEPARTMENT OF ECE

VII. CALCULATIONS:

VIII. WAVEFORM ANALYSIS:

BTECH II-II ECA Page 116

DEPARTMENT OF ECE

IX. INFERENCE:

 The bootstrap sweep circuit generates a linear sweep voltage.

 Sweep amplitude and duration are controlled by RC time constant.
 The output closely matches the theoretical waveform under ideal conditions.

X. RESULT:

The Bootstrap sweep circuit was successfully simulated in Multisim. The output matched theoretical
expectations with linear ramp characteristics.

XI. PRECAUTIONS IN SIMULATION:

 Set correct time step for transient analysis.

 Ensure component models match real equivalents.
 Ground all reference points.

XII. TROUBLESHOOTING IN SIMULATION:

Problem Cause Solution

No waveform Missing gate signal Set function generator
Output distortion Incorrect capacitor polarity Flip capacitor or replace
Flat output Feedback path broken Reconnect diode and cap

XIII. EXTENSIONS:

 Add an op-amp buffer.

 Simulate high-speed sweep (>10kHz).
 Use for triangular waveform generation.

XIV. APPLICATIONS:

 CRO horizontal sweep

 Ramp generator
 Waveform modulation
 Function generator timing base

XV. VIVA QUESTIONS:

1. Define (a) Voltage time base generator, (b) current time base generator (c) linear time base
generator.
2. What is the relation between the slope error, displacement error and transmission error?

4. What are the various methods of generating time base wave-form?

5. Which amplifier is used in Boot-strap time base generator?

5. Which type of sweep does a bootstrap time-base generator produce?

6. What is the gain of the amplifier used in Bootstrap time base generator?

7. What is retrace time? Write the formula for the same for Bootstrap time base generator.

BTECH II-II ECA Page 117

DEPARTMENT OF ECE

EXPERIMENT NO-11:
MILLER SWEEP CIRCUIT
(SOFTWARE)

I. AIM:

To simulate a Miller Sweep Circuit in Multisim and observe the negative-going linear ramp
waveform.

II. COMPONENTS IN MULTISIM:

Component Type/Value
Transistors BC107 (x2)
Resistors 100kΩ, 1kΩ
Capacitors 0.1μF, 10μF
DC Power Supply +15V
Function Generator Square wave, 1kHz
Oscilloscope Dual-channel
Ground —

III. THEORY:

Same as hardware — Miller sweep circuit uses one transistor as a gate-controlled switch (Q1) and
another as a high-gain inverting amplifier (Q2). The capacitor discharge through a large resistor
forms a linear voltage ramp.

IV. CIRCUIT DIAGRAM:

BTECH II-II ECA Page 118

DEPARTMENT OF ECE

V. PROCEDURE:

1. Open NI Multisim.
2. Place two NPN transistors (BC107).
3. Add resistors (100kΩ, 1kΩ) and capacitors (0.1μF, 10μF).
4. Connect gate input to Q1 base.
5. Power the circuit using +15V.
6. Connect output probe to Q2 collector.
7. Run Transient Analysis for 10ms.
8. Observe output waveform on CRO.

VI. OBSERVATIONS:

Parameter Simulated Value

Sweep Voltage ~10V downward
Sweep Time ~10ms
Retrace Time Fast (~0.2ms)
Shape Negative Ramp

VII. CALCULATIONS:

BTECH II-II ECA Page 119

DEPARTMENT OF ECE

VIII. SIMULATED GRAPH:

IX. INFERENCE:

The Miller Sweep Circuit successfully generates a negative linear ramp waveform as expected.
The waveform matches theoretical behavior with minor slope error.

X. PRECAUTIONS (Simulation):

 Ensure time step is small in transient setup.

 Use appropriate component models (BC107).
 Ground all signal and power references.

XI. TROUBLESHOOTING:
Problem Solution
No sweep Check function generator setup
Clipped waveform Increase sweep time or voltage
Constant output Check connections and transistor polarity

BTECH II-II ECA Page 120

DEPARTMENT OF ECE

XII. RESULT:

The Miller Sweep Circuit was successfully simulated. Output waveform behavior confirmed
theoretical expectations with a clean, linear negative ramp.

XIII. EXTENSIONS:

 Add op-amp for precision control.

 Implement automatic retrace.
 Generate triangular waveform using dual Miller stages.

XIV. APPLICATIONS:

 Time base generator in CRO

 Signal modulation systems
 Radar scanning control
 Sawtooth wave synthesis

XV. VIVA QUESTIONS:

1. Which amplifier is used in Miller sweep circuit?

2. What type of sweep is generated?
3. Advantage over bootstrap circuit?
4. Slope error formula?
5. Input needed for linear sweep?.
6. Time base waveform generation methods?
7. When do we get sawtooth waveform?
8. Which error is most dominant?
9. Applications of time-base generators?
10. Role of transistor in this circuit?

BTECH II-II ECA Page 121

DEPARTMENT OF ECE

EXPERIMENT NO-12:
CONSTANT CURRENT SWEEP GENERATOR
(SOFTWARE)

I. AIM

To simulate a Current Sweep Circuit using a BJT and inductor in Multisim and analyze voltage
and current waveforms.

II. COMPONENTS IN MULTISIM

Component Value
NPN BJT 2N2222
Resistor 1kΩ
Inductor 10mH
Diode 1N4007
DC Supply +15V
Function Generator Square Wave (1kHz, 5V)
Ground —
Oscilloscope —

III. THEORY

BTECH II-II ECA Page 122

DEPARTMENT OF ECE

IV. CIRCUIT DIAGRAM

V. PROCEDURE IN MULTISIM

1. Open Multisim and place 2N2222 transistor.

2. Add 10mH inductor in series with 1kΩ resistor (Rd) between collector and +15V.
3. Connect diode (reverse bias) from collector to +15V.
4. Drive base via 10kΩ resistor from function generator (1kHz square wave).
5. Ground emitter.
6. Attach oscilloscope probes to:
o Collector (Channel A)
o Resistor (to measure current indirectly via voltage)
7. Run the simulation and observe waveforms.

VI. OBSERVATIONS (MULTISIM)

Parameter Value in Simulation

Supply Voltage (Vcc) 15 V
Input Gating Signal (v_B) Square wave, 5 Vpp, 1 kHz
Inductor (L) 10 mH
Rd 1 kΩ
Transistor Saturation Voltage (V_CE(SAT)) ~0.2 V
Time Duration of Sweep (Tₛ) 5 ms (based on gating pulse)
Peak Inductor Current (i_L) ~7.5 mA at end of ramp

BTECH II-II ECA Page 123

DEPARTMENT OF ECE

VII. CALCULATIONS (SIMULATION VALIDATION)

VIII. NATURE OF GRAPHS (MULTISIM)

BTECH II-II ECA Page 124

DEPARTMENT OF ECE

IX. INFERENCE

The simulation confirms that a current sweep circuit can be implemented using a BJT and an
inductor. The collector voltage and inductor current waveforms align with analytical expectations.

Key behaviors:

 Controlled linear current sweep (ideal for time-base and radar systems).
 Energy stored in the inductor is safely dissipated via Rd and diode.

X. PRECAUTIONS (MULTISIM)

 Ensure correct orientation of diode (cathode to Vcc).

 Check base signal amplitude and frequency – must drive transistor into saturation.
 Transistor should not be left floating; always connect ground properly.
 Use appropriate scope probe settings (X10 recommended for voltage stability).

XI. TROUBLESHOOTING (MULTISIM)

Issue Likely Cause Solution

No ramp current observed Base signal not applied Check function generator and connections
Current not returning to 0 Missing diode or reversed diode Verify diode placement and polarity
Collector stays high Transistor not switching Check V_BE threshold and base resistor
Spikes or noise in Improper scope grounding or probe Ground all return paths, use probe
waveform attenuation
Waveforms cut off Improper time/div settings on Adjust X-axis scale and trigger settings
scope

XII. RESULTS (MULTISIM)

The simulated current sweep generator behaves as expected:

 A linear ramp of current is achieved during the ON time.

 Exponential decay follows the OFF phase.
 Waveforms at the collector and across the inductor validate theoretical and hardware results.

BTECH II-II ECA Page 125

DEPARTMENT OF ECE

XIII. EXTENSIONS

 Automate sweep variation by controlling Vcc using DAC.

 Use MOSFET instead of BJT for better switching efficiency.
 Generate triangular waveforms by combining two sweep circuits.
 Integrate current feedback for adaptive waveform shaping.

XIV. APPLICATIONS

 Time base generators in CROs and oscilloscopes.

 Sweep circuits in radar scanning and sonar.
 SMPS (Switch Mode Power Supply) design for soft start.
 Analog ramp generators in waveform synthesis.
 Test equipment requiring predictable ramped currents.

XV. VIVA QUESTIONS (MULTISIM + HARDWARE)

1. What would happen if the diode is removed?

2. What ensures linearity in the current sweep?
3. How do you determine the slope of the sweep?
4. Why is Rd used in the circuit?
5. Can this circuit be used for voltage sweep?
6. What is the significance of the saturation voltage (V_CE(sat))?.
7. Why use Multisim for such a circuit?

BTECH II-II ECA Page 126

DEPARTMENT OF ECE

EXPERIMENT NO-13:
SAMPLING GATE
(SOFTWARE)

I. AIM: To simulate and analyze the behavior of unidirectional and bidirectional sampling
gates using Multisim.

II. COMPONENTS (VIRTUAL)

 1N4007 Diode
 Resistors: 1 kΩ, 10 kΩ
 Capacitor: 0.047 µF
 Voltage Sources (Function Generator):
o Sine Wave: 1 kHz, 5 Vpp
o Square Wave: 1 kHz, 5 Vpp
 Oscilloscope (Virtual)
 Ground Terminals and Wiring Tools

III. THEORY

A sampling gate is an analog switching circuit that allows a portion of an analog input signal to pass
through only during a specific time interval, defined by a control signal. In ideal conditions:

 The output = input during the gate-ON (sampling) interval.

 The output = 0 when the gate is OFF.

The control signal is typically a square wave. Practical implementations often use diodes to allow or
block signal flow, depending on the control input.

IV. CIRCUIT DIAGRAM

BTECH II-II ECA Page 127

DEPARTMENT OF ECE

V. PROCEDURE

1. Build the circuit in Multisim per the diagram.

2. Configure:
o Signal: Sine wave, 1 kHz, 5 Vpp.
o Control: Square wave, 1 kHz, 5 Vpp, 50% duty.
3. Observe all three waveforms: input, control, and output.
4. Run time-domain transient analysis.
5. Vary input and control to analyze gating behavior.
6. Note how the output waveform changes with timing.

VI. OBSERVATIONS (Multisim)

Input Signal Control Signal Output Waveform

1 kHz sine 1 kHz square Sine sampled at HIGH
500 Hz sine 1 kHz square Smaller sine samples
1 kHz sine 2 kHz square Two samples per cycle

VII. CALCULATIONS

VIII. NATURE OF GRAPH (Multisim)

BTECH II-II ECA Page 128

DEPARTMENT OF ECE

IX. INFERENCE

Multisim accurately models the sampling operation using ideal diode behavior. It validates the real-
world behavior of sampling gates.

X. PRECAUTIONS (Multisim)

 Use correct pulse settings for control.

 Ground both sources.
 Match voltage amplitudes to diode bias conditions.
 Use transient analysis to visualize time-domain signals.

XI. TROUBLESHOOTING (Multisim)

Problem Cause Fix

Output flatline Diode orientation wrong Flip diode terminal

No output waveform Unconnected signal source Check all connections

Distorted gating Misaligned control and signal Adjust timing settings of generators

XII. RESULT

Multisim simulation confirms theoretical gating behavior.Sampled output aligns with timing window
from control signal.

XIII. EXTENSIONS

 Add logic-controlled MOSFET switch.

 Automate gate control using timers.
 Add a hold circuit to form sample-and-hold stage.

XIV. APPLICATIONS

Same as hardware section:

 D/A Converters
 Multiplexing
 Sample-and-hold
 High-precision amplifiers

XV. QUESTIONS (Viva)

1. What is a sampling gate?

2. What does the control signal do in this circuit?
3. What is another name for a control signal?
4. Differentiate between logic gate and sampling gate

BTECH II-II ECA Page 129

DEPARTMENT OF ECE

EXPERIMENT NO-14:
SCHMITT TRIGGER
(SOFTWARE)

I. AIM

To simulate and observe the operation of a Schmitt Trigger using Multisim, and to confirm the
generation of a square waveform from a sine wave input, while verifying hysteresis behavior and
threshold switching.

II. EQUIPMENT REQUIRED : MULTISIM

S.No Component Specification

1 Resistors 100Ω, 6.8kΩ, 3.9kΩ, 3.3kΩ, 2.2kΩ (2×)
2 Transistors (NPN) BC107 (or 2N2222) × 2
3 Capacitor 0.01 µF
4 Signal Generator 10 Vpp Sine, 1 kHz
5 Oscilloscope Dual-channel
6 DC Power Supply +12V
7 Ground, wires —

III. THEORY

A Schmitt Trigger is a bistable circuit that converts a sine or noisy analog signal into a clean
digital square wave by applying hysteresis through positive feedback.

 The circuit switches output states at two different input voltages:

o UTP (Upper Threshold Point)
o LTP (Lower Threshold Point)
 This hysteresis loop prevents multiple transitions from noise or small variations near
threshold.
 The behavior is realized using two NPN transistors, feedback resistors, and biasing
networks.

BTECH II-II ECA Page 130

DEPARTMENT OF ECE

IV. CIRCUIT DIAGRAM (Multisim Layout)

V. SIMULATION PROCEDURE

1. Open Multisim and begin a new project.

2. Place 2 BC107 NPN transistors.
3. Add the following resistors:
o 6.8kΩ (RC1), 3.3kΩ (RC2), 100Ω, 3.9kΩ, and two 2.2kΩ resistors.
4. Connect a 0.01 µF capacitor between signal input and Q2 base.
5. Use a function generator configured to:
o Sine wave
o 10 Vpp
o 1 kHz
6. Add DC Power Source (12V) to transistor collectors.
7. Ground the emitter of both transistors.
8. Connect oscilloscope probes:
o Channel A: Signal input
o Channel B: Q2 collector (Output)
9. Run Transient Analysis for 20 ms.
10. Observe and record waveforms and switching thresholds.

BTECH II-II ECA Page 131

DEPARTMENT OF ECE

VI. OBSERVATIONS FROM MULTISIM

Parameter Value
Input Sine wave, 10 Vpp, 1 kHz
Output Square wave
Upper Threshold (UTP) ~3.2 V
Lower Threshold (LTP) ~1.4 V
Vcc +12 V
Hysteresis Observed Yes

VII. CALCULATIONS

VIII. NATURE OF GRAPH

IX. INFERENCE

 The circuit functions correctly in simulation and mimics expected Schmitt Trigger behavior.
 Output waveform clearly switches only at threshold voltages, producing noise-immune
square wave from analog input.

BTECH II-II ECA Page 132

DEPARTMENT OF ECE

X. PRECAUTIONS

1. Ensure transistors are not reversed.

2. Double-check sine wave amplitude is large enough to cross UTP/LTP.
3. Ground all components correctly.
4. Avoid overlapping signal and control paths in simulation for clarity.

XI. TROUBLESHOOTING

Issue Possible Cause Fix

Verify function generator and
No output waveform No input signal or transistor off
wiring
No square wave
Input amplitude too small Increase signal to exceed UTP/LTP
switching
Clipping in waveform Vpp too large or CRO scaling issue Adjust oscilloscope scale
Wrong resistor values or
Flat output Cross-check all resistor placements
connections

XII. RESULT

The Schmitt Trigger circuit was successfully simulated using Multisim.

The simulation confirmed the generation of a square wave from a sine wave input and validated
the positive feedback behavior via hysteresis.

XIII. EXTENSIONS

 Replace BJT with Op-Amp for precision.

 Design variable UTP/LTP by adjusting feedback resistors.
 Use Schmitt Trigger as zero-crossing detector or noise filter in digital circuits.

XIV. APPLICATIONS

1. Waveform shaping (e.g., sine to square)

2. Switch debouncing
3. Analog-to-digital signal conditioning
4. Noise immunity enhancement
5. Oscillator circuits

XV. VIVA QUESTIONS

1. What is the main function of a Schmitt Trigger?

2. What are UTP and LTP?
3. What causes hysteresis in this circuit?
4. Why are two transistors used?
5. Where is the output taken from in this circuit?

BTECH II-II ECA Page 133

DEPARTMENT OF ECE

EXPERIMENT NO-15:
SWEEP CIRCUIT
(SOFTWARE)

I. AIM:

To simulate and analyze the operation of a frequency divider using a Unijunction Transistor
(UJT) relaxation oscillator in Multisim, and to observe its waveform characteristics including
sweep frequency and trigger pulses.

II. EQUIPMENT REQUIRED (Virtual Components in Multisim):

S.No Component Specification

1 UJT 2N2646
2 Resistor 100 kΩ
3 Capacitor 0.47 µF
4 DC Power Supply +15 V
5 Virtual Oscilloscope Dual Channel
6 Ground —
7 Virtual Wire Tools —

III. THEORY:

A UJT relaxation oscillator functions by charging a capacitor through a resistor until the capacitor
voltage reaches a threshold (V_P) at which the UJT turns ON, discharging the capacitor rapidly and
generating a trigger pulse.This pulse generation occurs at regular intervals, thereby acting as a
frequency divider or pulse generator. The frequency of oscillation depends on the resistor-
capacitor (RC) time constant and the intrinsic stand-off ratio (η) of the UJT

BTECH II-II ECA Page 134

DEPARTMENT OF ECE

IV. CIRCUIT DIAGRAM (Multisim Layout):

V. PROCEDURE (Multisim Simulation)

1. Open NI Multisim and create a new schematic.

2. From the component library, place:
o UJT (2N2646)
o 100 kΩ resistor
o 0.47 µF capacitor
o +15V DC power source
o Ground
o Oscilloscope
3. Wire the components:
o Connect R and C in series to emitter (E).
o Connect B1 to ground via 1 kΩ resistor.
o Connect oscilloscope channels:
 CH A → Across capacitor
 CH B → Across R1 at Base 1
4. Set the DC power supply to +15V.
5. Open Simulation → Analysis → Transient Analysis
o Run for 100 ms with time step 0.1 ms
6. Observe and record output waveform characteristics.

BTECH II-II ECA Page 135

DEPARTMENT OF ECE

VI. OBSERVATIONS:

Parameter Value
Resistor (R) 100 kΩ
Capacitor (C) 0.47 µF
VBB (Power Supply) +15V
η (Eta) 0.65
Measured Period (T) ≈ 49 ms
Measured Frequency ≈ 20.4 Hz
Output Sharp negative pulses at B1

VII. CALCULATIONS:

VIII. NATURE OF GRAPH (Multisim Output):

IX. INFERENCE:

 The UJT oscillator simulated correctly in Multisim.

 The output waveform confirms successful sweep generation and frequency division.
 The time period of pulses matches closely with theoretical RC-based calculation.

BTECH II-II ECA Page 136

DEPARTMENT OF ECE

X. PRECAUTIONS:

1. Ensure UJT pins (E, B1, B2) are correctly connected.

2. Keep probe grounding consistent in the simulator.
3. Set appropriate transient simulation time (≥ 100 ms).
4. Use realistic values for R and C (not too small or too large).

XI. TROUBLESHOOTING:

Problem Cause Solution

No waveform Incorrect UJT pinout Check UJT datasheet
Irregular pulses Wrong component values Adjust R or C to proper range
Flatline output Missing power supply Connect and enable VBB
Unstable oscillation Floating nodes Ensure grounding and complete wiring

XII. RESULT:

The frequency divider using a UJT relaxation oscillator was successfully simulated in Multisim.
Observed waveforms and timing confirm correct operation, and theoretical frequency calculations
match simulation.

XIII. EXTENSIONS:

 Add a pulse-shaping stage (e.g., Schmitt trigger) to clean the output.

 Use multiple UJT stages for frequency cascading.
 Integrate with logic circuits or counters for event triggering.

XIV. APPLICATIONS:

1. Pulse generator
2. Ramp/Sawtooth waveform generator
3. SCR and Triac triggering
4. Time-delay circuits
5. Digital clock dividers

XV. VIVA QUESTIONS (Multisim)

1. What is the role of a UJT in this circuit?

2. What determines the frequency of the sweep?
3. Why do we observe sawtooth at the capacitor and pulses at B1?.
4. Can we adjust the frequency?
5. Why is this called a frequency divider?

BTECH II-II ECA Page 137