522 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL 36, NO 3.

MARCH 1989

Short-Channel Effects in SO1 MOSFET’s

SURYA VEERARAGHAVAN, STUDENT MEMBER, IEEE, AND JERRY G. FOSSUM, FELLOW, IEEE

Absfract-Short-channel effects in thin-film silicon-on-insulator (SOI) traded off for a reduced saturated drain current related to
MOSFET’s are examined, theoretically and experimentally, and are charge coupling and carrier velocity saturation, and pos-
shown to be unique because of dependences on film thickness and body
and back-gate (substrate) biases. These dependences enable control of
sibly an increased hot-carrier-induced degradation.
threshold-voltage reduction, channel-charge enhancement due to a In Section 111, we present evidence for a short-channel
drain bias, carrier velocity saturation, channel-length modulation and effect exclusive to SO1 MOSFET’s whereby the back-sur-
its effect on output conductance, as well as device degradation due to face charge condition (i.e., accumulation or depletion)
hot carriers in short-channel SO1 MOSFET’s. Furthermore, a short- depends on the channel length and drain bias as well as
channel effect exclusive to SO1 MOSFET’s, “back-surface charge
modulation,” is described. Because of the unique short-channel ef-
the body and back-gate biases. We discuss the relevance
fects, we note that the use of SO1 MOSFET’s in VLSI circuits provides of this effect to device design and model selection for cir-
the designer with additional flexibility as compared to hulk-MOSFET cuit simulation.
design. Various design trade-offs are discussed.
11. ANALYSIS
I. INTRODUCTION A. Threshold Voltage Reduction
In thin-film SO1 MOSFET’s, the back gate participates
Et NHANCEMENT-MODE MOSFET’s fabricated on
hin silicon-on-insulator (SOI) films have recently re-
ceived much attention in VLSI applications due to im-
in the depletion-charge sharing [2] with the front gate,
source, and drain, and thereby influences the threshold-
proved isolation, reduced parasitic capacitance, and en- voltage reduction. In this section, we extend previous
hanced radiation hardness as compared to devices studies [3], [4] of this effect by characterizing its voltage
fabricated using bulk technology. Now, there is increas- dependences.
ing evidence that SO1 MOSFET’s also provide additional Consider the p-channel MOSFET of channel length L
device and circuit design flexibility when scaled down to and uniform body doping No fabricated on a thin SO1 film
VLSI dimensions because of unique short-channel effects. of thickness tb shown in Fig. 1. For zero drain-to-source
In Section I1 we investigate these short-channel effects, voltage V,, and a (front-) gate voltage VCfsthat induces
and we show how they can be controlled by the appropri- strong inversion at the front surface, the film may be as-
ate biasing of the back gate (i.e., the underlying substrate) sumed to be completely depleted except for the charge in
and/or the film body, or by changing the film thickness. the channel and a possible layer of accumulation charge
These controls, which stem from the influence of the un- at the back surface. The potential in the film is given by
derlying (back) oxide-film interface on the potential dis- the solution of the Poisson equation with fixed depletion
tribution in the film, are characterized by experimentally charge, without regard to the carrier-continuity equation.
isolating the short-channel effects in a variety of devices The depletion charge Qb(eff) controlled (shared) by the
(with body contacts), using the insight afforded by nu- front and back gates can be expressed as [ l ]
merical simulations and a previously developed physical
model [ l ] .
In general, our study reveals that the threshold-voltage
reduction by charge sharing, drain-induced (channel) where Q b ( = qN,t,) is the total charge per unit area in
charge enhancement (drain-induced barrier lowering in the (fully depleted) film and d is the distance over which
weak inversion), and channel-length modulation (and the back-surface potential varies from the source/drain-
consequently, the saturated drain conductance) are best body junction built-in potential Vb; ( < 0 ) to some value
controlled by scaling the film thickness with the channel \ k s b O midway between the source and drain (see Fig. 1).
length and by biasing the back gate (substrate) to accu- The effective depletion-charge density in (1) is used in
mulate the back surface. However, we show that these a one-dimensional approximation of the Poisson equation
improvements due to back-surface accumulation must be to give the threshold voltage, which approaches the exact
one-dimensional solution [5]as L tends to infinity. As long
Manuscript received June 10, 1988; revised August 31, 1988. This work as \ k s b O stays constant as L is reduced, the reduction in
was supported by Harris Semiconductor, Melbourne, FL.
S. Veeraraghavan was with the Department of Electrical Engineering, threshold voltage A VTfcan be written as
University of Florida, Gainesville, FL 3261 1. He is now with Motorola,
Inc., Austin, TX 78762.
J. G . Fossum is with the Department of Electrical Engineering, Uni-
versity of Florida, Gainesville, FL 3261 1 ,
IEEE Log Number 8825918.

0018-9383/89/0300-0522$01.OO 0 1989 IEEE

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VEERAKAGHAVAN AND FOSSUM. SHOKI-CHANNEL b.FFF.CIS I N Sol 21OSFET.S 523

‘GfS o.20 I

‘d’ bur ie d
<
L ’ oxide

1
d
“GbS
Fig. I . SO1 MOSFET structure with a simple charge-sharing representa- I ,.,,I,,

tion b) L\ hich the completely depleted tilni (doping den\it) N,,) is par- Fig. 2 Measured threshold-\ oltagtt reduction .l V , , ( L. 1 for t \ \ o \et\ of SO1
titioned into region\ “conti-olled” by the gates. \ource. and drain p-channel MOSFET’s of tilrn thickncsae\ I,, = 0.8 piii (solid lines) and
1.3 giii (dotted lines) with identical pi-ocessing schedule\. at t w o differ-
ent back-gate (substrate) biases. V,,,,, = 2 0 V ( r ) and - 5 V (.. ) cor-
where Cot-= ~ , , , / f , ~is~ the front-oxide capacitance. The responding to back-hurfnce accumulation and depletion. respectively. The
distance 2 is related to the bias by defining it in terms of et to 2 V in a l l the nieasureiiients to deplete the film
and make the thin-film analysi\ applicable For ;ill d e i i c e \ . the front and
an effective electric field (see Fig. 1): back gate-oxide thicknesses are I,,, = 32.5 nni and /(,,, = 370 nm. and
the tilni-doping density i \ N,, = 2 X I O ” c11i ‘.

Eh(eff)
comprises fringing fields from the back-gate oxide,
controlled by the back-gate bias VG,,s, as well as the com-
ponent from the junction depletion region [ 11. Note from
(3) that for fixed \E,hO,an increase in El,(eff)
by any means
will reduce d and hence the charge sharing. For example,
this may be done by increasing the film doping [6].
When the back surface is accumulated by a large posi-
tive VGhs,\EshOis pinned at the body voltage VB,y.In this
case, A VTf is proportional to r,,/L as in (2). Then. if the
film is made thinner as its lateral dimensions are scaled,
VTfwill not decrease (in magnitude) as much as if f h were
kept constant. We demonstrate this effect in Fig. 2 where
measured A VTfversus L and V,,, are plotted for two sets
of SO1 MOSFET’s fabricated identically on SO1 films of
different f/,.
In addition to the dependence on thickness, the mea-
sured A VTfplotted in Fig. 2 shows a dependence on V,,,.
When V,,, is decreased to deplete the back surface, A VTf
is increased. Based on the preceding discussion, this de-
pendence is explained by noting that the fringing fields in
El,(eff)decrease, and hence d in (3) and the charge shared
by the source and drain increase.
This effect of reducing the fringing fields in E,,,,,, is
(b)
further clarified by a PISCES [7] simulation of an SO1
Fig. 3 . PISCES-simulated equipotential (9’)contours i n increments of 0.1
MOSFET with L = 1 .O pm in strong inversion. The equi- V for a I,, = 0.27 pni p-channel SO1 MOSFET with ( a ) the back surface
potential contours plotted in Fig. 3 for the cases of back- accumulated ( V,,,,, = 10 V ) . and ( b ) the back surface depleted i =

surface accumulation ( VG,,s = 10 V ) and back-surface de- 0 V ) . Only the contours for V,>,< 9’ < Vi,, + 1 V are hhown. I n both
cases. V,,s = 0 V (linear region). VI;,$ = - 2 . 5 V (strong inversion).
pletion ( V C h s = 0 V ) show that indeed as VGhsdecreases, and the (minority-) electron q~iaai-Fcrmipotential is set iit 0 V .
Eh(cff) decreases, causing d and A VTtto increase, as men-
tioned above.
Note in Fig. 3 that as VG,,7is decreased and the back sus VGbsfor a MOSFET with a mask L = 1 .O pm, show-
surface is depleted, \E,/,” decreases and ultimately would ing a maximum in A VTt,for fixed VBs,as the back surface
approach V,; as the back surface is inverted. Thus, we is swept from accumulation ( VGl,s= 20 V ) to inversion
note from (3) that the A V , ( Vr;i,s)trend discussed above ( VGiIs= - 5 V ) . (The dependence of A V , on VBsfollows
is reversed as ( *,5/,o-V/,,)approaches zero. This reversal the trend in bulk MOSFET’s: As the reverse bias on the
is illustrated in Fig. 4 where we plot measured A VTfver- drainisource-body junction is increased. A VTt increases,

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524 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 36. NO. 3 . MARCH 198')

and Vv(ef,) is a measure of the modulation of channel

charge at the source due to the two-dimensional electric
field in the film, i.e., due to DICE. We note, therefore,
from (4) that the characterization of the channel charge
and hence the device conductance deviate from that pre-
dicted by the gradual channel approximation as p in-
creases, or as the back surface goes from accumulation to
depletion. Also, we note from (4) that the two-dimen-
sional DICE effect is diminished as t b decreases.
This control of the two-dimensionality of the potential
distribution in the film is demonstrated by a PISCES [7]
VB5-8V
simulation of the device in Fig. 3 with V,, = -2.0 V.
' ~ ' ~ i " ' i " " ' ~ ' ' ' ~ '
-5.8 5.8 18.8 15.8 28.8 The equipotential contours plotted in Fig. 5 clearly indi-
"GbS (" cate that the distribution is more two-dimensional when
Fig. 4. Measured threshold-voltage reduction A V,, ( V,,, V8,) for an L the back surface is depleted ( VGbs= 0 V ) that when it is
= 1 .O pm p-channel MOSFET fabricated on a SO1 film with tb = 0.27
pn, t,,/ = 25 nm, to, = 450 nm, and No = 2 x 10'' C I I - ~ .
accumulated ( V G b , = 10 V ) . This dependence on the
back-surface charge condition is explained qualitatively
by noting that the V,,-induced displacement in the de-
due to increased charge-sharing.) Other measurements re- pleted film (with fixed charge) must terminate on excess
veal that the back-gate bias at which the maximum in A VTf surface charge. Thus the presence of an accumulation
occurs depends on L , as implied by (2) and (3). layer at the back surface tends to limit the modulation of
With regard to the scaled-device design for minimum the (front) channel charge.
A V v , we remark that operating the MOSFET with the It is possible to derive an expression for the channel
back surface close to inversion is normally undesirable current in terms of the induced channel charges at the
due to problems with leakage. Thus, the only viable de- boundaries of the channel [ l ] . In particular, in the satu-
sign options for SO1 MOSFET's are to scale t h with L , ration region of operation for V G f , 2: Vv(eff), the p-chan-
setting VGbsto accumulate the back surface, and/or to thin ne1 current can be written approximately as
the back-gate oxide, all of which tend to increase
and reduce the charge sharing. Of course, other design
considerations, some of which are discussed herein, could
imply necessary trade-offs as the device is scaled.
where W is the device width and a = Cb/Cr!for
B. Drain-Induced Conductivity Enhancement (DICE) CbC&/( cb + c,,) CO,, depending on whether the back
surface is accumulated or depleted [I], [ 5 ] . For VcfS =
When a large (negative) drain voltage V,, is applied to
a short p-channel MOSFET, the channel charge is mod- Vv(eff), the effective mobility peffis virtually independent
of VGfs, and the channel-length modulation that deter-
ulated indirectly through the two-dimensional Poisson
mines the effective channel length L, is controlled pri-
equation in the film, as well as directly through the in-
marily by VDs[l]. Thus, it is possible to estimate VTf(eff)
duced gradient in the surface potential \ksf along the chan-
nel (the gradual channel approximation [8] accounts for from a plot of 6, versus VGfsin the saturation region
the latter effect). In this section, we show how the former near threshold.
modulation, i.e., DICE, is affected by the back-surface Measured V T f ( e f f , ( characteristics
L) of the l b = 0.8 pm
charge condition in the thin-film SO1 MOSFET. device in Fig. 2, for different VGb, and VDs,are plotted in

In [ 11, we have derived an approximate expression for Fig. 6. These data confirm our conclusion derived above
the channel charge in terms of L and the applied biases. that the DICE effect is minimized when the back surface
In particular, this analysis expresses the charge at the is accumulated. The effect of varying t b is shown by the
source end of the channel as measured data plotted in Fig. 7. Consistent with
(4), these data reveal that the DICE effect is reduced as t h
decreases.
With regard to scaled device design for minimizing the
DICE then, the same criteria mentioned for minimizing
A A VTfapply. In this case, thinning the back-gate oxide is
- -e, ( V G f S - VTf(effJ (4)
effective in limiting the DICE effect because it enables the
where p = 1 or 1 + cb/(cb + Cob), depending on back gate (substrate) to accommodate some of the VDs-
whether the back surface is accumulated or depleted, C,, induced displacement.
= E,,/tob is the back-oxide capacitance, cb = ~ , / t ,is
defined as the body capacitance, and Vv(eff) is defined, C . Velocity Saturation and Channel-Length Modulation
mathematically, as an "effective" threshold voltage. For In the saturation region of operation of a MOSFET, the
a given device and drain bias, the difference between VTf drain current IDS( sat) and the incremental drain conduc-

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VEEKARAGHAVAN A N D FOSSIJM SHORT-CHANNEL. EFFECTS I N SO1 MOSFET'S 525

s,o*

-1.1 L 1
2 4 6 8 10

I IUlll!

Fig. 7 . Effective threshold voltage V , , , , , , ( L ) for the p-channel devices of

Fig. 2, measured at VDs = -2 V ( + ) and - 5 V ( x ) for ri, = 0 . 8 pm
(solid lines) and 1.3 p m (dotted lines) with VGhS = 20 V and Vss = 2
V.

is usually undesirable, as well as in a decrease in gDs(sat),

which is usually desirable. Thus, in conjunction with the
previous discussions, design trade-offs are implied.
For a long-channel thin-film SO1 MOSFET [ 5 ] ,
c< 1/( 1 +
a ) as indicated in (9,and is accordingly de-
creased as the back-surface charge condition is changed
(b) from depletion to accumulation. This decrease in
Fig. 5 . PISCES-simulated equipotential ('k) contours in increments of 0 . 2 occurs because the transverse electric field in the film in-
V for the SO1 MOSFET of Fig. 3 with (a) the hack surface accumulated
( V,i,,s = 10 V ) , and (b) the back surface depleted (V,,, = 0 V ) . Only
creases and, via Gauss's Law, causes a decrease in the
the contours for Vi,<- 2 V < 'k < Vi,, +
1 are shown. In both cases. channel charge for fixed ( VGfs-Vrf)and results in pre-
VrIS= - 2 V , V,,, = -2.5 V , and the (minority-) electron quasi-Fermi mature velocity saturation. (The decrease in is en- '

potential is set at 0 V.
hanced by the degradation of pef,caused by the increasing
field.) As discussed above, this effect is exacerbated as
-0 4 the channel length is decreased. This is clearly seen in
Fig. 8, where we plot the normalized quantity ZDS,5at,L
XSS versus L derived from measurements on a t/, = 0.8 pm
device with ( VGfs-Vv) and VDsfixed for the cases of back-
surface accumulation ( VGhs= 20 V ) and depletion ( VGhS
= 0 V ) . Additional measurements show the increase in
L with increasing t!,, implied above.
In addition to the variation of with L , the drain
conductance gDs(,at) associated with the channel-length
modulation is of interest. In Fig. 9 we plot the measured
-1.0 I I normalized conductance gDs(5at,L versus L for the SO1
z 4 6 8 10
MOSFET of Fig. 8, and for a thicker device. We note
1. l~lrll! from the plots that back-surface depletion results in an
Fig. 6 . Elfective threshold voltage V , , , , , , , ( L ) for the rh = 0 . 8 pm MOS- increase in gDs(s\;lt) due to increased channel-length mod-
FET of Fig. 2. measured at Vr,< = -2 V i + ) and - 5 V ( X ) for Vci,s ulation. This result is qualitatively explained below, based
ranging from 3 V (back-surface accumulation) to - 3 V (back-surface
depletion); V H 5 = 2 V for all the measurements. on the model developed in [ 11.
For the SO1 MOSFET, Gauss's law applied to the (thin)
high-field region near the drain (where the carrier velocity
tance gD.y(,dt)
depend on the manner in which the carrier is saturated) yields a solution for the potential in that re-
velocity in the channel saturates. This velocity saturation gion [9], [lo], [ l ] . This solution can be used to express
and the channel-length modulation it produces are impor- the channel-length modulation A L in terms of the termi-
tant in short-channel devices because the channel charge nal voltages, including VGhs[l]:
that remains near the drain in the saturation region is pro-
portional to which varies inversely with L. For
SO1 MOSFET's, there are additional dependences on the
back-surface charge condition and on r,,. In this section,
we demonstrate that accumulating the back surface and/ wherel, { (3th/(1 + a)]'/*isacharacteristiclength[ll]
or thinning the film result in a reduction of which which depends on the film thickness as well as the charge

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526 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 36, NO. 3. MARCH 1989

0 x 10-

3 -10

-60 (,,( A!,

,,.._.__.......
5000 ’ 5 10 15 20 25
I

I. (Lllll)
Fig. 10. PISCES-simulated I D S ( Vas) curves for the th = 0.27 pm (solid
Fig. 8. Measured drain-saturation current I D . y , , a t j ( L )normalized
, by I / L , lines) p-channel SO1 MOSFET of Figs. 3 and 5 at VChs = 10 V (back-
for the t,, = 0.8 pm p-channel SO1 MOSFET’s of Fig. 2 with ( VGrs- surface accumulation) and VChs = 0 V (back-surface depletion) com-
V n ) = -4 V and VDS= -5 V for back-surface accumulation with V,,, pared with simulations of a similar MOSFET with th = 0.135 pm (dotted
= 20 V (0) and back-surface depletion with VGhs = 0 V (A);Vss = 2 lines) at the same bias conditions. All simulations were done with ( VG,s-
V. Vr,) = - 5 V and the (minority-) electron quasi-Fermi potential set at
0 v.
300 , 4
I
e on hot-carrier generation in SO1 MOSFET’s. Through ac-
b
P
celerated stress tests, Colinge [12] has shown that the life-
time of the MOSFET can be improved by depleting the
back surface or by allowing the body to float with the back
surface in accumulation. For a given VGfs,both these con-
ditions result in a lowered ,,/I and hence increased
VDS(sat),and therefore a lowered electric field in the drain
region. From our discussion in the previous paragraphs,
the reason for increased channel-length modulation in
01 I thicker films or when the back is depleted is similar: a
0 5 10 15 20 25

1. (~1111)
decrease in the longitudinal electric field at the drain,
Fig. 9. Incremental conductance gDsl,,,,(L), normalized by 1 / L , derived which we have modeled in terms of I,. Thus, a large I,
from I,,,,,,, measurements for the bias conditions of Fig. 8 ( VGhS= 20 correlates with reduced hot-carrier generation. It there-
V (0) and 0 V ( A ) ) for t h = 0.8 pm (solid lines) and 1.3 pm (dotted fore appears that the use of ultra-thin SO1 films and back-
lines).
surface accumulation to improve short-channel behavior
would also result in increased device-degradation prob-
condition of the back surface (via /3 and a,which we in- lems. However, further experimental studies are neces-
troduced previously ) [ 11. This dependence reflects the sary to conclusively prove this deduction.
two-dimensional effect of the back-surface accumulation
layer in limiting the potential variation in the film, and in 111. BACK-SURFACE CHARGEMODULATION
confining all variations in potential to a region very close In the previous section, we implicitly assumed that the
to the front surface of the MOSFET. A decrease in 1, has back-surface charge condition depends only on the ap-
been related to an increase in the maximum longitudinal plied biases V,, and VGbs.However, we show in this sec-
electric field in the drain region (E,,, = (V,, - tion that in general the back-surface charge condition is
/ l , ) , and a simultaneous reduction in the channel- also dependent on L.
length modulation [lo], [ l l ] . Thus, we note that back- It is possible, with fixed VEs and I/GbS, for a back-sur-
surface accumulation (lower /3, higher a ) and/or reduc- face accumulation layer present in a long-channel SO1
tion in tb must result in reduced channel-length modula- MOSFET to be partially or completely depleted away by
tion, consistent with the measurements presented above. a sufficient reduction in L. This depletion-charge-sharing
To further clarify these effects on gDs(sat), PISCES-sim- effect, which occurs exclusively in SO1 MOSFET’s, is
ulated IDS( V,,) for the L = 1.0 pm device of Figs. 3 and reflected by comparisons in Fig. 11 of the measured lin-
5 ( t b = 0.27 pm) at VGb, = 0 V and VGbs = 10 V are ear-region ,,Z ( VGfs, VBs)characteristics for a long and
compared in Fig. 10 with simulations of a similar device short device with VGb, fixed to accumulate the back sur-
with tb = 0.135 pm. In order to cancel out the effect of face of the long-L device. For the long-channel device,
variable V,,, all the simulations were done with ( VGfs- the characteristics are seen to show a strong dependence
V T f )constant. From the plots it is evident that reduction on VBsand, correspondingly, a weak dependence on VGbs
in t h as well as back-surface accumulation tend to reduce (not shown), as expected for back-surface accumulation
the channel-length modulation as well as [ 5 ] . These dependences are reversed for the short-channel
We now relate the above discussion to previous studies device, as expected for back-surface depletion.

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 527

-
VFERARAGHAVAN AND FOSSUM. SHORT-CHANNEL EFFECTS I N SO1 MOSFkT‘S

Measured huurad
-80.0 I I I I
vi? = o v

P
Y

VGf IVolts 1 M c Volt. 1

(a) (a)

huurad

/
- ‘ . O ~ -
L

VB = ov

- a0 -1.0 O -2.8 -3.8. -4.0 z

-5.0 ~
E -1.E -2.8 -3.6
VGf IVolts 1 VD c Volts 1
(b) (b)
Fig. 1 1 . Measured linear-region I,( Vcj,. V B ) characteristics of (a) a long Fig. 12. Measured I,>( VI>,V H )characteristics of (a) the long, and ( b ) the
( L = 5 wm). and (b) a short ( L = 0.8 p n ) p-channel SO1 MOSFET ( t i , short SO1 MOSFET‘s of Fig. 1 I with VGbS= I O V set to accumulate the
= 0.27 wm. I,,, = 25 nni. I,,/, = 450 nm, and N , = 2 x 10lh cni-’) back surface of the long-channel device; V,, = -3 V . In (b), note the
with = 10 V set to accumulate the back surface o f the long-channel disappearance of the effect of V B as either V B or VI>is increased.
device.

(for long L ) to operate as a (semi-) bulk MOSFET [ 131

Similarly, any accumulation layer present at the back to behave as a thin-film device when L is scaled-down
surface, for a given device, can be partially or completely sufficiently. With regard to the SO1 circuit simulation, we
depleted away by a nonzero VDs.This effect has been rec- mention that most compact device models assume that the
ognized previously, even for long MOSFET’s [ 5 ] ,but in MOSFET operates with a spatially uniform back-surface
fact is exacerbated as L is reduced due to the two-dimen- charge condition. (Although it is possible to develop a
sional potential distribution. The overall effect on the general physical model that accounts for the back-surface
drain current can be quite dramatic, as is evident from a charge modulation [ 141, the present technology is in flux
comparison of Fig. 12(a) and (b), where we plot mea- and does not seem to warrant the added complexity.) We
sured Ins( VDs, V B s )characteristics for a long ( L = 5 p m ) thus note that the length dependence of the back-surface
and a short ( L = 0.8 p m ) SO1 MOSFET for fixed Vcfs charge condition must be incorporated into any model se-
and V,,,. In the long device, the presence of an accu- lection or parameter-extraction algorithm. For example,
mulation layer at the back surface allows the applied V,, the model selection criteria in [13], which were defined
to modulate Vrf, and therefore InS. In the short-channel for long L , should be generalized, based on ( 5 ) , to include
device, the back-surface accumulation layer is modulated the channel-length dependence.
away at large V,, and/or large VDs,and so IDS is much
less dependent on VBs. Iv. S U M M A R Y / C O N C L U S I O N S
These back-surface charge modulations in short-chan- We have shown that the presence of the additional
ne1 SO1 MOSFET’s can further cause a device designed (back) gate in SO1 MOSFET’s can significantly affect the

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~

528 IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 36. NO. 3. MARCH 1989

behavior of short-channel devices. Through measure- [ I I] C. Hu. S . Tam, F. C. Hsu, P. K. KO, T. Y. Chan, and K . W . Terrill,
“Hot-electron-induced MOSFET degradation-model, monitor, and
ments and simulations, we have shown that short-channel improvement,” IEEE Trans. Electron Devices, vol. ED-32, pp. 375-
effects like threshold-voltage reduction, drain-induced 385, Feb. 1985.
conductivity enhancement, and channel-length modula- [ 121 J.-P. Colinge, “Hot-electron effects in silicon-on-insulator n-channel
MOSFET’s” IEEE Trans. Electron Devices, vol. ED-34, pp. 2173-
tion can be controlled by thinning the SO1 film and/or by 2177, Oct. 1987.
accumulating the back surface with an applied back-gate [I31 J. G . Fossum, S . Veeraraghavan, and D. FitzPatrick, “Model selec-
bias. Design trade-offs, however, involve reduced drain tion for SO1 MOSFET circuit simulation,” IEEE Trans. Computer-
Aided Design, vol. CAD-7, pp. 541-544, Apr. 1988.
current related to charge coupling and carrier velocity sat- [ 141 S . Veeraraghavan, “Modeling small-geometry silicon-on-insulator
uration as well as reduced carrier mobility, and possibly transistors for device and circuit computer-aided design,” Ph.D. dis-
increased hot-carrier effects. In SO1 CMOS applications, sertation, Univ. of Florida, Gainesville, 1988.
these trade-offs are complicated by the constraint that both
h
the n- and p-channel devices share a common back gate
(substrate). Optimal designs would require a physical
Surya Veeraraghavan (S’84) received the
model like that in [l]. We have also reported a short- B.Tech. degree in electrical engineering from the
channel effect exclusive to SO1 MOSFET’s whereby a re- Indian Institute of Technology, Bombay, in 1983
duction in the channel length can deplete the entire film, and the M.E. and Ph.D. degrees from the Uni-
versity of Florida, Gainesville, in 1985 and 1988,
negating the control of device properties by the (film) body respectively
voltage. He worked as a summer trainee at the Bhabba
Atomic Research Center, Bombay, in 1982, and
ACKNOWLEDGMENT at the VLSI Design Laboratory, Texas Instru-
ments, Dallas, in 1984 where he was part of the
We wish to acknowledge W. Krull and R. Sundaresan DRAM design group. He was a Graduate Assis-
for providing us with test devices. We are also grateful to tant and Instructor in the Department of Electrical Engineering at the Uni-
versity of Florida from 1983 to 1988. He is currently a staff member in the
the Hewlett-Packard Corporation for its donation of the Advanced Products R&D Laboratory at Motorola, Inc., Austin, TX. His
TECAP measurement software. major research interests include large-signal transient modeling of semi-
conductor devices for use in circuit simulation.
REFERENCES
[ I ] S . Veeraraghavan and J. G. Fossum, “A physical short-channel model
*
for the thin-film SO1 MOSFET applicable to device and circuit CAD,”
IEEE Trans. Elecrron Devices, vol. ED-35, pp. 1866-1875, Nov. Jerry G. Fossum (S’69-M’72-SM’79-F’83) was
1988. born in Phoenix, AZ, in 1943. He received the
[2] L. A. Akers and J. J . Sanchez, “Threshold voltage models of short, B . S . , M.S., and Ph.D. degrees in electrical en-
narrow and small geometry MOSFET’s: A review,” Solid-Stare Elec- gineering from the University of Arizona, Tuc-
tron., vol. 25, no. 7 , pp. 621-641, 1982. son, in 1966, 1969, and 1971, respectively. His
[3] T . Sekigawa and Y . Hayashi, “Calculated threshold-voltage charac- doctoral research was in the area of semiconduc-
teristics of an XMOS transistor having an additional bottom gate,” tor device and integrated circuit modeling.
Solid-State Electron., vol. 27, pp. 827-828, 1984. During his graduate program, he was a NASA
141 J.-P. Colinge and T . I . Kamins, “CMOS circuits made in thin SI- Predoctoral Trainee, a Graduate Teaching and Re-
MOX films,’’ Electron. Lett., vol. 23, pp. 1162-1 164, Oct. 1987. search Associate, and an Industrial Consultant. In
[ 5 ] H. K. Lim and J. G . Fossum, “Current-voltage characteristics of thin- 1971. he ioined the technical staff of Sandia Lab-
film SO1 MOSFET’s in strong inversion,” IEEE Trans. Electron De- oratories, Albuquerque, NM, where he was engaged in various semicon-
vices, vol. ED-31, pp. 401-408, Apr. 1984. ductor device analysis and modeling activities, including the development
[6] R. H . Dennard, F. H. Gaensslen. H. Yu, V. L. Rideout, E. Bassons, of silicon solar cells. In 1978, he became Associate Professor of Electrical
and A. R. LeBlanc, “Design of ion-implanted MOSFET’s with very Engineering at the University of Florida, Gainesville, and in 1980 was
small physical dimensions,” IEEE J . Solid-Stare Circuirs, vol. SC- promoted to Professor of Electrical Engineering. His general area of inter-
9, pp. 256-267, Oct. 1974. est is semiconductor device theory and technology; his current research
171 M. R . Pinto, C . S . Rafferty. and R. W. Dutton, PISCES-II: Poisson involves device modeling for TCAD. with emphasis on bipolar transistors,
and Conrinuity Equation Solver, Stanford Electronics Lab., Stanford high-voltage power switches, and thin-film SO1 MOSFET’s.
Univ., Stanford, CA, 1984. Dr. Fossum is an Associate Editor for the IEEE TRANSACTIONS ON COM-
[8] S . M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: PUTER-AIDEDDESIGNOF ICAS and a member of the Honorary Editorial
Wiley, 1981. Advisory Board of Solid-State Electronics. He has several times served on
[9] Y. A. El-Mansy and D . M. Caughey, “Modeling weak avalanche the Program Committee of the IEEE International Electron Devices Meet-
multiplication currents in IGFET’s and SOS transistors for CAD,” in ing; in 1979 he was Chairman of the Subcommittee on Quantum Electron-
IEDM Tech. Dig., 1975. ics and Energy Conversion Devices. In 1983, he was elected a Fellow of
[IO] Y. A. El-Mansy and A. R. Boothroyd, “A simple two-dimensional the IEEE for “contributions to the theory and technology of silicon solar
model for IGFET operation in the saturation region,” IEEE Trans. cells and transistors.” He is listed in Who’s Who in America, 1984, 1986,
Electron Devices, vol. ED-24, pp. 254-262, Mar. 1977. and 1988, and in Who’s Who in Frontiers of Science and Technology, 1986.

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