5 4 3 2 1

D D

LCFC NM-D701
C
HS533 M/B Schematics Document C

AMD FP6 Renoir with DDR4

REV:0.1
2020-10-13

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/02/27 Deciphered Date 2020/02/27 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15
Date: Tuesday, November 03, 2020 Sheet 1 of 45
5 4 3 2 1
 5 4 3 2 1

DP0
Channel A
LCD 15" HD/FHD
AMD FP6 Renoir DDR4
Combo Jack
DDR4
Touch Screen Memory Down
Channel B Antenna
D 16
I2C2 BGA 1140 DDR4
D
14,15

Redriver (M.2 WLAN Card)

HDMI 1.4b PS8203T DP1
Bluetooth 26

USB Type-C Conn DP AUX MUX M.2 Card

DP2AUX
Normal type C PI3USB102ZMEX
24 22

USBC0
USB2.0 GPP
X1
PD Controller I2C3
RTS5457-GR GPP X4
22
GPP[0:4] M.2 SSD 21
USB Small Board
USB 3.0 Gen 1 USB 3.0 repeater USB3 Port 1
AOU PS8719

SATA
SATA HDD
C C
USB Small Board
USB 3.0 Gen 1 USB 3.0 repeater USB3 Port 2
PS8719

Card Reader USB2.0 port5

IO Board RTS5146
USB2.0 X7 HDA

USB Type-C Conn USB2.0 port0

Normal type C
SPI Flash HDA CODEC
USB 3.1 Gen 1 USB3.0 port1 16M
AOU (USB1) USB2.0 port1 8 ALC3287 33

USB3.0 port4
USB 3.1 Gen 1 USB2.0 port4 Stereo
Speaker
33
USB2.0 port2
Camera/IR Camera
Internal
FAN TPM Mic
USB2.0 25
USB2.0 port6 28 Microphone 33
M.2 WLAN Slot(BT)
Headphone
LPC
33
Finger print USB2.0 port7

B B

battery SMBUS
Audio 50
39
SMBUS EC IT8227

Charger 30
40

Thermal
Sensor External Connector/Socket
25
Keyboard Power Button
Hall Sensor Internal Connector/Socket
25 31 27
Internal Switch

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/02/27 Deciphered Date 2020/02/27 BLOCK DIAGRAM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 2 of 45
5 4 3 2 1
 A B C D E

SIGNAL
Voltage Rails ( O --> Means ON , X --> Means OFF ) I2C Control Table STATE SLP_S3# SLP_S5# +VALW +V +VS Clock

+5VS S0 (Full ON) HIGH HIGH ON ON ON ON

SOURCE Device
+3VS
S1 (Power On Suspend) HIGH HIGH ON ON ON LOW
+1.8VS
power +0.75VS TP_I2C2_SCL APU Touch Screen S3 (Suspend to RAM) LOW HIGH ON ON OFF OFF
plane B+
1 (+20VSB) +5VALW +0.6VS TP_I2C2_SDA +3VS +3VS 1
+2.5V S4 (Suspend to Disk) LOW LOW ON OFF OFF OFF
+3VL +3VALW
+1.2V
+5VLP
(+3VALW_APU)
+VDDC_VDD APU I2C address S5 (Soft OFF) LOW LOW ON OFF OFF OFF
+1.8VALW
+VDDCR_SOC Device Address
+0.75VALW
?
BOM Structure Table
?
State BOM Structure BTO Item
Port List @ Not stuff
SOURCE Device
ME@ Connector
HSIO Port Device EMC Part
EMC@
TP_I2C3_SCL APU Touch Pad
0 EMC_NS@ EMC reserve Part
TP_I2C3_SDA +3VALW +3VS
1 RF@ RF Part
2 TPM@ TPM part
S0 O O O O GFX 3
APU I2C address N/A HDT@ HDT Debug part
Device Address
4 REDRV@ Redriver part
S3 5
O O O X Elan：SA469D-22HA 69x104x1.0 ? LPC@
2
Synaptics：TM-P3255-008 69x104x1.0 ?
6 TS@
2

S5 S4/AC
7 NON_TS@
O O X X 0
SOURCE Device FP@
1 NON_FP@
S5 S4/ Battery only SSD
O X X X 2
USBC_I2C_SCL APU PD Controller 3
S5 S4/AC & Battery
USBC_I2C_SDA +1.8VALW +5VALW 4 WLAN
don't exist X X X X 5
APU I2C address GPP
6 N/A
Device Address 7
? 8 HDD
SMBUS Control Table
9
SOURCE PD BATT IT8227 EXPAND WLAN Thermal APU Charger PMIC
10 N/A
Sensor 11
0 Type C
3 3
EC_SMB_CK0
IT8227 USB3.0
1 USB 3.0 ( AOU)
EC_SMB_DA0 +3VL X X X X V V X X 4 USB 3.0 ( Normal)
+3VS +3VS
5 N/A
EC_SMB_CK1
IT8227
0 Type C
EC_SMB_DA1 +3VL X V X X X X V X 1 USB 3.0 ( AOU)
+3VL +3VL
2 Camera
EC_SMB_CK2
IT8227
3 Touch Screen
EC_SMB_DA2 +3VS V X X X X X X X 4 USB 3.0 ( Normal)
+3VL USB2.0
5 Cardreader
EC_SMB_CK3 IT8227
6 BT
+3VL X X X X X X X V 7 Finger Print
EC_SMB_DA3 +3VL

EC SM Bus0 address EC SM Bus1 address EC SM Bus2 address

Device Address Device Address Device Address
4 4
PD Charger 0b00010010 APU SB-TSI releate to F3x1E4[SbiAddr] or
Address Select Pins setting
PMIC 0X34 Battery ?
Thermal Sensor 10011011b(read) 10011010b(write)
Title
EC SM Bus3 address Security Classification LC Future Center Secret Data

Device Address
Issued Date 2013/08/15 Deciphered Date 2013/08/15 Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Expand IT8013 0100,A2,A1,A0 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 3 of 45
A B C D E
 5 4 3 2 1

D D

UC1A

G13 F4
F13 P_GFX_RXP0 P_GFX_TXP0 F2
P_GFX_RXN0 P_GFX_TXN0
J14 F3
H14 P_GFX_RXP1 P_GFX_TXP1 E4
P_GFX_RXN1 P_GFX_TXN1
G15 E1
F15 P_GFX_RXP2 P_GFX_TXP2 C1
P_GFX_RXN2 P_GFX_TXN2
J15 D5
K15 P_GFX_RXP3 P_GFX_TXP3 E6
P_GFX_RXN3 P_GFX_TXN3
H16 C6
J16 P_GFX_RXP4 P_GFX_TXP4 D6
P_GFX_RXN4 P_GFX_TXN4
F18 B6
G18 P_GFX_RXP5 P_GFX_TXP5 C7
P_GFX_RXN5 P_GFX_TXN5
J18 D8
K18 P_GFX_RXP6 P_GFX_TXP6 B8
C
P_GFX_RXN6 P_GFX_TXN6 C
H19 C8
G19 P_GFX_RXP7 P_GFX_TXP7 A8
P_GFX_RXN7 P_GFX_TXN7

PCIE_PRX_DTX_P0 G11 L3 PCIE_PTX_DRX_P0 0.22U_6.3V_K_X5R_0201

1 2 CC9 PCIE_PTX_C_DRX_P0
[21] PCIE_PRX_DTX_P0 PCIE_PRX_DTX_N0 F11 P_GPP_RXP0 P_GPP_TXP0 L1 PCIE_PTX_DRX_N0 0.22U_6.3V_K_X5R_0201
1 2 PCIE_PTX_C_DRX_N0 PCIE_PTX_C_DRX_P0 [21]
CC10
[21] PCIE_PRX_DTX_N0 P_GPP_RXN0 P_GPP_TXN0 PCIE_PTX_C_DRX_N0 [21]
PCIE_PRX_DTX_P1 J10 L4 PCIE_PTX_DRX_P1 0.22U_6.3V_K_X5R_0201
1 2 CC11 PCIE_PTX_C_DRX_P1
[21] PCIE_PRX_DTX_P1 PCIE_PRX_DTX_N1 H10 P_GPP_RXP1 P_GPP_TXP1 L2 PCIE_PTX_DRX_N1 0.22U_6.3V_K_X5R_0201
1 2 PCIE_PTX_C_DRX_N1 PCIE_PTX_C_DRX_P1 [21]
CC12
M.2 SSD1 [21] PCIE_PRX_DTX_N1 P_GPP_RXN1 P_GPP_TXN1 PCIE_PTX_C_DRX_N1 [21]
PCIE_PRX_DTX_P2 PCIE_PTX_DRX_P2 0.22U_6.3V_K_X5R_0201 PCIE_PTX_C_DRX_P2
M.2 SSD1
G8 M4 1 2 CC13
[21] PCIE_PRX_DTX_P2 PCIE_PRX_DTX_N2 F8 P_GPP_RXP2/SATA0_RXP P_GPP_TXP2/SATA0_TXP M2 PCIE_PTX_DRX_N2 0.22U_6.3V_K_X5R_0201
1 2 PCIE_PTX_C_DRX_N2 PCIE_PTX_C_DRX_P2 [21]
CC14
[21] PCIE_PRX_DTX_N2 P_GPP_RXN2/SATA0_RXN P_GPP_TXN2/SATA0_TXN PCIE_PTX_C_DRX_N2 [21]
PCIE_PRX_DTX_P3 G6 N3 PCIE_PTX_DRX_P3 0.22U_6.3V_K_X5R_0201
1 2 CC15 PCIE_PTX_C_DRX_P3
[21] PCIE_PRX_DTX_P3 PCIE_PRX_DTX_N3 F7 P_GPP_RXP3/SATA1_RXP P_GPP_TXP3/SATA1_TXP N1 PCIE_PTX_DRX_N3 0.22U_6.3V_K_X5R_0201
1 2 PCIE_PTX_C_DRX_N3 PCIE_PTX_C_DRX_P3 [21]
CC16
[21] PCIE_PRX_DTX_N3 P_GPP_RXN3/SATA1_RXN P_GPP_TXN3/SATA1_TXN PCIE_PTX_C_DRX_N3 [21]

PCIE_PRX_DTX_P4 M9 T2 PCIE_PTX_DRX_P4 0.1U_6.3V_K_X5R_0201

1 2 CC17 PCIE_PTX_C_DRX_P4
WLAN [26] PCIE_PRX_DTX_P4 PCIE_PRX_DTX_N4 P_GPP_RXP4 P_GPP_TXP4 PCIE_PTX_DRX_N4 0.1U_6.3V_K_X5R_0201 PCIE_PTX_C_DRX_N4 PCIE_PTX_C_DRX_P4 [26] WLAN
M8 T4 1 2 CC18
[26] PCIE_PRX_DTX_N4 P_GPP_RXN4 P_GPP_TXN4 PCIE_PTX_C_DRX_N4 [26]
L7 R1
L6 P_GPP_RXP5 P_GPP_TXP5 R3
P_GPP_RXN5 P_GPP_TXN5
K7 P2
K8 P_GPP_RXP6 P_GPP_TXP6 P4
P_GPP_RXN6 P_GPP_TXN6
H6 N2
H7 P_GPP_RXP7 P_GPP_TXP7 N4
P_GPP_RXN7 P_GPP_TXN7

SATA_PRX_DTX_P0 L9 K2 SATA_PTX_DRX_P0
[29] SATA_PRX_DTX_P0 SATA_PRX_DTX_N0 L10 P_GPP_RXP8/SATA2_RXP P_GPP_TXP8/SATA2_TXP K4 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 [29]
HDD [29] SATA_PRX_DTX_N0 P_GPP_RXN8/SATA2_RXN P_GPP_TXN8/SATA2_TXN SATA_PTX_DRX_N0 [29] HDD
K11 J4
B
J11 P_GPP_RXP9/SATA3_RXP P_GPP_TXP9/SATA3_TXP J2 B
P_GPP_RXN9/SATA3_RXN P_GPP_TXN9/SATA3_TXN
J12 H3
H12 P_GPP_RXP10 P_GPP_TXP10 H1
P_GPP_RXN10 P_GPP_TXN10
J13 H4
K13 P_GPP_RXP11 P_GPP_TXP11 H2
P_GPP_RXN11 P_GPP_TXN11
FP6 REV0.92
PART 2/13

AMD-RENOIR-FP6_BGA1140
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP5 (PCIE SATA I/F)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 4 of 45
5 4 3 2 1
 5 4 3 2 1

DDRA_MA_DM[0..7] [14]
DDRA_MB_DM[0..7] [15]
DDR_A_DQS#[0..7] [14]
UC1B
DDR_B_DQS#[0..7] [15]
UC1C
DDR_A_DQS[0..7] [14]
DDR_A_MA0 DDR_B_DQS[0..7] [15]
AK26
DDR_A_MA1 MA_ADD0/RSVD DDR_A_D0 DDR_A_D[0..63] [14] DDR_B_MA0
AG24 K27 AM29
DDR_A_MA2 MA_ADD1/RSVD MA_DATA0/MAA_DATA8 DDR_A_D1 DDR_B_MA1 MB_ADD0/RSVD DDR_B_D0 DDR_B_D[0..63] [15]
AG23 L26 AH31 C27
DDR_A_MA3 MA_ADD2/MAB_CA0 MA_DATA1/MAA_DATA9 DDR_A_D2 DDR_A_MA[0..13] [14] DDR_B_MA2 MB_ADD1/RSVD MB_DATA0/MBA_DATA8 DDR_B_D1
AG26 N26 AJ30 A28
DDR_A_MA4 MA_ADD3/MAA_CA4 MA_DATA2/MAA_DATA13 DDR_A_D3 DDR_B_MA3 MB_ADD2/MBB_CA0 MB_DATA1/MBA_DATA9 DDR_B_D2 DDR_B_MA[0..13] [15]
AG27 N27 AH29 F29
DDR_A_MA5 AF21 MA_ADD4/MAA_CA5 MA_DATA3/MAA_DATA12 G27 DDR_A_D4 DDR_B_MA4 AG32 MB_ADD3/MBA_CA4 MB_DATA2/MBA_DATA13 F31 DDR_B_D3
DDR_A_MA6 AF22 MA_ADD5/MAA_CA3 MA_DATA4/MAA_DATA11 H27 DDR_A_D5 DDR_B_MA5 AG30 MB_ADD4/MBA_CA5 MB_DATA3/MBA_DATA12 B27 DDR_B_D4
DDR_A_MA7 AF25 MA_ADD6/MAA_CA2 MA_DATA5/MAA_DATA10 M27 DDR_A_D6 DDR_B_MA6 AG31 MB_ADD5/MBA_CA3 MB_DATA4/MBA_DATA11 D27 DDR_B_D5
DDR_A_MA8 AF24 MA_ADD7/RSVD MA_DATA6/MAA_DATA15 N24 DDR_A_D7 DDR_B_MA7 AF30 MB_ADD6/MBA_CA2 MB_DATA5/MBA_DATA10 E32 DDR_B_D6
DDR_A_MA9 AE21 MA_ADD8/RSVD MA_DATA7/MAA_DATA14 DDR_B_MA8 AG29 MB_ADD7/RSVD MB_DATA6/MBA_DATA15 F30 DDR_B_D7
D D
DDR_A_MA10 AL21 MA_ADD9/RSVD L23 DDR_A_D8 DDR_B_MA9 AF29 MB_ADD8/RSVD MB_DATA7/MBA_DATA14
DDR_A_MA11 AF27 MA_ADD10/MAB_CS_L1 MA_DATA8/MAA_DATA0 N21 DDR_A_D9 DDR_B_MA10 AM30 MB_ADD9/RSVD H31 DDR_B_D8
DDR_A_MA12 AE23 MA_ADD11/MAA_CKE1 MA_DATA9/MAA_DATA1 T21 DDR_A_D10 DDR_B_MA11 AF31 MB_ADD10/MBB_CS_L1 MB_DATA8/MBA_DATA0 H30 DDR_B_D9
DDR_A_MA13 AM23 MA_ADD12/MAA_CKE0 MA_DATA10/MAA_DATA5 T22 DDR_A_D11 DDR_B_MA12 AE32 MB_ADD11/MBA_CKE1 MB_DATA9/MBA_DATA1 K31 DDR_B_D10
DDR_A_WE# AM21 MA_ADD13_BANK2/RSVD MA_DATA11/MAA_DATA4 M22 DDR_A_D12 DDR_B_MA13 AP30 MB_ADD12/MBA_CKE0 MB_DATA10/MBA_DATA5 L30 DDR_B_D11
[14] DDR_A_WE# DDR_A_CAS# MA_WE_L_ADD14/MAB_CKE1 MA_DATA12/MAA_DATA7 DDR_A_D13 DDR_B_WE# MB_ADD13_BANK2/RSVD MB_DATA11/MBA_DATA4 DDR_B_D12
AL27 L24 AP31 G30
[14] DDR_A_CAS# DDR_A_RAS# MA_CAS_L_ADD15/RSVD MA_DATA13/MAA_DATA6 DDR_A_D14 [15] DDR_B_WE# DDR_B_CAS# MB_WE_L_ADD14/MBB_CKE1 MB_DATA12/MBA_DATA7 DDR_B_D13
AL24 R21 AP29 H29
[14] DDR_A_RAS# MA_RAS_L_ADD16/MAB_CKE0 MA_DATA14/MAA_DATA2 DDR_A_D15 [15] DDR_B_CAS# DDR_B_RAS# MB_CAS_L_ADD15/RSVD MB_DATA13/MBA_DATA6 DDR_B_D14
R23 AN29 K30
MA_DATA15/MAA_DATA3 [15] DDR_B_RAS# MB_RAS_L_ADD16/MBB_CKE0 MB_DATA14/MBA_DATA2 DDR_B_D15
K29
DDR_A_BA0 AL22 P24 DDR_A_D16 MB_DATA15/MBA_DATA3
[14] DDR_A_BA0 DDR_A_BA1 MA_BANK0/MAB_CS_L0 MA_DATA16/MAA_DATA17 DDR_A_D17 DDR_B_BA0 DDR_B_D16
AK27 R26 AN31 N32
[14] DDR_A_BA1 MA_BANK1/MAB_CA1 MA_DATA17/MAA_DATA16 DDR_A_D18 [15] DDR_B_BA0 DDR_B_BA1 MB_BANK0/MBB_CS_L0 MB_DATA16/MBA_DATA21 DDR_B_D17
T27 AM32 N29
DDR_A_BG0 MA_DATA18/MAA_DATA21 DDR_A_D19 [15] DDR_B_BA1 MB_BANK1/MBB_CA1 MB_DATA17/MBA_DATA22 DDR_B_D18
AE27 V27 P30
[14] DDR_A_BG0 DDR_A_BG1 MA_BG0/MAA_CS_L1 MA_DATA19/MAA_DATA20 DDR_A_D20 DDR_B_BG0 MB_DATA18/MBA_DATA20 DDR_B_D19
AE26 P25 AD29 L32
[14] DDR_A_BG1 MA_BG1/MAA_CS_L0 MA_DATA20/MAA_DATA19 DDR_A_D21 [15] DDR_B_BG0 DDR_B_BG1 MB_BG0/MBA_CS_L1 MB_DATA19/MBA_DATA19 DDR_B_D20
P27 AD31 L31
DDR_A_ACT_N MA_DATA21/MAA_DATA18 DDR_A_D22 [15] DDR_B_BG1 MB_BG1/MBA_CS_L0 MB_DATA20/MBA_DATA17 DDR_B_D21
AD22 V23 M30
[14] DDR_A_ACT_N MA_ACT_L/RSVD MA_DATA22/MAA_DATA23 DDR_A_D23 DDR_B_ACT_N MB_DATA21/MBA_DATA16 DDR_B_D22
T25 AD30 L29
DDRA_MA_DM0 MA_DATA23/MAA_DATA22 [15] DDR_B_ACT_N MB_ACT_L/RSVD MB_DATA22/MBA_DATA18 DDR_B_D23
L27 N31
DDRA_MA_DM1 N23 MA_DM0/MAA_DM1 W22 DDR_A_D24 DDRA_MB_DM0 C30 MB_DATA23/MBA_DATA23
DDRA_MA_DM2 R27 MA_DM1/MAA_DM0 MA_DATA24/MAA_DATA30 Y23 DDR_A_D25 DDRA_MB_DM1 H32 MB_DM0/MBA_DM1 R30 DDR_B_D24
DDRA_MA_DM3 Y24 MA_DM2/MAA_DM2 MA_DATA25/MAA_DATA31 AC24 DDR_A_D26 DDRA_MB_DM2 M29 MB_DM1/MBA_DM0 MB_DATA24/MBA_DATA30 R32 DDR_B_D25
DDRA_MA_DM4 AP27 MA_DM3/MAA_DM3 MA_DATA26/MAA_DATA26 AC23 DDR_A_D27 DDRA_MB_DM3 T29 MB_DM2/MBA_DM2 MB_DATA25/MBA_DATA31 V30 DDR_B_D26
DDRA_MA_DM5 AW23 MA_DM4/MAB_DM2 MA_DATA27/MAA_DATA27 V21 DDR_A_D28 DDRA_MB_DM4 AU30 MB_DM3/MBA_DM3 MB_DATA26/MBA_DATA26 V32 DDR_B_D27
DDRA_MA_DM6 AT21 MA_DM5/MAB_DM3 MA_DATA28/MAA_DATA28 W21 DDR_A_D29 DDRA_MB_DM5 BD28 MB_DM4/MBB_DM2 MB_DATA27/MBA_DATA27 P29 DDR_B_D28
DDRA_MA_DM7 AV18 MA_DM6/MAB_DM1 MA_DATA29/MAA_DATA29 AA24 DDR_A_D30 DDRA_MB_DM6 BB23 MB_DM5/MBB_DM3 MB_DATA28/MBA_DATA28 P31 DDR_B_D29
W24 MA_DM7/MAB_DM0 MA_DATA30/MAA_DATA24 AA22 DDR_A_D31 DDRA_MB_DM7 BD20 MB_DM6/MBB_DM1 MB_DATA29/MBA_DATA29 U31 DDR_B_D30
MA_DM8/RSVD_52 MA_DATA31/MAA_DATA25 W31 MB_DM7/MBB_DM0 MB_DATA30/MBA_DATA25 U29 DDR_B_D31
DDR_A_DQS0 M25 AP26 DDR_A_D32 MB_DM8/RSVD_57 MB_DATA31/MBA_DATA24
DDR_A_DQS#0 M24 MA_DQS_H0/MAA_DQS_H1 MA_DATA32/MAB_DATA17 AN24 DDR_A_D33 DDR_B_DQS0 E29 AT29 DDR_B_D32
DDR_A_DQS1 P22 MA_DQS_L0/MAA_DQS_L1 MA_DATA33/MAB_DATA16 AR25 DDR_A_D34 DDR_B_DQS#0 D28 MB_DQS_H0/MBA_DQS_H1 MB_DATA32/MBB_DATA16 AU32 DDR_B_D33
DDR_A_DQS#1 P21 MA_DQS_H1/MAA_DQS_H0 MA_DATA34/MAB_DATA21 AU26 DDR_A_D35 DDR_B_DQS1 J31 MB_DQS_L0/MBA_DQS_L1 MB_DATA33/MBB_DATA17 AW31 DDR_B_D34
DDR_A_DQS2 T24 MA_DQS_L1/MAA_DQS_L0 MA_DATA35/MAB_DATA20 AN25 DDR_A_D36 DDR_B_DQS#1 J29 MB_DQS_H1/MBA_DQS_H0 MB_DATA34/MBB_DATA21 AW30 DDR_B_D35
DDR_A_DQS#2 R24 MA_DQS_H2/MAA_DQS_H2 MA_DATA36/MAB_DATA19 AN27 DDR_A_D37 DDR_B_DQS2 N30 MB_DQS_L1/MBA_DQS_L0 MB_DATA35/MBB_DATA20 AR30 DDR_B_D36
DDR_A_DQS3 AA21 MA_DQS_L2/MAA_DQS_L2 MA_DATA37/MAB_DATA18 AR27 DDR_A_D38 DDR_B_DQS#2 M31 MB_DQS_H2/MBA_DQS_H2 MB_DATA36/MBB_DATA19 AT31 DDR_B_D37
C DDR_A_DQS#3 Y21 MA_DQS_H3/MAA_DQS_H3 MA_DATA38/MAB_DATA23 AU27 DDR_A_D39 DDR_B_DQS3 T30 MB_DQS_L2/MBA_DQS_L2 MB_DATA37/MBB_DATA18 AV30 DDR_B_D38 C
DDR_A_DQS4 AP23 MA_DQS_L3/MAA_DQS_L3 MA_DATA39/MAB_DATA22 DDR_B_DQS#3 T31 MB_DQS_H3/MBA_DQS_H3 MB_DATA38/MBB_DATA23 AW29 DDR_B_D39
DDR_A_DQS#4 AP24 MA_DQS_H4/MAB_DQS_H2 AV25 DDR_A_D40 DDR_B_DQS4 AU29 MB_DQS_L3/MBA_DQS_L3 MB_DATA39/MBB_DATA22
DDR_A_DQS5 AW22 MA_DQS_L4/MAB_DQS_L2 MA_DATA40/MAB_DATA30 AW25 DDR_A_D41 DDR_B_DQS#4 AU31 MB_DQS_H4/MBB_DQS_H2 AY29 DDR_B_D40
DDR_A_DQS#5 AV22 MA_DQS_H5/MAB_DQS_H3 MA_DATA41/MAB_DATA31 AV20 DDR_A_D42 DDR_B_DQS5 BA27 MB_DQS_L4/MBB_DQS_L2 MB_DATA40/MBB_DATA29 AY32 DDR_B_D41
DDR_A_DQS6 AT20 MA_DQS_L5/MAB_DQS_L3 MA_DATA42/MAB_DATA26 AW20 DDR_A_D43 DDR_B_DQS#5 BB27 MB_DQS_H5/MBB_DQS_H3 MB_DATA41/MBB_DATA28 BC27 DDR_B_D42
DDR_A_DQS#6 AR20 MA_DQS_H6/MAB_DQS_H1 MA_DATA43/MAB_DATA27 AV27 DDR_A_D44 DDR_B_DQS6 BC23 MB_DQS_L5/MBB_DQS_L3 MB_DATA42/MBB_DATA24 BB26 DDR_B_D43
DDR_A_DQS7 AR18 MA_DQS_L6/MAB_DQS_L1 MA_DATA44/MAB_DATA28 AW26 DDR_A_D45 DDR_B_DQS#6 BA23 MB_DQS_H6/MBB_DQS_H1 MB_DATA43/MBB_DATA25 BC25 DDR_B_D44
DDR_A_DQS#7 AT18 MA_DQS_H7/MAB_DQS_H0 MA_DATA45/MAB_DATA29 AU21 DDR_A_D46 DDR_B_DQS7 BC20 MB_DQS_L6/MBB_DQS_L1 MB_DATA44/MBB_DATA27 BA25 DDR_B_D45
Y26 MA_DQS_L7/MAB_DQS_L0 MA_DATA46/MAB_DATA24 AW21 DDR_A_D47 DDR_B_DQS#7 BA20 MB_DQS_H7/MBB_DQS_H0 MB_DATA45/MBB_DATA26 BB30 DDR_B_D46
Y27 MA_DQS_H8/RSVD_58 MA_DATA47/MAB_DATA25 Y32 MB_DQS_L7/MBB_DQS_L0 MB_DATA46/MBB_DATA30 BA28 DDR_B_D47
MA_DQS_L8/RSVD_59 AT22 DDR_A_D48 Y30 MB_DQS_H8/RSVD_61 MB_DATA47/MBB_DATA31
SA_CLK_DDR0 AJ25 MA_DATA48/MAB_DATA11 AP21 DDR_A_D49 MB_DQS_L8/RSVD_60 BA24 DDR_B_D48
[14] SA_CLK_DDR0 SA_CLK_DDR#0 MA_CLK_H0/MAA_CKT MA_DATA49/MAB_DATA10 DDR_A_D50 SB_CLK_DDR0 MB_DATA48/MBB_DATA11 DDR_B_D49
AJ24 AN19 AJ31 BC24
[14] SA_CLK_DDR#0 MA_CLK_L0/MAA_CKC MA_DATA50/MAB_DATA14 DDR_A_D51 [15] SB_CLK_DDR0 SB_CLK_DDR#0 MB_CLK_H0/MBA_CKT MB_DATA49/MBB_DATA10 DDR_B_D50
AJ22 AN18 AK30 BC22
MA_CLK_H1/MAB_CKT MA_DATA51/MAB_DATA15 DDR_A_D52 [15] SB_CLK_DDR#0 MB_CLK_L0/MBA_CKC MB_DATA50/MBB_DATA14 DDR_B_D51
AJ21 AU23 AK32 BA22
MA_CLK_L1/MAB_CKC MA_DATA52/MAB_DATA12 AR22 DDR_A_D53 AL31 MB_CLK_H1/MBB_CKT MB_DATA51/MBB_DATA15 BB25 DDR_B_D52
MA_DATA53/MAB_DATA13 AN20 DDR_A_D54 MB_CLK_L1/MBB_CKC MB_DATA52/MBB_DATA12 BD25 DDR_B_D53
MA_DATA54/MAB_DATA9 AP19 DDR_A_D55 MB_DATA53/MBB_DATA13 BB22 DDR_B_D54
MA_DATA55/MAB_DATA8 MB_DATA54/MBB_DATA9 BD22 DDR_B_D55
AT19 DDR_A_D56 MB_DATA55/MBB_DATA8
DDR_A_CS0# AL25 MA_DATA56/MAB_DATA6 AW18 DDR_A_D57 BA21 DDR_B_D56
[14] DDR_A_CS0# MA_CS_L0/MAB_CA2 MA_DATA57/MAB_DATA7 DDR_A_D58 DDR_B_CS0# MB_DATA56/MBB_DATA4 DDR_B_D57
AM26 AU16 AN30 BC21
MA_CS_L1/MAB_CA5 MA_DATA58/MAB_DATA2 DDR_A_D59 [15] DDR_B_CS0# MB_CS_L0/MBB_CA2 MB_DATA57/MBB_DATA5 DDR_B_D58
AW16 AR31 BC18
MA_DATA59/MAB_DATA3 AW19 DDR_A_D60 MB_CS_L1/MBB_CA5 MB_DATA58/MBB_DATA2 BB18 DDR_B_D59
MA_DATA60/MAB_DATA4 AU19 DDR_A_D61 MB_DATA59/MBB_DATA3 BB20 DDR_B_D60
MA_DATA61/MAB_DATA5 AP16 DDR_A_D62 MB_DATA60/MBB_DATA6 BB21 DDR_B_D61
MA_DATA62/MAB_DATA1 AT16 DDR_A_D63 MB_DATA61/MBB_DATA7 BB19 DDR_B_D62
DDR_A_CKE0 AD24 MA_DATA63/MAB_DATA0 MB_DATA62/MBB_DATA1 BA18 DDR_B_D63
[14] DDR_A_CKE0 MA_CKE0/MAA_CA1 DDR_B_CKE0 MB_DATA63/MBB_DATA0
AD25 W27 AC31
MA_CKE1/MAA_CA0 MA_CHECK0/RSVD_54 [15] DDR_B_CKE0 MB_CKE0/MBA_CA1
W25 AC29 W30
MA_CHECK1/RSVD_53 AC26 MB_CKE1/MBA_CA0 MB_CHECK0/RSVD_56 W29
MA_CHECK2/RSVD_68 AC27 MB_CHECK1/RSVD_55 AA30
DDR_A_ODT0 AM24 MA_CHECK3/RSVD_69 V26 MB_CHECK2/RSVD_65 AB29
[14] DDR_A_ODT0 MA_ODT0/MAB_CA3 MA_CHECK4/RSVD_49 DDR_B_ODT0 MB_CHECK3/RSVD_67
B AM27 V24 AP32 V29 B
MA_ODT1/MAB_CA4 MA_CHECK5/RSVD_48 [15] DDR_B_ODT0 MB_ODT0/MBB_CA3 MB_CHECK4/RSVD_50
AA27 AR29 V31
+1.2V MA_CHECK6/RSVD_63 AA25 MB_ODT1/MBB_CA4 MB_CHECK5/RSVD_51 AA29
MA_CHECK7/RSVD_62 MB_CHECK6/RSVD_64 AA31
DDR_A_ALERT_N AE24 +1.2V +1.2V MB_CHECK7/RSVD_66
[14] DDR_A_ALERT_N MA_ALERT_L/TEST31A DDR_A_PARITY DDR_B_ALERT_N
AK24 DDR_A_PARITY [14] [15] DDR_B_ALERT_N
AE30
RC150 1 2 1K_0402_5% DDR_A_EVENT# AK23 MA_PAROUT/RSVD MB_ALERT_L/TEST31B AM31 DDR_B_PARITY
DDR4_A_DRAMRST# MA_EVENT_L DDR_B_EVENT# MB_PAROUT/RSVD DDR_B_PARITY [15]
[14] DDR4_A_DRAMRST# AD27 AN21 RC151 1 2 1K_0402_5% AL30
MA_RESET_L FP6 REV0.92 M_DDR4 AN22 DDR4_B_DRAMRST# AC32 MB_EVENT_L FP6 REV0.92
PART 1/13 M_LPDDR4 [15] DDR4_B_DRAMRST# MB_RESET_L PART 9/13

AMD-RENOIR-FP6_BGA1140 AMD-RENOIR-FP6_BGA1140
@ @

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP5 (MEM)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 5 of 45
5 4 3 2 1
 5 4 3 2 1

+3VS
RPC6 +1.8VS +1.8VS
UC1D DP_BLON=>VDD18 S0 APU_HDMI_DDC_CLK 1 4
APU_HDMI_DDC_DATA 2 3

2
APU_EDP_TX0+ D11 A22 DP_ENBKL PD FOR CUSTOMER
[16] APU_EDP_TX0+ APU_EDP_TX0- DP0_TXP0 DP_BLON DP_ENVDD PU FOR INTERNAL
B11 D23 RC52 RC49
+1.8VALW [16] APU_EDP_TX0- DP0_TXN0 DP_DIGON DP_EDP_PWM 2.2K_0404_4P2R_5%
C23
eDP APU_EDP_TX1+ C11 DP_VARY_BL DP2_HPD RC2 1 2 100K_0402_5%
39.2_0402_1%
@
1K_0402_5%
[16] APU_EDP_TX1+ APU_EDP_TX1- DP0_TXP1 APU_EDP_AUX APU_EDP_HPD
A11 D12 RC53 1 2 100K_0402_5%

APU_TEST31
[16] APU_EDP_TX1- APU_EDP_AUX [16]

1
1

DP0_TXN1 DP0_AUXP B12 APU_EDP_AUX# APU_HDMI_HPD RC155 1 2 100K_0402_5% APU_TEST31 DP_STEREOSYNC

RC50 D10 DP0_AUXN C12 APU_EDP_HPD APU_EDP_AUX# [16] eDP M_TEST CONNECTION TBD
APU_EDP_HPD [16]

2
4.7K_0402_5% B10 DP0_TXP2 DP0_HPD +1.8VS
DP0_TXN2 J20 APU_HDMI_DDC_CLK RC54 RC51
DP1_AUXP APU_HDMI_DDC_DATA APU_HDMI_DDC_CLK [17]
D9 K20
APU_HDMI_DDC_DATA [17] HDMI 39.2_0402_1% 1K_0402_5%
2

APU_RST# B9 DP0_TXP3 DP1_AUXN L21 APU_HDMI_HPD @ @

DP0_TXN3 DP1_HPD APU_HDMI_HPD [17] RPC7

1
D APU_HDMI_TX2+ DP2_AUXP APU_TEST17 D
PLACE CC30 CAPS CLOSE TO APU,CRB reserve 27pf G23 L19 4 5
[17] APU_HDMI_TX2+ APU_HDMI_TX2- DP1_TXP0 DP2_AUXP DP2_AUXN DP2_AUXP [22] APU_TEST14
H23 M19 3 6
1 [17] APU_HDMI_TX2- DP1_TXN0 DP2_AUXN M20 DP2_HPD DP2_AUXN [22] Type C APU_TEST16 2 7
APU_HDMI_TX1+ DP2_HPD DP2_HPD [22] APU_TEST15
CC30 F22 1 8
56P_50V_J_NPO_0201 [17] APU_HDMI_TX1+ APU_HDMI_TX1- DP1_TXP1
G22 M14 check with AMD ,Follow CRB ,USE PU, 07/29
2 [17] APU_HDMI_TX1- DP1_TXN1 DP3_AUXP
@ L14 10K_0804_8P4R_5%
HDMI APU_HDMI_TX0+ G21 DP3_AUXN L16 @
[17] APU_HDMI_TX0+ APU_HDMI_TX0- DP1_TXP2 DP3_HPD
H21
[17] APU_HDMI_TX0- DP1_TXN2 DP_STEREOSYNC
B23
APU_HDMI_CLK+ F20 DP_STEREOSYNC
+1.8VS +1.8VALW [17] APU_HDMI_CLK+ APU_HDMI_CLK- DP1_TXP3
G20
[17] APU_HDMI_CLK- DP1_TXN3 To EDP panel +3VS
1

1
RC55 PU FOR INTERNAL

RC416 4.7K_0402_5% PD FOR CUSTOMER +3VALW RC56

300_0402_5% 4.7K_0402_5%
@
2

2
APU_PWROK RC147
10K_0402_5%
PCH_EDP_PWM [16]
PLACE CC31 CAPS CLOSE TO APU,CRB reserve 27pf
1 BB6 TEST4 1 @ TC4

3
TEST4 BD5 TEST5 1 @ TC5 QC1B
CC31 TEST5

D2
56P_50V_J_NPO_0201 AG12 5
2 @ TEST6 G2
G25 APU_TEST14

S2
6
TEST14 K25 APU_TEST15
APU_TEST15
QC1A
TEST15 F25 APU_TEST16

D1

4
TEST16 F26 APU_TEST17
APU_TEST17 DP_EDP_PWM 2 PJT7838_SOT363-6
TEST17 G1
+3VS H26 APU_TEST31 1 @ TC7

S1
1
TEST31
RC58

1
RPC8 PJT7838_SOT363-6
AK9 1 @ TC8 100K_0402_5%
8 1 APU_SIC TEST41
7 2 APU_SID APU_TDI AP3 AK21

2
6 3 APU_PROCHOT#_R APU_TDO AU1 TDI ANALOGIO_0 AG21
C 5 4 ALERT# APU_TCK AR2 TDO ANALOGIO_1 C
APU_TMS AU3 TCK
APU_TRST# AR4 TMS
1/16W_1K_5%_8P4R_0804 APU_DBREQ# AT2 TRST_L
DBREQ_L +0.75VS

APU_RST# AW3 P3 SMU_ZVDDP RC60 1 2 196_0402_1%

[22] APU_RST# APU_PWROK RESET_L SMU_ZVDD
AW4
[44] APU_PWROK PWROK
RC62 1 2 0_0402_5% APU_SIC B22
+3VS_APU [25,30] EC_SMB_CK0 SIC
RC63 1 2 0_0402_5% APU_SID D22 DP_ENVDD RC72 1 2 0_0402_5%
[25,30] EC_SMB_DA0 SID VDDP_S5_SENSE PCH_ENVDD [16]
ALERT# C22 AK7 1 @ TC25
APU_THERMTRIP# AN9 ALERT_L VDDP_S5_SENSE AK12 APU_VDDP_RUN_FB_H 1 @ TC11
[30] APU_THERMTRIP#

1
RC66 1 2 0_0402_5% APU_PROCHOT#_R B25 THERMTRIP_L VDDP_SENSE J23 VDDCR_SOC_VCC_SENSE
[30]
APU_THERMTRIP# APU_PROCHOT# PROCHOT_L VDDCR_SOC_SENSE VDDCR_VCC_SENSE VDDCR_SOC_VCC_SENSE [44]
RC67 1 2 1K_0402_1% K22 RC71
VDDCR_SENSE VDDCR_VCC_SENSE [44]
J21 100K_0402_5%
RC68 1 2 0_0402_5% APU_SVC_RA D25 VDDIO_MEM_S3_SENSE
[44] APU_SVC SVC0
RC69 1 2 0_0402_5% APU_SVD_RA C25 J22 VDDCR_VSS_SENSE
[44] APU_SVD VDDCR_VSS_SENSE [44]

2
RC70 1 2 0_0402_5% APU_SVT_RA A25 SVD0 FP6 REV0.92 VSS_SENSE_A AJ12 VSS_SENSEB 1 @ TC12
[44] APU_SVT SVT0 PART 3/13 VSS_SENSE_B
LCD Power IC can change for PCH_ENVDD for cost down
AMD-RENOIR-FP6_BGA1140 VDDCR_SOC_VCC_SENSE 1 @ TC13
VDDCR_VCC_SENSE 1 @ TC14
@
APU_SVC APU_SVD APU_SVT VDDCR_VSS_SENSE 1 @ TC15
27P_25V_J_NPO_0201

27P_25V_J_NPO_0201

27P_25V_J_NPO_0201

1 1 1
CC34 CC35 CC36
@

2 2 2 DP_ENBKL RC81 1 2 0_0402_5%

PCH_ENBKL [16]

B B

New HDT conn +1.8VALW +1.8VALW

JHDT1 +1.8VALW
1 1/16W_1K_5%_8P4R_0804
1 2
2 3 APU_TCK 8 1
2

3 4 APU_TMS 7 2 RC74
4 5 APU_TDI 6 3 1K_0402_5%
5 6 APU_TDO 1 HDT@ 2 APU_DBREQ# 5 4 HDT@
6 7 APU_PWROK RC78
7 8 APU_RST# 33_0402_5% RPC9
1

8 9 APU_DBREQ#_R
9 10 APU_TRST#_R RC79 1 HDT@ 2 33_0402_5% HDT@ APU_TRST#
13 10 11 1
14 GND1 11 12 CC38
GND2 12 0.01U_6.3V_K_X7R_0201
HIGHS_FC1AF121-1151H HDT@
2
ME@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP5 (DP/JTAG/SIV2/MISC)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 6 of 45
5 4 3 2 1
 5 4 3 2 1

Mirror code: Platform allows RSMRST# = 0 to SPI tri-state

add reserved QC11,RC3268 For mirror 07/31 +1.8VALW +3VALW_APU
@ 0_0402_5%
PCIE_WAKE#_RA RC5 1 2

1
RC3 1 2 0_0402_5% 1 RC6

1
10K_0402_5%
RC4 CC21 @ EC_PCIE_WAKE# [30]
10K_0402_5% 10U 6.3V M X5R 0402 DC2
2 SYS_RESET# 1 2 SYS_PWRGD_R

2
2
RSMRST#_R RC8 1 2 0_0402_5% SYS_PWRGD_R RB751V-40_SOD323-2
[30] EC_RSMRST# [30] EC_SYS_PWRGD
1 1 @
1
CC22 CC24 @ CC23
+3VL 0.1U_6.3V_K_X5R_0201 0.1U_6.3V_K_X5R_0201 0.1U_6.3V_K_X5R_0201
2 2
2

1
RC3268
@ 10K_0402_5%
RC9 1 2 33_0402_5% PCIE_RST0#_R
[21,26,28] PLT_RST#

6
D D D

2
2 QC11A ADD 150P CAP 0804

1
G 2N7002KDWH_SOT363-6 1
@ RC10 CC25
S 100K_0402_5% 150P_25V_J_NPO_0402

1
3
D @
5 2 RPC1
QC11B

2
G 2N7002KDWH_SOT363-6 EGPIO145 1 4
@ EGPIO146 2 3
S

4
UC1E 10K_0404_4P2R_5%
AM3
SFH_IPIO271 AT4
SFH_IPIO272 AM1 EGPIO147 RC3271 1 2 10K_0402_5%
SFH_IPIO273 AJ8
SFH_IPIO274 AW7
SFH_IPIO39 AU2
PCIE_RST0#_R AP6 SFH_IPIO41
PCIE_RST1#_R AT13 PCIE_RST0_L/EGPIO26 AP14 EGPIO145 If unused, enable internal pull up or pull down by software.
RSMRST#_R AR8 PCIE_RST1_L/EGPIO27 I2C0_SCL/EGPIO145 AN14 EGPIO146
RSMRST_L I2C0_SDA/EGPIO146
PBTN_OUT# RC11 1 2 0_0402_5% PWRBTN#_R AT12 AP2 EGPIO147
[30] PBTN_OUT# SYS_PWRGD_R PWR_BTN_L/AGPIO0 I2C1_SCL/EGPIO147 BOARD_ID4
AW2 AN3 E14 is ID3 +1.8VS
SYS_RESET# AL2 PWR_GOOD I2C1_SDA/EGPIO148
[13] SYS_RESET# PCIE_WAKE#_RA SYS_RESET_L/AGPIO1 TS_I2C2_SCL_R
AW12 AN12
WAKE_L/AGPIO2 I2C2_SCL/EGPIO113/SMBUS0_I2C_SCL AP12 TS_I2C2_SDA_R TS_I2C2_SCL_R [16]
PM_SLP_S3# 2 PM_SLP_S3# RC14 1 2 0_0402_5% PM_SLP_S3#_R AT11 I2C2_SDA/EGPIO114/SMBUS0_I2C_SDA TS_I2C2_SDA_R [16] Touch Screen
CC146 @1 2200P_25V_K_X7R_0201
PM_SLP_S5# [30] PM_SLP_S3# PM_SLP_S5# RC15 PM_SLP_S5#_R SLP_S3_L TP_I2C3_SCL_R
CC147 @1 2 2200P_25V_K_X7R_0201 1 2 0_0402_5% AV11 AM9
[13,30] PM_SLP_S5# SLP_S5_L I2C3_SCL/AGPIO19/SMBUS1_I2C_SCL TP_I2C3_SDA_R TP_I2C3_SCL_R [13,31]
AM10
I2C3_SDA/AGPIO20/SMBUS1_I2C_SDA TP_I2C3_SDA_R [13,31]Touch Pad
AW13
S0A3_GPIO/AGPIO10 D24
RC3276 1 2 0_0402_5% AC_PRESENT_R BA8 SFH1_SCL B24
[30] AC_PRESENT AC_PRES/AGPIO23 SFH1_SDA
RC16 1 2 10K_0402_5% BATLOW# AV6
+3VALW_APU LLB_L/AGPIO12 QWLAN@
BB7 RC3274 1 2 0_0402_5% M2_UART_WAKE#_APU
AW8 AGPIO3 BA6 M2_UART_WAKE#_APU [26]
EGPIO42 AGPIO4/SATAE_IFDET SSD_SATA_PCIE_DET1# [21]
+3VS_TS
AK10 OD,Pull high 3VALW?
Follow E14 07/30 AGPIO5/DEVSLP0 BC6 SATA_DEVSLP1 RPC2
AGPIO6/DEVSLP1 BOARD_ID0 SATA_DEVSLP1 [21] TS_I2C2_SCL_R
AW15 3 2
SATA_ACT_L/AGPIO130 Follow E1415 Wait for define Board ID 07/27 TS_I2C2_SDA_R 4 1
AG6 AU4 BOARD_ID7
AG7 ACP_WOV_CLK AGPIO9 AP7 APU_SSD_RST# 2.2K_0404_4P2R_5%
AJ6 ACP_WOV_MIC0_MIC1_DATA AGPIO40 AV13 BOARD_ID2 APU_SSD_RST# [21]
ACP_WOV_MIC2_MIC3_DATA AGPIO69 BB12 RC169 1 2 0_0402_5% EC_SMI# +3VS_APU
C HDA_BITCLK AN6 AGPIO86/SPI_CLK2 EC_SMI# [30] C
RC19 1 2 0_0402_5% HDA_SDIN0_R AL6 AZ_BITCLK/TDM_BCLK_MIC
[33] HDA_SDIN0 HDA_SDIN1 AZ_SDIN0/CODEC_GPI INTRUDER_ALERT RC20 EC_SMI#
TC1 @ 1 AM7 AU7 2 @ 1 20M_0402_5%
VCCRTC RC21 1 2 2.2K_0402_5%
TC2 @ 1 HDA_SDIN2 AJ9 AZ_SDIN1/SW_DATA1B/TDM_BCLK_PLAYBACK INTRUDER_ALERT AR11 PCH_TP_INT# RC22 1 2 10K_0402_5%
HDA_RST# AZ_SDIN2/SW_DATA2/TDM_DATA_PLAYBACK/ACP_WOV_MIC4_MIC5_DATA SPKR/AGPIO91 PCH_BEEP [33]
AM6 AW11 BLINK
HDA_SYNC AN8 AZ_RST_L/SW_DATA1A/SW_DATA3/TDM_DATA_MIC BLINK/AGPIO11 APU_TS_INT# RC148 1 2 10K_0402_5%
Board ID[0:1] Board ID[2:3] Memory AZ_SYNC/TDM_FRM_MIC
HDA_SDOUT AK6 AV15 RC3277 1 PCH_TP_INT#
2 0_0402_5%
AZ_SDOUT/TDM_FRM_PLAYBACK GENINT1_L/AGPIO89 PCH_TP_INT# [31]
AU14 +3VALW_APU
AM4 GENINT2_L/AGPIO90 APU_TS_INT#_R RC149 1 2 0_0402_5%
00 4G SW_MCLK/TDM_BCLK_BT APU_TS_INT# [16]
AL3
AM2 SW_DATA0/TDM_DOUT_BT AT10 PCH_WLAN_OFF# RPC3
00 AGPIO7/FCH_ACP_I2S_SDIN_BT FANIN0/AGPIO84 PCH_WLAN_OFF# [26]
01 8G AL4 FP6 REV0.92 AU10 PCH_BT_OFF# TP_I2C3_SDA_R 3 2
Samsung AGPIO8/FCH_ACP_I2S_LRCLK_BT PART 4/13 FANOUT0/AGPIO85 PCH_BT_OFF# [26] TP_I2C3_SCL_R 4 1
10 16G
AMD-RENOIR-FP6_BGA1140 2.2K_0404_4P2R_5%
11 12G new mem board ID @
+3VS_APU +3VALW_APU
00 4G RPC4
01 Board ID[0:1] Board ID[2:3] PBTN_OUT# 1 8
RPC58 PCIE_WAKE#_RA
Micron Memory 2 7
01 8G PCH_WLAN_OFF# 1 4 AC_PRESENT 3 6
PCH_BT_OFF# 2 3 4 5
10 16G
00 4G 10K_0404_4P2R_5% 10K_0804_8P4R_5%
11 12G
Blink RC24 1 @ 2 10K_0402_5%
00 4G 无 RPC5 PM_SLP_S3# RC25 1 @ 2 2.2K_0402_5%
10 11 PM_SLP_S5# RC26 1 @ 2 2.2K_0402_5%
01 8G TC3 @ 1 HDA_RST_AUDIO# 1 8 HDA_RST# APU_SSD_RST# RC27 1 @ 2 10K_0402_5%
Hynix new-Hynix
01 8G 无 [33] HDA_SYNC_AUDIO
2 7 HDA_SYNC
3 6 HDA_BITCLK SATA_DEVSLP1 RC415 1 @ 2 10K_0402_5%
[33] HDA_BITCLK_AUDIO 4 5 HDA_SDOUT
10 16G 10 16G [33] HDA_SDOUT_AUDIO
11 12G 1/16W_33_5%_8P4R_0804 QWLAN@
11 12G M2_UART_WAKE#_APU RC3275 1 2 10K_0402_5%

0 TS RC45
Board_ID4
1 NON-TS RC38 For EMI
HDA_BITCLK
1
PCH_TP_INT# RC28 1 @ 2 10K_0402_5%
0 FP RC46 CC27 RSMRST#_R RC32 1 @ 2 100K_0402_5%
Board_ID5 56P_50V_J_NPO_0201 SYS_PWRGD_R RC33 1 2 100K_0402_5%
2 EMC_NS@
B EGPIO142 ID1---------->EGPIO132_SIV B
1 NON-FP RC39 PCIE_RST1#_R RC34 1 2 10K_0402_5%
EGPIO132 ID5 +3.3VS--->EGPIO120 SIV Close to PCH @

Reserved
Board_ID6
Reserved

Reserved
Board_ID7
Reserved

+3VS_APU

+3VALW_APU [0~3] for Memory

2
+1.8VS +3VS_APU RC42 RC43 RC48
10K_0402_5% 10K_0402_5% RC37 10K_0402_5%
@ @ 2K_0402_5% @
@

1
BOARD_ID0
AGPIO130 ID0
EGPIO142 ID1------>EGPIO132 _SIV
1

BOARD_ID1
2

RC425 RC38 [8] BOARD_ID1 BOARD_ID2 AGPIO69 ID2

EGPIO148 ID4 +1.8VS 2K_0402_5% 10K_0402_5% RC39 BOARD_ID3
EGPIO132 ID5 +3.3VS--->EGPIO120 SIV @ Non_TS@ 10K_0402_5% [8] BOARD_ID3 EGPIO131 ID3
ID0~2 Follw E14, ID4 is Change E14 ID3
2

NON_FP@
1

1
BOARD_ID4 RC44
BOARD_ID5 RC35 RC36 10K_0402_5% RC41
[8] BOARD_ID5 2K_0402_5% 2K_0402_5% @ 2K_0402_5%
AGPIO8 ID6 +3.3VALW BOARD_ID7 @ @ @

2
AGPIO7 ID7 +3.3VALW
2

RC45 RC46
2

RC427 10K_0402_5% 2K_0402_5%

A A
10K_0402_5%
@ TS@ FP@
ADD BOARD ID6~7 07/31
1

2
1

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP5 AZ/I2C/ACPI/GPIO

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 7 of 45
5 4 3 2 1
 5 4 3 2 1

LPCCLK0 PCH_SPI_CLK

2
RC82 1 2 33_0402_5% LPC_RST#_R
[13,30] APU_LPC_RST#
RC83
1 0_0201_5% RC90
CC41 EMC_NS@ 10_0402_5%
150P_25V_J_NPO_0402 EMC_NS@

1
2
1 1
CC42 CC43
22P_0201_25V8 10P_0201_25V8G
EMC_NS@ EMC_NS@
+3VS_APU 2 2
RPC11
1 4 SSD_CLKREQ#
EMC EMC
D D
2 3 WLAN_CLKREQ# UC1F

10K_0404_4P2R_5%
SSD_CLKREQ# AR13
[21] SSD_CLKREQ# WLAN_CLKREQ# AP10 CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92
[16] APU_TS_RST [26] WLAN_CLKREQ# APU_TS_RST AR15 CLK_REQ1_L/AGPIO115
RC422 1 2 10K_0402_5% APU_TS_RST BOARD_ID3 AT14 CLK_REQ2_L/AGPIO116
[7] BOARD_ID3 BOARD_ID1 AN11 CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131
[7] BOARD_ID1 BOARD_ID5 AN13 CLK_REQ4_L/OSCIN/EGPIO132
@ [7] BOARD_ID5 AN15 CLK_REQ5_L/EGPIO120 Follow E14 07/30
RC423 1 2 10K_0402_5% APU_TS_RST CLK_REQ6_L/EGPIO121 +3VS_APU
SIV ID1 is SDV ID5 0926 AW14 RC3278 1 2 0_0402_5% FPR_RESET
EGPIO70 BB13 LPCPD# FPR_RESET [34]
@ LPCPD# [13]
CLK_PCIE_SSD RC84 1 2 0_0402_5% CLK_PCIE_SSD_R AF11 LPC_PD_L/AGPIO21 BA16 LAD0 RC85 1 2 10_0402_5% LPC_FRAME# RC94 1 @ 2 10K_0402_5%
[21] CLK_PCIE_SSD CLK_PCIE_SSD# 1 2 0_0402_5% CLK_PCIE_SSD#_R AF12 GPP_CLK0P LAD0/ESPI1_DATA0/EGPIO104 BA15 LAD1 1 2 10_0402_5% LPC_AD0 [30]
PCIE CLK0 SSD1[21] RC86 RC87
CLK_PCIE_SSD# GPP_CLK0N LAD1/ESPI1_DATA1/EGPIO105 BC13 LAD2 1 2 10_0402_5% LPC_AD1 [30] KBRST# 1 2 10K_0402_5%
RC88 LPC_AD2 [30] RC96
CLK_PCIE_WLAN RC89 1 2 0_0402_5% CLK_PCIE_WLAN_R AG4 LAD2/ESPI1_DATA2/EGPIO106 BB14 LAD3 RC91 1 2 10_0402_5% @
[26] CLK_PCIE_WLAN GPP_CLK1P LAD3/ESPI1_DATA3/EGPIO107 LPC_AD3 [30]
CLK_PCIE_WLAN# RC92 1 2 0_0402_5% CLK_PCIE_WLAN#_R AG2 BB15 LPCCLK0 RC93 2 1 1/16W_3.3_1%_0402
PCIE CLK1 WLAN[26] CLK_PCIE_WLAN# GPP_CLK1N LPCCLK0/EGPIO74 BD13 LPC_CLKRUN#_R RC417 1 2 0_0402_5% CLK_PCI_EC [30] LDRQ0#_R
@ RC3270 1 2 10K_0402_5%
AG3 LPC_CLKRUN_L/AGPIO88 BA12 EGPIO75 LPC_CLKRUN# [13]
AG1 GPP_CLK2P LPCCLK1/EGPIO75 BC15 +3VALW_APU
GPP_CLK2N SERIRQ/AGPIO87 SERIRQ [13,30]
BA13
AF2 LFRAME_L/EGPIO109 LPC_FRAME# [30] EC_SCI# 1 2 10K_0402_5%
RC100 @
AF4 GPP_CLK3P BC12 LPC_RST#_R
Follow CRB 0Ω resistor pull down GPP_CLK3N LPC_RST_L/AGPIO32 AU12 INT#_TYPEC1_CPU
AH2 AGPIO68 AP4 EC_SCI_R# RC3279 1 2 0_0402_5% INT#_TYPEC1_CPU [22] Follow E14 07/31
1 2 0_0402_5% XGBECLK0 AH4 GPP_CLK4P LPC_PME_L/AGPIO22 EC_SCI# [30]
RC98
RC99 1 2 0_0402_5% XGBECLK1 GPP_CLK4N
AJ2 INT#_TYPEC1_CPU 10K_0402_5% 1 @ 2 RC114
AJ4 GPP_CLK5P BA11
GPP_CLK5N SPI_ROM_REQ/EGPIO67 BB11 AGPIO30 10K_0402_5% 1 2 RC116
AF8 SPI_ROM_GNT/EGPIO76
AF9 GPP_CLK6P/WIFIBT_CLKP AT15 KBRST# EGPIO75 10K_0402_5% 1 @ 2 RC117
GPP_CLK6N/WIFIBT_CLKN ESPI_RESET_L/KBRST_L/AGPIO129 LDRQ0#_R RC101 KBRST# [30]
BC11 1 LPC@ 2 0_0402_5% LDRQ0#
48M_OSC ESPI_ALERT_L/LDRQ0_L/EGPIO108 LDRQ0# [13]
TC16 @ 1 AK1 @
X48M_OSC BC10 SPI_CLK RC102 1 2 10_0402_5% PCH_SPI_CLKM
C SPI_CLK/ESPI_CLK C
BA10 SPI_D1 RC103 1 2 0_0402_5% PCH_SPI_D1_R
X48M_X1 BB3 SPI_DI/ESPI_DATA BB8 SPI_D0 RC104 1 2 0_0402_5% PCH_SPI_D0_R
X48M_X1 SPI_DO BA9 SPI_D2 RC105 1 2 0_0402_5% PCH_SPI_D2
SPI_WP_L/ESPI_DAT2 BC8 SPI_D3 RC106 1 2 0_0402_5% PCH_SPI_D3 SIV:Change "PCH_SPI_PIRQ#" From AGPIO88 to AGPIO31
SPI_HOLD_L/ESPI_DAT3 BD11 SPI_CS1# RC107 1 2 0_0402_5% PCH_SPI_CS1#
X48M_X2 BA5 SPI_CS1_L BC9 AGPIO30
X48M_X2 SPI_CS2_L/ESPI_CS_L/AGPIO30 PCH_SPI_PIRQ# [28]
BB10 RC418 1 TPM@ 2 0_0402_5%
SPI_CS3_L/AGPIO31 BD8 SPI_CS#_TPM
SPI_TPM_CS_L/AGPIO29 SPI_CS#_TPM [28] +3VS_APU

XGBECLK0 AG10
XGBECLK1 AG9 RSVD_71 APU_UART0_TXD
RSVD_70 APU_UART0_TXD [26]

1 RC108 2

1 RC109 2

1 RC3273 2

1 RC111 2
1K_0402_1%

1K_0402_1%

1K_0402_1%

1K_0402_1%
APU_UART0_RTS#

QWLAN@

QWLAN@
APU_UART0_RTS# [26]
AW10
[26] SUSCLK RTCCLK
APU_UART0_RXD
X32K_X1 AY1 BA17 APU_UART0_RXD APU_UART0_RXD [26]
X32K_X1 EGPIO141/UART0_RXD BC16 APU_UART0_TXD @ @
EGPIO143/UART0_TXD BD15 APU_UART0_RTS# APU_UART0_CTS#
EGPIO142/UART0_RTS_L/UART1_RXD BC17 APU_UART0_CTS# APU_UART0_CTS# [26]
RC113 X32K_X2 AY4 EGPIO140/UART0_CTS_L/UART1_TXD BB16 FPR_DELINK_C R3101 @ 2 0_0201_5% FPR_DELINK
1 2 X32K_X2 AGPIO144/SHUTDOWN_L/UART0_INTR FPR_DELINK [30,34]
20M_0402_5% FP6 REV0.92
YC1 PART 5/13
1 2
AMD-RENOIR-FP6_BGA1140
32.768KHZ_12.5PF_202740-PG14 @ ADD QC7 For Mirror required 07/31

1 1
SIV:Modfify CC44(9pf), CC45(12pf) to 9pf 0922 +3VALW_APU
CC44 CC45
48MHz/10pF Crystal X48M_X1 9P_50V_B_NPO_0402 9P_50V_B_NPO_0402
SVT:Modify CC44,CC45 to 9pf_20200117
2 2
X48M_X2 Modify QC7 to SB00000ZI00 0805

2
B B
RC115 1 2 1M_0402_5%
PCH_SPI_CLKM 3 1 PCH_SPI_CLK_R
PCH_SPI_CLK_R [13]
Kevin H: change YC1 PN change to SJ10000MQ00,manual modify PN to SJ10000MQ00
YC2

1 4 +1.8V_SPI +1.8VALW QC7

OSC1 NC2 UB1
PCH_SPI_CS1# +1.8V_SPI
0.085 A LSI1012XT1G_SC-89-3
2 3 1 8 RC118 1 2 0_0402_5% RC3269 1 2 0_0402_5%
NC1 OSC2 PCH_SPI_D1 2 /CS VCC 7 PCH_SPI_D3
PCH_SPI_D2 3 DO(IO1) /RST(IO3) 6 PCH_SPI_CLK
1 @
48MHZ 10PF +-10PPM 7V48000023 4 /WP(IO2) CLK 5 PCH_SPI_D0
1 1 GND DI(IO0) CC48
CC46 CC47 W74M12JWSSIQ_SO8 0.1U_6.3V_K_X5R_0201
5.6P_50V_C_NPO_0402 5.6P_50V_C_NPO_0402 2 PCH_SPI_CLK_R RC159 1 2 0_0201_5% PCH_SPI_CLK
2 2
RC160 1 2 0_0201_5%
EC_SPI_CLK [30]

16MB(128Mb)
SIV:Modfify CC46/47 From 8p to 5.6pF _0922 RC161 1 TPM@ 2 0_0201_5%
TPM_SPI_CLK [28]

PCH_SPI_CS1# RC162 1 2 0_0201_5% EC_SPI_CS1#

EC_SPI_CS1# [30]
Need change to ±10ppm
R-BOM has change SJ10000VD00 10ppm +1.8V_SPI PCH_SPI_D0_R PCH_SPI_D0
RC163 1 2 0_0201_5%
UC4 RC164 1 2 0_0201_5%
PCH_SPI_CS1# 1 8 +1.8V_SPI EC_SPI_SI [30]
/CS VCC RC165 1 TPM@ 2 0_0201_5%
PCH_SPI_D1 2 7 PCH_SPI_D3 TPM_SPI_MOSI [28]
IO1 IO3
PCH_SPI_D2 3 6 PCH_SPI_CLK
IO2 CLK
4 5 PCH_SPI_D0 PCH_SPI_D1_R RC166 1 2 0_0201_5% PCH_SPI_D1
GND IO0
9 RC167 1 2 0_0201_5%
PAD_GND EC_SPI_SO [30]
@
+1.8V_SPI RC168 1 TPM@ 2 0_0201_5%
A TPM_SPI_MISO [28] A
W74M25JWZEIQ_WSON8_8X6
RC119 1 2 10K_0402_5% PCH_SPI_CS1#
RC120 1 2 10K_0402_5% PCH_SPI_D1
RC121 1 @ 2 10K_0402_5% PCH_SPI_D2
RC122 1 @ 2 10K_0402_5% PCH_SPI_D3

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP5 CLK/LPC/SD/EMMC/UART
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Thursday, November 05, 2020 Sheet 8 of 45
5 4 3 2 1
 5 4 3 2 1

UC1G

N7 P8
R7 AGPIO256/WIFIBT_BT_DATA EGPIO267/RFIC_SPI_CLK R9
N6 AGPIO257/WIFIBT_BT_VALID EGPIO268/RFIC_SPI_SS R6
T6 AGPIO258/WIFIBT_BT_SYNC AGPIO269/RFIC_SPI_DATA
AGPIO259/WIFIBT_BT_CLK

D R10 P9 D
T12 AGPIO260/WIFIBT_QSPI_DATA0 AGPIO270/WIFIBT_RFIC_WAKEUP T9
P12 AGPIO261/WIFIBT_QSPI_DATA1 EGPIO271/WIFIBT_BUCKEN T8
P11 AGPIO262/WIFIBT_QSPI_DATA2 EGPIO266/WIFIBT_FLOW
T11 AGPIO263/WIFIBT_QSPI_DATA3
P6 AGPIO264/WIFIBT_QSPI_CLK
AGPIO265/WIFIBT_QSPI_SS V7
WIFIBT_DATA_RXP V6
WIFIBT_DATA_RXN
V9
WIFIBT_DATA_TXP V10
WIFIBT_DATA_TXN
FP6 REV0.92
PART 12/13

AMD-RENOIR-FP6_BGA1140
@

UC1H

For Full type c USB20_P0 AC6 AA1 USBC0_TX_P1

[24] USB20_P0 USB20_N0 USBC0_DP/USB0_DP USBC0_TX1P/USB0_TXP/DP2_TXP2 USBC0_TX_N1 USBC0_TX_P1 [24]
USB P0 AC7 AA3
[24] USB20_N0 USBC0_DN/USB0_DN USBC0_TX1N/USB0_TXN/DP2_TXN2 USBC0_TX_N1 [24]
USB20_P1 AA8 AA2 USBC0_RX_P1 USB Type-C 1
[27] USB20_P1 USB20_N1 USB1_DP USBC0_RX1P/USB0_RXP/DP2_TXP3 USBC0_RX_N1 USBC0_RX_P1 [24]
USB3.0 Port1 AOU AA9 AA4
[27] USB20_N1 USB1_DN USBC0_RX1N/USB0_RXN/DP2_TXN3 USBC0_RX_N1 [24]
USB P1
USB20_P2 Y10 AC2 USBC0_TX_P2 USB Typec integrated USBC SWITCH with DP
[16] USB20_P2 USB20_N2 USB2_DP USBC0_TX2P/DP2_TXP1 USBC0_TX_N2 USBC0_TX_P2 [24]
For camera [16] USB20_N2 Y9 AC4
USB2_DN USBC0_TX2N/DP2_TXN1 USBC0_TX_N2 [24]
USB P2
Y7 AC1 USBC0_RX_P2
USB3_DP USBC0_RX2P/DP2_TXP0 USBC0_RX_N2 USBC0_RX_P2 [24]
Touch Screen Y6 AC3
Remove Reserved USB 2.0 Interface 07/29 USB3_DN USBC0_RX2N/DP2_TXN0 USBC0_RX_N2 [24]
USB P3 AE1 USB30_TX_P1
USB1_TXP USB30_TX_N1 USB30_TX_P1 [27]
AE3
USB20_P4 USB1_TXN USB30_TX_N1 [27]
AC9
[27] USB20_P4 USB20_N4 USBC4_DP/USB4_DP USB30_RX_P1
IO Board for USB3.0 port2 [27] USB20_N4 AC10 AD8 USB30_RX_P1 [27] USB3.0 Port1 AOU
USB P4 USBC4_DN/USB4_DN USB1_RXP AD9 USB30_RX_N1
USB20_P5 USB1_RXN USB30_RX_N1 [27]
C IO Board for Card reader AA11 C
[27] USB20_P5 USB20_N5 USB5_DP
USB P5 [27] USB20_N5 AA12
USB5_DN
BT USB20_P6 W8
[26] USB20_P6 USB20_N6 USB6_DP USB30_TX_P4
USB P6 [26] USB20_N6 W9 V3
USB6_DN USBC4_TX1P/USB4_TXP/DP3_TXP2 USB30_TX_N4 USB30_TX_P4 [27]
V1
USB20_P7 USBC4_TX1N/USB4_TXN/DP3_TXN2 USB30_TX_N4 [27]
Finger print W11
[34] USB20_P7 USB20_N7 USB7_DP USB30_RX_P4
USB P7 [34] USB20_N7 W12 U4 USB30_RX_P4 [27] USB3.0 port2
+1.8VALW USB7_DN USBC4_RX1P/USB4_RXP/DP3_TXP3 U2 USB30_RX_N4
USBC4_RX1N/USB4_RXN/DP3_TXN3 USB30_RX_N4 [27]
RPC57
1 4 USBC_I2C_SCL AL9 W2
2 3 USBC_I2C_SCL USBC4_TX2P/DP3_TXP1 W4
USBC_I2C_SDA AL8 USBC4_TX2N/DP3_TXN1
4.7K_0404_4P2R_5% USBC_I2C_SDA W1
USBC4_RX2P/DP3_TXP0 W3
USB_OC0# AE9 USBC4_RX2N/DP3_TXN0
[27] USB_OC0# USB_OC1# USB_OC0_L/AGPIO16
[27] USB_OC1# AE10 AD2
AE6 USB_OC1_L/AGPIO17 USB5_TXP AD4
FN_LED# AE7 USB_OC2_L/AGPIO18 USB5_TXN
[31] FN_LED# USB_OC3_L/AGPIO24 AD12
USB5_RXP AD11
USB5_RXN

FP6 REV0.92
PART 10/13

AMD-RENOIR-FP6_BGA1140
@

+3VALW_APU
Vgs(th) max= 1V
B RPC12 B
USB_OC0# 1 4
USB_OC1# 2 3 +1.8VALW
PD I2C port
10K_0404_4P2R_5%

RC419 10K_0402_5%
FN_LED# 2 1
@

2
G1
USBC_I2C_SCL 1 6 PDC_SCL
S1 D1 PDC_SCL [22]
ADD Revsered RC419 07/30

QC8A
PJT7838_SOT363-6

5
G2
USBC_I2C_SDA 4 3 PDC_SDA
S2 D2 PDC_SDA [22]

QC8B
PJT7838_SOT363-6

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP5 USB/WIFI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 9 of 45
5 4 3 2 1
 5 4 3 2 1

D D

UC1I

D21 A18
A20 CAM0_CSI2_CLOCKP CAM0_CLK
CAM0_CSI2_CLOCKN C18
D18 CAM0_I2C_SCL B17
C B18 CAM0_CSI2_DATAP0 CAM0_I2C_SDA C
CAM0_CSI2_DATAN0 D17
C19 CAM0_SHUTDOWN
D20 CAM0_CSI2_DATAP1
CAM0_CSI2_DATAN1
C21
B21 CAM0_CSI2_DATAP2
CAM0_CSI2_DATAN2
C20
B20 CAM0_CSI2_DATAP3
CAM0_CSI2_DATAN3
C15 A13
A15 CAM1_CSI2_CLOCKP CAM1_CLK
CAM1_CSI2_CLOCKN B13
D16 CAM1_I2C_SCL D13
B16 CAM1_CSI2_DATAP0 CAM1_I2C_SDA
CAM1_CSI2_DATAN0 C14
D15 CAM1_SHUTDOWN
B15 CAM1_CSI2_DATAP1 C16
CAM1_CSI2_DATAN1 FP6 REV0.92 CAM_PRIV_LED C13
PART 13/13 CAM_IR_ILLU

AMD-RENOIR-FP6_BGA1140
@

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP5 CAM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 10 of 45
5 4 3 2 1
 5 4 3 2 1

+VDDC_VDD
+VDDCR_SOC +VDDC_VDD
UC1J
15A N16 G7 44A
N18 VDDCR_SOC_1 VDDCR_1 G10
VDDCR_SOC_2 VDDCR_2

180P_50V_J_NPO_0402
N20 G12
P17 VDDCR_SOC_3 VDDCR_3 G14
P19 VDDCR_SOC_4 VDDCR_4 H8
VDDCR_SOC_5 VDDCR_5 1

CC60
R18 H11
R20 VDDCR_SOC_6 VDDCR_6 H15
T19 VDDCR_SOC_7 VDDCR_7 K6
U18 VDDCR_SOC_8 VDDCR_8 K12 2
U20 VDDCR_SOC_9 VDDCR_9 K14
D D
V19 VDDCR_SOC_10 VDDCR_10 L8
W18 VDDCR_SOC_11 VDDCR_11 M7
W20 VDDCR_SOC_12 VDDCR_12 M10
Y19 VDDCR_SOC_13 VDDCR_13 N14
VDDCR_SOC_14 VDDCR_14 P7
VDDCR_15 P10
+1.2V VDDCR_16 P13
VDDCR_17 P15
6A AC20 VDDCR_18 R8
AC28 VDDIO_MEM_S3_1 VDDCR_19 R14
AD23 VDDIO_MEM_S3_2 VDDCR_20 R16
AD26 VDDIO_MEM_S3_3 VDDCR_21 T7 +VDDCR_SOC

22UC_6.3VC_MC_X5RC_0603
AD28 VDDIO_MEM_S3_4 VDDCR_22 T10
AD32 VDDIO_MEM_S3_5 VDDCR_23 T13
+3VS_APU AE20 VDDIO_MEM_S3_6 VDDCR_24 T15
+3VS VDDIO_MEM_S3_7 VDDCR_25

180P_50V_J_NPO_0402
AE22 T17
VDDIO_MEM_S3_8 VDDCR_26

1U_0402_6.3V6K
AE25 U14
VDDIO_MEM_S3_9 VDDCR_27

22UC_6.3VC_MC_X5RC_0603
AE28 U16

1U_0402_6.3V6K

1U_0402_6.3V6K
VDDIO_MEM_S3_10 VDDCR_28 1 1

CC76

CC77
RC125 1 2 0_0402_5%
1 1 1 1 AF23 V13
VDDIO_MEM_S3_11 VDDCR_29

CC141
AF26 V15

CC66

CC67

CC68
22UC_6.3VC_MC_X5RC_0603

AF28 VDDIO_MEM_S3_12 VDDCR_30 V17

@ AF32 VDDIO_MEM_S3_13 VDDCR_31 W7 2 2
2 2 2 2 AG20 VDDIO_MEM_S3_14 VDDCR_32 W10
AG22 VDDIO_MEM_S3_15 VDDCR_33 W14
+1.8VS BO BU AG25 VDDIO_MEM_S3_16 VDDCR_34 W16
AG28 VDDIO_MEM_S3_17 VDDCR_35 Y8
1U_0402_6.3V6K

1U_0402_6.3V6K
AJ20 VDDIO_MEM_S3_18 VDDCR_36 Y13
1 1 1 VDDIO_MEM_S3_19 VDDCR_37
AJ23 Y15
CC78

CC79

CC80

AJ26 VDDIO_MEM_S3_20 VDDCR_38 Y17

@ AJ28 VDDIO_MEM_S3_21 VDDCR_39 AA7
2 2 2 AJ32 VDDIO_MEM_S3_22 VDDCR_40 AA10
22UC_6.3VC_MC_X5RC_0603

+1.8VS +1.8VALW AK22 VDDIO_MEM_S3_23 VDDCR_41 AA14

BO BU AK25 VDDIO_MEM_S3_24 VDDCR_42 AA16
AK28 VDDIO_MEM_S3_25 VDDCR_43 AA18
+1.8VALW AL23 VDDIO_MEM_S3_26 VDDCR_44 AB13
VDDIO_MEM_S3_27 VDDCR_45

2
AL26 AB15
1U_0402_6.3V6K

1U_0402_6.3V6K

RC126 RC127 AL28 VDDIO_MEM_S3_28 VDDCR_46 AB17 +1.2V

1 1 VDDIO_MEM_S3_29 VDDCR_47
AL32 AB19
CC82

CC83

1 0_0402_5% 0_0402_5% VDDIO_MEM_S3_30 VDDCR_48

AM22 AC14
CC81

@ @ +VDD_AUD_ALW AM25 VDDIO_MEM_S3_31 VDDCR_49 AC16

22UC_6.3VC_MC_X5RC_0603
1

1
2 2 VDDIO_MEM_S3_32 VDDCR_50

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

180P_50V_J_NPO_0402
AM28 AC18

0.22U_6.3V_K_X5R_0201
22UC_6.3VC_MC_X5RC_0603

2 VDDIO_MEM_S3_33 VDDCR_51

1U_0402_6.3V6K

1U_0402_6.3V6K
AN28 AD7

1U_0402_6.3V6K
BO BU AN32 VDDIO_MEM_S3_34 VDDCR_52 AD10
1 1 1 VDDIO_MEM_S3_35 VDDCR_53 1 1 1 1 1 1 1 1 1

CC88

CC89

CC90

CC91

CC93

CC95

CC96

CC122

CC98
AP28 AD13

CC84

CC85

CC86
C +3VALW_APU AR32 VDDIO_MEM_S3_36 VDDCR_54 AD15 C
VDDIO_MEM_S3_37 VDDCR_55 AD17
1U_0402_6.3V6K

1U_0402_6.3V6K

@ @
1 1
2 2 2 1A AC21 VDDCR_56 AD19 2 2 2 2 2 2 2 2 2
AD21 VDDIO_VPH_1 VDDCR_57 AE8
CC100

CC101

1 VDDIO_VPH_2 VDDCR_58 AE14

CC99

BO BU
@
0.2A AP9 VDDCR_59 AE16
2 2 VDDIO_AUDIO VDDCR_60 AE18
0.25A
22UC_6.3VC_MC_X5RC_0603

2 AL18 VDDCR_61 AF7

BO BU AM17 VDD_33_1 VDDCR_62 AF10
VDD_33_2 VDDCR_63 AF13 @
+0.75VALW 2.5A AL20 VDDCR_64 AF15
ALL BU(on bottom side under SOC)
AM19 VDD_18_1 VDDCR_65 AF17
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

VDD_18_2 VDDCR_66 AF19

1 1 1 1A AL19 VDDCR_67 AG14
CC103

CC104

CC105

1 VDD_18_S5_1 VDDCR_68
AM18 AG16
CC102

VDD_18_S5_2 VDDCR_69 AG18

2 2 2 0.25A AL17 VDDCR_70 AH13 +1.2V
2 AM16 VDD_33_S5_1 VDDCR_71 AH15
VDD_33_S5_2 VDDCR_72 AH17
2A
22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

@ VDDCR_73
BO BU AL11 AH19
+0.75VS AL12 VDDP_S5_1 VDDCR_74 AJ7
VDDP_S5_2 VDDCR_75

180P_50V_J_NPO_0402

180P_50V_J_NPO_0402
AM12 AJ10
180P_50V_J_NPO_0402

VDDP_S5_3 VDDCR_76

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201
AJ14
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1 1 1 1 1 1 1 1 1 1 1
2A M15 VDDCR_77 AJ16 1 1 1 1 1 1
VDDP_1 VDDCR_78

CC117

CC118

CC119

CC120

CC121

CC97
M16 AJ18
CC106

CC107

CC108

CC109

CC110

CC111

CC112

CC113

CC114

CC115

CC116

M18 VDDP_2 VDDCR_79 AK13

VDDP_3 VDDCR_80 AK15 @
2 2 2 2 2 2 2 2 2 2 2 VDDCR_81 AK17 2 2 2 2 2 2
VDDCR_82 AK19
4.5uA AJ11 VDDCR_83
BO(Bottom side outside SOC) BU VDDBT_RTC_G FP6 REV0.92
JCMOS1 PART 6/13
@ Decoupling between processor and DIMMs
VCCRTC +RTCBATT_APU AMD-RENOIR-FP6_BGA1140
@
Across vddio and vss split
1

1 2
RC128 1K_0402_5%
0.22U_6.3V_K_X5R_0201
1U_0402_6.3V6K

1 1 +1.2V
CC123

CC124

2 2

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
1

B 1 1 1 1 1 1 1 1 1 B

CC125

CC127

CC128

CC129

CC130

CC131

CC132

CC133

CC134
RC130
470_0603_5%
@
2 2 2 2 2 2 2 2 2
12

D QC4
2 EC_RTCRST#_ON
G EC_RTCRST#_ON [30]
2

@ @ @ @ @ @ @ @
S L2N7002KWT1G_SOT323-3 RC131
3

@ 10K_0402_5%
@ Reserved for debug
1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP5 POWER

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 11 of 45
5 4 3 2 1
 5 4 3 2 1

D D

UC1K UC1L UC1M

AM20 K28 AR14 BD19 V5 AE13

A3 VSS_310 VSS_60 K32 AR16 VSS_246 VSS_305 BD21 V8 VSS_122 VSS_184 AE15
A5 VSS_1 VSS_61 L5 AR19 VSS_247 VSS_306 BD23 V11 VSS_123 VSS_185 AE17
A7 VSS_2 VSS_62 L13 AR21 VSS_248 VSS_307 BD26 V14 VSS_124 VSS_186 AE19
A10 VSS_3 VSS_63 L15 AR26 VSS_249 VSS_308 BD30 V16 VSS_125 VSS_187 AF1
A12 VSS_4 VSS_64 L18 AR28 VSS_250 VSS_309 V18 VSS_126 VSS_188 AF3
A14 VSS_5 VSS_65 L20 AT23 VSS_251 V20 VSS_127 VSS_189 AF5
A16 VSS_6 VSS_66 L25 AU5 VSS_252 V22 VSS_128 VSS_190 AF14
A19 VSS_7 VSS_67 L28 AU8 VSS_253 V25 VSS_129 VSS_191 AF16
A21 VSS_8 VSS_68 M1 AU11 VSS_254 V28 VSS_130 VSS_192 AF18
A23 VSS_9 VSS_69 M3 AU13 VSS_255 W5 VSS_131 VSS_193 AF20
A26 VSS_10 VSS_70 M5 AU15 VSS_256 W13 VSS_132 VSS_194 AG5
A30 VSS_11 VSS_71 M21 AU18 VSS_257 AV8 W15 VSS_133 VSS_195 AG8
C3 VSS_12 VSS_72 M23 AU20 VSS_258 RSVD_46 BD18 W17 VSS_134 VSS_196 AG11
C10 VSS_13 VSS_73 M26 AU22 VSS_259 RSVD_47 AV3 W19 VSS_135 VSS_197 AG13
C32 VSS_14 VSS_74 M28 AU25 VSS_260 RSVD_45 AU6 W23 VSS_136 VSS_198 AG15
E7 VSS_15 VSS_75 M32 AU28 VSS_261 RSVD_44 AR6 W26 VSS_137 VSS_199 AG17
E8 VSS_16 VSS_76 N5 AV1 VSS_262 RSVD_43 AR3 W28 VSS_138 VSS_200 AG19
E10 VSS_17 VSS_77 N8 AV5 VSS_263 RSVD_42 AP1 W32 VSS_139 VSS_201 AH14
E11 VSS_18 VSS_78 N11 AV7 VSS_264 RSVD_41 AN16 Y1 VSS_140 VSS_202 AH16
E12 VSS_19 VSS_79 N13 AV10 VSS_265 RSVD_40 AN4 Y3 VSS_141 VSS_203 AH18
E13 VSS_20 VSS_80 N15 AV12 VSS_266 RSVD_39 AN2 Y5 VSS_142 VSS_204 AH20
C E14 VSS_21 VSS_81 N17 AV14 VSS_267 RSVD_38 AM14 Y11 VSS_143 VSS_205 AJ1 C
E15 VSS_22 VSS_82 N22 AV16 VSS_268 RSVD_37 AM13 Y14 VSS_144 VSS_206 AJ3
E16 VSS_23 VSS_83 N25 AV19 VSS_269 RSVD_36 AL29 Y16 VSS_145 VSS_207 AJ5
E18 VSS_24 VSS_84 N28 AV21 VSS_270 RSVD_35 AL15 Y18 VSS_146 VSS_208 AJ13
E19 VSS_25 VSS_85 P1 AV23 VSS_271 RSVD_34 AL14 Y20 VSS_147 VSS_209 AJ15
E20 VSS_26 VSS_86 P5 AV26 VSS_272 RSVD_33 AL13 Y22 VSS_148 VSS_210 AJ17
E21 VSS_27 VSS_87 P14 AV28 VSS_273 RSVD_32 AK3 Y25 VSS_149 VSS_211 AJ19
E22 VSS_28 VSS_88 P16 AV32 VSS_274 RSVD_31 AJ29 Y28 VSS_150 VSS_212 AK5
E23 VSS_29 VSS_89 P18 AW5 VSS_275 RSVD_30 AJ27 AA5 VSS_151 VSS_213 AK8
E25 VSS_30 VSS_90 P20 AW28 VSS_276 RSVD_29 AF6 AA13 VSS_152 VSS_214 AK11
E26 VSS_31 VSS_91 P23 AY6 VSS_277 RSVD_28 AE12 AA15 VSS_153 VSS_215 AK14
E27 VSS_32 VSS_92 P26 AY7 VSS_278 RSVD_27 AD6 AA17 VSS_154 VSS_216 AK16
F5 VSS_33 VSS_93 P28 AY8 VSS_279 RSVD_26 AD3 AA19 VSS_155 VSS_217 AK18
F19 VSS_34 VSS_94 P32 AY10 VSS_280 RSVD_25 AC30 AA23 VSS_156 VSS_218 AK20
F21 VSS_35 VSS_95 R5 AY11 VSS_281 RSVD_24 AC12 AA26 VSS_157 VSS_219 AL1
F23 VSS_36 VSS_96 R11 AY12 VSS_282 RSVD_23 AB31 AA28 VSS_158 VSS_220 AL5
F28 VSS_37 VSS_97 R13 AY13 VSS_283 RSVD_22 AA20 AA32 VSS_159 VSS_221 AL7
G1 VSS_38 VSS_98 R15 AY14 VSS_284 RSVD_21 AA6 AB2 VSS_160 VSS_222 AL10
G3 VSS_39 VSS_99 R17 AY15 VSS_285 RSVD_20 Y12 AB4 VSS_161 VSS_223 AL16
G5 VSS_40 VSS_100 R19 AY16 VSS_286 RSVD_19 W6 AB14 VSS_162 VSS_224 AM5
G16 VSS_41 VSS_101 R22 AY18 VSS_287 RSVD_18 V12 AB16 VSS_163 VSS_225 AM8
G26 VSS_42 VSS_102 R25 AY19 VSS_288 RSVD_17 R12 AB18 VSS_164 VSS_226 AM11
G28 VSS_43 VSS_103 R28 AY20 VSS_289 RSVD_16 N19 AB20 VSS_165 VSS_227 AM15
G32 VSS_44 VSS_104 T1 AY21 VSS_290 RSVD_15 N12 AC5 VSS_166 VSS_228 AN1
H5 VSS_45 VSS_105 T3 AY22 VSS_291 RSVD_14 N10 AC8 VSS_167 VSS_229 AN5
H13 VSS_46 VSS_106 T5 AY23 VSS_292 RSVD_13 N9 AC11 VSS_168 VSS_230 AN7
H18 VSS_47 VSS_107 T14 AY25 VSS_293 RSVD_12 M13 AC13 VSS_169 VSS_231 AN10
H20 VSS_48 VSS_108 T16 AY26 VSS_294 RSVD_11 M12 AC15 VSS_170 VSS_232 AN23
H22 VSS_49 VSS_109 T18 AY27 VSS_295 RSVD_10 M11 AC17 VSS_171 VSS_233 AN26
H25 VSS_50 VSS_110 T20 BB1 VSS_296 RSVD_9 M6 AC19 VSS_172 VSS_234 AP5
H28 VSS_51 VSS_111 T23 BB32 VSS_297 RSVD_8 L12 AC22 VSS_173 VSS_235 AP8
J19 VSS_52 VSS_112 T26 BD3 VSS_298 RSVD_7 K19 AC25 VSS_174 VSS_236 AP13
K1 VSS_53 VSS_113 T28 BD7 VSS_299 RSVD_6 F16 AD1 VSS_175 VSS_237 AP15
K3 VSS_54 VSS_114 T32 BD10 VSS_300 RSVD_5 F14 AD5 VSS_176 VSS_238 AP18
K5 VSS_55 VSS_115 U13 BD12 VSS_301 RSVD_4 F12 AD14 VSS_177 VSS_239 AP20
K16 VSS_56 VSS_116 U15 BD14 VSS_302 RSVD_3 F10 AD16 VSS_178 VSS_240 AP25
K21 VSS_57 VSS_117 U17 BD16 VSS_303 RSVD_2 C26 AD18 VSS_179 VSS_241 AR1
K26 VSS_58 VSS_118 U19 VSS_304 RSVD_1 AD20 VSS_180 VSS_242 AR5
B VSS_59 VSS_119 V2 AE5 VSS_181 VSS_243 AR7 B
VSS_120 V4 FP6 REV0.92 AE11 VSS_182 VSS_244 AR12
FP6 REV0.92 VSS_121 PART 11/13 VSS_183 VSS_245
PART 7/13 FP6 REV0.92
AMD-RENOIR-FP6_BGA1140 AMD-RENOIR-FP6_BGA1140 PART 8/13
@ @ AMD-RENOIR-FP6_BGA1140
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP5 GND

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 12 of 45
5 4 3 2 1
 5 4 3 2 1

+1.8VS +1.8VALW +3VALW_APU

1
RC132 RC133 RC134
10K_0402_5% 10K_0402_5% 10K_0402_5%
@

2
D D
PCH_SPI_CLK_R
[8] PCH_SPI_CLK_R [7] SYS_RESET#

1
RC135 RC136
2K_0402_5% 2K_0402_5%
@ @

2
STRAP PINS SYS_RESET#
1:USE 48MHZ CRYSTAL CLOCK AND
GENERATE BOTH INTERNAL AND EXTERNAL CLOCKS(DEFAULT)
0:USE 100MHZ PCIE CLOCK AS REFERENCE CLOCK AND
PCH_SPI_CLK GENERATE INTERNAL CLOCKS ONLY
C C

1:NORMAL RESET MODE(DEFAULT)

SYS_RESET# 0:SHORT RESET MODE

LPC ROM EMULATOR HEADER

+3VALW_APU +3VS_APU

PIN4 should be removed as a Key

2

RC138 RC139
0_0402_5% 0_0402_5%
DAISY CHAIN ROUTING FOR LPC SIGNALS
LPC@ LPC@
1

B B

APU_LPC_RST# RC140 1 LPC@ 2 0_0402_5%

[8,30] APU_LPC_RST# LPC_RST#_H 1 1 1 2 0_0402_5% PM_SLP_S5#
@ IT1 IT2 @ RC141 @
PM_SLP_S5# [7,30]
LPCRUNPWR 1 @ IT3

RC142 1 LPC@ 2 0_0402_5% I2C3_SCL_LPC 1 @ IT5 IT4 @ 1 I2C3_SDA_LPC RC143 1 LPC@ 2 0_0402_5%
[7,31] TP_I2C3_SCL_R 1 1 SERIRQ TP_I2C3_SDA_R [7,31]
@ IT7 IT6 @
SERIRQ [8,30]
IT8 @ 1 LDRQ0#
LDRQ0# [8]
2 2
CC142 CC143
0.1U_6.3V_K_X5R_0201 0.1U_6.3V_K_X5R_0201
LPC@ 1 1 LPC@

CC142 CC143 should be put on APU side to reduce stub when MP

+3VS_APU

RC144 1 @ 2 10K_0402_5% LPCPD# LPCPD# [8]

RC145 1 @ 2 10K_0402_5% LPC_CLKRUN#

LPC_CLKRUN# [8]

+3VALW_APU

A LPC@ A
RC3272 1 2 10K_0402_5% LPCPD#

RC146 1 2 100K_0402_5% APU_LPC_RST#

CC138 1 2 150P_50V_J_NPO_0402

@ Title
Security Classification LC Future Center Secret Data
Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP5 Straps
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 13 of 45
5 4 3 2 1
 5 4 3 2 1

Note: The memory CLK signal pairs are routed point to point and reference either the VSS plane or the VDDIO_MEM_S3 plane. The CLK termination must match the CLK reference plane
DDR_A_D[0..63]
[5] DDR_A_D[0..63] SA_CLK_DDR#0

8Gb SDP
UD3 UD2 RD122 1 2 39_0402_5% 1 2
DDR_A_DQS#[0..7] SA_CLK_DDR0 RD123 1 2 39_0402_5% CD313
DDR_A_MA0 DDR_A_D38 [5] DDR_A_DQS#[0..7] DDR_A_MA0 DDR_A_D30
P3 G2 P3 G2

16Gb DDP
[5] DDR_A_MA0 DDR_A_MA1 A0 DQL0 DDR_A_D33 DDR_A_DQS[0..7] DDR_A_MA1 A0 DQL0 DDR_A_D28 0.1u_0201_10V6K
P7 F7 P7 F7
[5] DDR_A_MA1 DDR_A_MA2 A1 DQL1 DDR_A_D39 [5] DDR_A_DQS[0..7] DDR_A_MA2 A1 DQL1 DDR_A_D31 +1.2V
R3 H3 R3 H3 1 2 @
[5] DDR_A_MA2 DDR_A_MA3 A2 DQL2 DDR_A_D36 DDR_A_MA3 A2 DQL2 DDR_A_D25
N7 H7 N7 H7
[5] DDR_A_MA3 DDR_A_MA4 A3 DQL3 DDR_A_D34 DDR_A_MA4 A3 DQL3 DDR_A_D26
[5] DDR_A_MA4 N3 H2 N3 H2 CD557 3.3P_50V_C_NPO_0201
DDR_A_MA5 P8 A4 DQL4 H8 DDR_A_D37 DDR_A_MA5 P8 A4 DQL4 H8 DDR_A_D24 DDR_A_ALERT_N RD86 1 2 1/20W_1K_1%_0201
[5] DDR_A_MA5 DDR_A_MA6 A5 DQL5 DDR_A_D35 DDR_A_MA6 A5 DQL5 DDR_A_D27
P2 J3 P2 J3
[5] DDR_A_MA6 DDR_A_MA7 A6 DQL6 DDR_A_D32 DDR_A_MA7 A6 DQL6 DDR_A_D29
R8 J7 R8 J7
[5] DDR_A_MA7 DDR_A_MA8 A7 DQL7 DDR_A_D48 DDR_A_MA8 A7 DQL7 DDR_A_D18
R2 A3 R2 A3
[5] DDR_A_MA8 DDR_A_MA9 A8 DQU0 DDR_A_D50 DDR_A_MA9 A8 DQU0 DDR_A_D16 +0.6VS
[5] DDR_A_MA9 R7 B8 R7 B8 @
DDR_A_MA10 M3 A9 DQU1 C3 DDR_A_D53 DDR_A_MA10 M3 A9 DQU1 C3 DDR_A_D23 DRAM_DDR_A_BG1 RD238 2 1 0_0201_5% DDR_A_BG1
[5] DDR_A_MA10 DDR_A_MA11 A10/AP DQU2 DDR_A_D55 DDR_A_MA11 A10/AP DQU2 DDR_A_D21 DDR_A_BG1 [5]
T2 C7 T2 C7
[5] DDR_A_MA11 DDR_A_MA12 A11 DQU3 DDR_A_D52 DDR_A_MA12 A11 DQU3 DDR_A_D19
M7 C2 M7 C2
[5] DDR_A_MA12 DDR_A_MA13 A12/BC_N DQU4 DDR_A_D51 DDR_A_MA13 A12/BC_N DQU4 DDR_A_D20
T8 C8 T8 C8
[5] DDR_A_MA13 A13 DQU5 A13 DQU5

2
D3 DDR_A_D49 D3 DDR_A_D22
DDR_A_WE# L2 DQU6 D7 DDR_A_D54 DDR_A_WE# L2 DQU6 D7 DDR_A_D17 RD234
[5] DDR_A_WE# DDR_A_CAS# WE_N/A14 DQU7 DDR_A_CAS# WE_N/A14 DQU7
D M8 M8 0_0201_5% D
[5] DDR_A_CAS# DDR_A_RAS# L8 CAS_N/A15 +1.2V DDR_A_RAS# L8 CAS_N/A15 +1.2V DDR_A_CS0# RD51 1 2 1/20W_39_5%_0201
[5] DDR_A_RAS# RAS_N/A16 D1 RAS_N/A16 D1 DDR_A_ODT0 1 2 1/20W_39_5%_0201
RD52 @

1
SA_CLK_DDR#0 K8 VDD1 J1 SA_CLK_DDR#0 K8 VDD1 J1
[5] SA_CLK_DDR#0 SA_CLK_DDR0 CK_C VDD2 SA_CLK_DDR0 CK_C VDD2 DDR_A_CKE0
K7 L1 K7 L1 RD53 1 2 1/20W_39_5%_0201
[5] SA_CLK_DDR0 CK_T VDD3 CK_T VDD3
R1 R1
DDR_A_CKE0 K2 VDD4 B3 DDR_A_CKE0 K2 VDD4 B3 DDR_A_MA0 RD54 1 2 1/20W_39_5%_0201
[5] DDR_A_CKE0 CKE VDD5 CKE VDD5 DDR_A_MA1
G7 G7 RD179 1 2 1/20W_39_5%_0201
DDR_A_DQS#4 F3 VDD6 B9 DDR_A_DQS#3 F3 VDD6 B9 DDR_A_MA2 RD56 1 2 1/20W_39_5%_0201
DDR_A_DQS4 G3 DQSL_C VDD7 J9 DDR_A_DQS3 G3 DQSL_C VDD7 J9 DDR_A_MA3 RD57 1 2 1/20W_39_5%_0201
DDR_A_DQS#6 A7 DQSL_T VDD8 L9 DDR_A_DQS#2 A7 DQSL_T VDD8 L9
DDR_A_DQS6 B7 DQSU_C VDD9 T9 DDR_A_DQS2 B7 DQSU_C VDD9 T9 DDR_A_MA4 RD58 1 2 1/20W_39_5%_0201
DQSU_T VDD10 DQSU_T VDD10 DDR_A_MA5 RD59 1 2 1/20W_39_5%_0201
DDRA_MA_DM6 E2 A1 DDRA_MA_DM2 E2 A1 DDR_A_MA6 RD60 1 2 1/20W_39_5%_0201
[5] DDRA_MA_DM6 DDRA_MA_DM4 NF/UDM_N/UDBI_N VDDQ1 [5] DDRA_MA_DM2 DDRA_MA_DM3 NF/UDM_N/UDBI_N VDDQ1 DDR_A_MA7 UD1_DDR_A_UZQ
E7 C1 E7 C1 RD61 1 2 1/20W_39_5%_0201
[5] DDRA_MA_DM4 NF/LDM_N/LDBI_N VDDQ2 [5] DDRA_MA_DM3 NF/LDM_N/LDBI_N VDDQ2
G1 G1
DDR_A_BA0 N2 VDDQ3 F2 DDR_A_BA0 N2 VDDQ3 F2 DDR_A_MA8 RD62 1 2 1/20W_39_5%_0201
[5] DDR_A_BA0 DDR_A_BA1 BA0 VDDQ4 DDR_A_BA1 BA0 VDDQ4 DDR_A_MA9
N8 J2 N8 J2 RD63 1 2 1/20W_39_5%_0201
[5] DDR_A_BA1 BA1 VDDQ5 BA1 VDDQ5 DDR_A_MA10
F8 F8 RD64 1 2 1/20W_39_5%_0201
DDR_A_ACT_N L3 VDDQ6 J8 DDR_A_ACT_N L3 VDDQ6 J8 DDR_A_MA11 RD67 1 2 1/20W_39_5%_0201 UD2_DDR_A_UZQ
[5] DDR_A_ACT_N DDR_A_CS0# ACT_N VDDQ7 DDR_A_CS0# ACT_N VDDQ7
L7 A9 L7 A9
[5] DDR_A_CS0# DDR_A_ALERT_N CS_N VDDQ8 DDR_A_ALERT_N CS_N VDDQ8 DDR_A_MA12
P9 D9 P9 D9 RD70 1 2 1/20W_39_5%_0201
[5] DDR_A_ALERT_N ALERT_N VDDQ9 G9 +2.5V ALERT_N VDDQ9 G9 +2.5V DDR_A_MA13 1 2 1/20W_39_5%_0201
RD71
DDR_A_BG0 M2 VDDQ10 DDR_A_BG0 M2 VDDQ10 DDR_A_WE# RD72 1 2 1/20W_39_5%_0201
[5] DDR_A_BG0 BG0 BG0 DDR_A_CAS# UD3_DDR_A_UZQ
B1 B1 RD73 1 2 1/20W_39_5%_0201
DDR_A_ODT0 K3 VPP1 R9 DDR_A_ODT0 K3 VPP1 R9
[5] DDR_A_ODT0 ODT VPP2 +VREF_CA_CHA ODT VPP2 +VREF_CA_CHA
DDR_A_PARITY T3 M1 DDR_A_PARITY T3 M1 DDR_A_RAS# RD74 1 2 1/20W_39_5%_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
[5] DDR_A_PARITY PAR VREFCA PAR VREFCA DDR_A_BG0 1 2 1/20W_39_5%_0201
RD75

1000P 25V K X7R 0201

1000P 25V K X7R 0201

1 1 1 1
1 210K_0402_5% TEN_UD3_A N9 E1 1 210K_0402_5% TEN_UD2_A N9 E1 DRAM_DDR_A_BG1 1 2 1/20W_39_5%_0201 UD4_DDR_A_UZQ

CD509

CD233

CD513

CD528
RD94 RD95 RD229

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
TEN VSS1 K1 TEN VSS1 K1 @
VSS2 1 1 VSS2 1 1
DDR4_A_DRAMRST#_R P1 N1 DDR4_A_DRAMRST#_R P1 N1 DDR_A_BA0 1 2 1/20W_39_5%_0201

CD230

CD231

CD335

CD512
RD76
RESET_N VSS3 T1 2 2 RESET_N VSS3 T1 2 2 DDR_A_BA1 1 2 1/20W_39_5%_0201

4700P_25V_K_X7R_0201
RD77
VSS4 VSS4

1
F1 B2 F1 B2

1/20W_240_1%_0201

1/20W_240_1%_0201

1/20W_240_1%_0201

1/20W_240_1%_0201
H1 VSSQ1 VSS5 G8 2 2 H1 VSSQ1 VSS5 G8 2 2 DDR_A_ACT_N 1 2 1/20W_39_5%_0201

RD233

RD232

RD231

RD228
1 1 RD78
CD47 A2 VSSQ2 VSS6 K9 A2 VSSQ2 VSS6 K9 DDR_A_PARITY RD79 1 2 1/20W_39_5%_0201
D2 VSSQ3 VSS8 D2 VSSQ3 VSS8

CD426
RD284 RD285
0.1U_6.3V_K_X5R_0201 E3 VSSQ4 T7 1 2 E3 VSSQ4 T7 1 2

2
2 A8 VSSQ5 VSS7 @ 0_0402_5% 2 A8 VSSQ5 VSS7 @ 0_0402_5%
@ D8 VSSQ6 D8 VSSQ6 @ @ @ @
E8 VSSQ7 M9 DRAM_DDR_A_BG1 E8 VSSQ7 M9 DRAM_DDR_A_BG1
C9 VSSQ8 VSS9 C9 VSSQ8 VSS9
VSSQ9 UD3_DDR_A_UZQ VSSQ9 UD2_DDR_A_UZQ
RD233 RD232 RD231 RD228 will install different
H9 E9 H9 E9
VSSQ10 VSS10 F9 UD3_DDR_A_LZQ VSSQ10 VSS10 F9 UD2_DDR_A_LZQ
ZQ ZQ

value base on SDP or DDP.control by Virtual symbol

1

1
RD39 RD40
K4AAG165WA-BCWE_FBGA96 1/20W_240_1%_0201 K4AAG165WA-BCWE_FBGA96 1/20W_240_1%_0201
@ @
2

2
C C

Layout Note: Place near DRAM

3A@1.5V
+1.2V +1.2V
For layout requir swap UD1 bit 07/25
UD1
UD4 follow SCL 20pcs 0.22uf
DDR_A_MA0 P3 G2 DDR_A_D6
DDR_A_MA1 A0 DQL0 DDR_A_D5 DDR_A_MA0 DDR_A_D59

47P_25V_J_NPO_0201

27P_25V_J_NPO_0201

27P_25V_J_NPO_0201

27P_25V_J_NPO_0201

27P_25V_J_NPO_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201
P7 F7 P3 G2
DDR_A_MA2 R3 A1 DQL1 H3 DDR_A_D3 DDR_A_MA1 P7 A0 DQL0 F7 DDR_A_D57
DDR_A_MA3 A2 DQL2 DDR_A_D4 DDR_A_MA2 A1 DQL1 DDR_A_D63 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

27P_25V_J_NPO_0201

27P_25V_J_NPO_0201

47P_25V_J_NPO_0201

27P_25V_J_NPO_0201

47P_25V_J_NPO_0201

47P_25V_J_NPO_0201

27P_25V_J_NPO_0201
N7 H7 R3 H3 1 CD267 CD542 CD543 CD548 CD547 CD544 CD535 CD545 CD536 CD537 CD546 CD433 CD434 CD453 CD463 CD452 CD454 CD150 CD451 CD461 CD457
DDR_A_MA4 A3 DQL3 DDR_A_D2 DDR_A_MA3 A2 DQL2 DDR_A_D60

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@
N3 H2 N7 H7 CD266
DDR_A_MA5 P8 A4 DQL4 H8 DDR_A_D0 DDR_A_MA4 N3 A3 DQL3 H2 DDR_A_D58 @ @
DDR_A_MA6 A5 DQL5 DDR_A_D7 DDR_A_MA5 A4 DQL4 DDR_A_D61 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 @ 2 2 2 2 2

EMC_NS@
P2 J3 P8 H8
DDR_A_MA7 R8 A6 DQL6 J7 DDR_A_D1 DDR_A_MA6 P2 A5 DQL5 J3 DDR_A_D62 2
DDR_A_MA8 R2 A7 DQL7 A3 DDR_A_D13 DDR_A_MA7 R8 A6 DQL6 J7 DDR_A_D56
DDR_A_MA9 R7 A8 DQU0 B8 DDR_A_D12 DDR_A_MA8 R2 A7 DQL7 A3 DDR_A_D41
DDR_A_MA10 M3 A9 DQU1 C3 DDR_A_D8 DDR_A_MA9 R7 A8 DQU0 B8 DDR_A_D40 @
DDR_A_MA11 T2 A10/AP DQU2 C7 DDR_A_D10 DDR_A_MA10 M3 A9 DQU1 C3 DDR_A_D46
DDR_A_MA12 A11 DQU3 DDR_A_D11 DDR_A_MA11 A10/AP DQU2 DDR_A_D44
3A@1.5V
M7 C2 T2 C7
DDR_A_MA13 T8 A12/BC_N DQU4 C8 DDR_A_D9 DDR_A_MA12 M7 A11 DQU3 C2 DDR_A_D47
A13 DQU5 D3 DDR_A_D15 DDR_A_MA13 T8 A12/BC_N DQU4 C8 DDR_A_D45 +1.2V
DDR_A_WE# L2 DQU6 D7 DDR_A_D14 A13 DQU5 D3 DDR_A_D43
DDR_A_CAS# M8 WE_N/A14 DQU7 DDR_A_WE# L2 DQU6 D7 DDR_A_D42
DDR_A_RAS# L8 CAS_N/A15 +1.2V DDR_A_CAS# M8 WE_N/A14 DQU7
RAS_N/A16 D1 DDR_A_RAS# L8 CAS_N/A15 +1.2V
SA_CLK_DDR#0 VDD1 RAS_N/A16 +1.2V +0.6VS +2.5V

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201
K8 J1 D1
SA_CLK_DDR0 K7 CK_C VDD2 L1 SA_CLK_DDR#0 K8 VDD1 J1
CK_T VDD3 SA_CLK_DDR0 CK_C VDD2 1 1 1 1 1 1 1 1 1 1
R1 K7 L1 CD438 CD437 CD458 CD456 CD460 CD436 CD435 CD439 CD455 CD317
DDR_A_CKE0 K2 VDD4 B3 CK_T VDD3 R1
CKE VDD5 G7 DDR_A_CKE0 K2 VDD4 B3
DDR_A_DQS#0 F3 VDD6 B9 CKE VDD5 G7 2 2 2 2 2 2 2 2 2 2

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

DDR_A_DQS0 G3 DQSL_C VDD7 J9 DDR_A_DQS#7 F3 VDD6 B9
DQSL_T VDD8 DQSL_C VDD7 1 1 1 1 1 1 1 1
DDR_A_DQS#1 DDR_A_DQS7

CD559

CD560

CD561

CD562

CD563

CD564

CD565

CD566
A7 L9 G3 J9
DDR_A_DQS1 B7 DQSU_C VDD9 T9 DDR_A_DQS#5 A7 DQSL_T VDD8 L9
DQSU_T VDD10 DDR_A_DQS5 B7 DQSU_C VDD9 T9 @ @
DDRA_MA_DM1 E2 A1 DQSU_T VDD10 2 2 2 2 2 2 2 2
[5] DDRA_MA_DM1 DDRA_MA_DM0 NF/UDM_N/UDBI_N VDDQ1 DDRA_MA_DM5 +1.2V
E7 C1 E2 A1
[5] DDRA_MA_DM0 NF/LDM_N/LDBI_N VDDQ2 [5] DDRA_MA_DM5 DDRA_MA_DM7 NF/UDM_N/UDBI_N VDDQ1 +1.2V
G1 [5] DDRA_MA_DM7 E7 C1
DDR_A_BA0 N2 VDDQ3 F2 NF/LDM_N/LDBI_N VDDQ2 G1 @ @
BA0 VDDQ4 VDDQ3 @
B DDR_A_BA1 N8 J2 DDR_A_BA0 N2 F2 B
BA1 VDDQ5 F8 DDR_A_BA1 N8 BA0 VDDQ4 J2
DDR_A_ACT_N VDDQ6 BA1 VDDQ5

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201
L3 J8 F8
DDR_A_CS0# L7 ACT_N VDDQ7 A9 DDR_A_ACT_N L3 VDDQ6 J8
CS_N VDDQ8 ACT_N VDDQ7 1 1 1 1
DDR_A_ALERT_N P9 D9 DDR_A_CS0# L7 A9 CD444 CD443 CD442 CD441
ALERT_N VDDQ9 +2.5V DDR_A_ALERT_N CS_N VDDQ8 1 1
G9 P9 D9
DDR_A_BG0 M2 VDDQ10 ALERT_N VDDQ9 G9 +2.5V @ @ @ CD323 CD153
BG0 B1 DDR_A_BG0 M2 VDDQ10 2 2 2 2 22P_50V_J_NPO_0402 22P_50V_J_NPO_0402
DDR_A_ODT0 K3 VPP1 R9 BG0 B1 2 2
ODT VPP2 +VREF_CA_CHA DDR_A_ODT0 K3 VPP1 R9 RF_NS@ RF_NS@
DDR_A_PARITY T3 M1 ODT VPP2 +VREF_CA_CHA
1U_6.3V_K_X5R_0201
0.1U_6.3V_K_X5R_0201

RD96 PAR VREFCA DDR_A_PARITY T3 M1

1U_6.3V_K_X5R_0201
0.1U_6.3V_K_X5R_0201
1000P 25V K X7R 0201

TEN_UD1_A 1 1 PAR VREFCA

1 2 N9 E1
CD515

CD529
0.1U_6.3V_K_X5R_0201

1000P 25V K X7R 0201

TEN VSS1 TEN_UD4_A 1 1

CD517

CD530
10K_0201_5% K1 RD97 1 210K_0402_5% N9 E1

0.1U_6.3V_K_X5R_0201
VSS2 1 1 TEN VSS1
DDR4_A_DRAMRST#_R P1 N1 K1
CD339

CD514

RESET_N VSS3 VSS2 1 1

T1 2 2 DDR4_A_DRAMRST#_R P1 N1 +0.6VS

CD343

CD516
0.1U_6.3V_K_X5R_0201

F1 VSS4 B2 RESET_N VSS3 T1 2 2

VSSQ1 VSS5 2 2 VSS4 +1.2V RF Requirement
H1 G8 F1 B2
follow SCL 10pcs 0.22uf
0.1U_6.3V_K_X5R_0201

1 VSSQ2 VSS6 VSSQ1 VSS5 2 2

CD427

A2 K9 H1 G8
D2 VSSQ3 VSS8 RD287 A2 VSSQ2 VSS6 K9
VSSQ4 1 VSSQ3 VSS8

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201
E3 T7 1 2 D2
CD428

RD286
2 A8 VSSQ5 VSS7 @ 0_0402_5% E3 VSSQ4 T7 1 2
@ VSSQ6 VSSQ5 VSS7 1 1 1 1 1 1 1 1 1 1
D8 A8 @ 0_0402_5% CD327 CD462 CD459 CD464 CD440 CD447 CD448 CD446 CD445 CD242
E8 VSSQ7 M9 DRAM_DDR_A_BG1 2 D8 VSSQ6
C9 VSSQ8 VSS9 @ E8 VSSQ7 M9 DRAM_DDR_A_BG1 @ @

12P_50V_J_NPO_0201

12P_50V_J_NPO_0201

12P_50V_J_NPO_0201

12P_50V_J_NPO_0201

2.2P_25V_C_COG_0201

2.2P_25V_C_COG_0201

2.2P_25V_C_COG_0201

2.2P_25V_C_COG_0201
VSSQ9 VSSQ8 VSS9 1 1 1 1 1 1 1 1
H9 E9 UD1_DDR_A_UZQ C9 2 2 @ 2 2 2 2 2 2 2 2

RF_NS@ CD50

RF_NS@ CD51

RF_NS@ CD52

RF_NS@ CD53

RF_NS@ CD60

RF_NS@ CD61

RF_NS@ CD62

RF_NS@ CD63
VSSQ10 VSS10 F9 UD1_DDR_A_LZQ H9 VSSQ9 E9 UD4_DDR_A_UZQ
ZQ VSSQ10 VSS10 F9 UD4_DDR_A_LZQ
ZQ
1

2 2 2 2 2 2 2 2
1

RD43 @
K4AAG165WA-BCWE_FBGA96 1/20W_240_1%_0201 RD44
@ K4AAG165WA-BCWE_FBGA96 1/20W_240_1%_0201
+0.6VS +0.6VS +2.5V
@
2

180P_50V_J_NPO_0402
0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201
1 1

CD558
DDR4_A_DRAMRST# 1 1 1 1
RD288 1 2 0_0402_5% DDR4_A_DRAMRST#_R CD450 CD449 CD503
[5] DDR4_A_DRAMRST#
CD501 CD502 22P_50V_F_COG_0201
22P_50V_F_COG_0201 22P_50V_F_COG_0201 2 2
2 2 2 2 RF_NS@
+1.2V RF_NS@ RF_NS@
1
0.1U_6.3V_K_X5R_0201

1 RD10
CD315 1K_0402_1% +VREF_CA_CHA

15mil
A A
2

2
1000P 25V K X7R 0201
1

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
1K_0402_1%

1 1 1
RD11

CD510

CD511

CD117

@ @
2

@2 2 2

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 DDRIV SO-DIMM A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 14 of 45
5 4 3 2 1
 5 4 3 2 1

DDR_B_D[0..63] CD370

8Gb SDP UD7

[5] DDR_B_D[0..63]
DDR_B_DQS#[0..7]
UD6 SB_CLK_DDR#0
SB_CLK_DDR0
RD243
RD263
1
1
2 39_0402_5%
2 39_0402_5%
1 2

16Gb DDP DDR_B_MA0 DDR_B_D38 [5] DDR_B_DQS#[0..7] DDR_B_MA0 DDR_B_D17

[5] DDR_B_MA0 P3 G2 P3 G2
DDR_B_MA1 P7 A0 DQL0 F7 DDR_B_D37 DDR_B_DQS[0..7] DDR_B_MA1 P7 A0 DQL0 F7 DDR_B_D21 Note: CLK termination must match the CLK reference plane. 0.1u_0201_10V6K
[5] DDR_B_MA1 DDR_B_MA2 A1 DQL1 DDR_B_D35 [5] DDR_B_DQS[0..7] DDR_B_MA2 A1 DQL1 DDR_B_D23 +1.2V
R3 H3 R3 H3 1 2
[5] DDR_B_MA2 DDR_B_MA3 A2 DQL2 DDR_B_D33 DDR_B_MA3 A2 DQL2 DDR_B_D19
N7 H7 N7 H7 CD567 @
[5] DDR_B_MA3 DDR_B_MA4 A3 DQL3 DDR_B_D39 DDR_B_MA4 A3 DQL3 DDR_B_D18
N3 H2 N3 H2 3.3P_50V_C_NPO_0201
[5] DDR_B_MA4 DDR_B_MA5 A4 DQL4 DDR_B_D36 DDR_B_MA5 A4 DQL4 DDR_B_D20 DDR_B_ALERT_N
[5] DDR_B_MA5 P8 H8 P8 H8 RD279 1 2 1/20W_1K_1%_0201
DDR_B_MA6 P2 A5 DQL5 J3 DDR_B_D34 DDR_B_MA6 P2 A5 DQL5 J3 DDR_B_D16
[5] DDR_B_MA6 DDR_B_MA7 A6 DQL6 DDR_B_D32 DDR_B_MA7 A6 DQL6 DDR_B_D22
R8 J7 R8 J7
[5] DDR_B_MA7 DDR_B_MA8 A7 DQL7 DDR_B_D42 DDR_B_MA8 A7 DQL7 DDR_B_D31
R2 A3 R2 A3
[5] DDR_B_MA8 DDR_B_MA9 A8 DQU0 DDR_B_D44 DDR_B_MA9 A8 DQU0 DDR_B_D24 +0.6VS
R7 B8 R7 B8 @
[5] DDR_B_MA9 DDR_B_MA10 A9 DQU1 DDR_B_D46 DDR_B_MA10 A9 DQU1 DDR_B_D27 DRAM_DDR_B_BG1 DDR_B_BG1
[5] DDR_B_MA10 M3 C3 M3 C3 RD257 2 1 0_0201_5% DDR_B_BG1 [5]
DDR_B_MA11 T2 A10/AP DQU2 C7 DDR_B_D41 DDR_B_MA11 T2 A10/AP DQU2 C7 DDR_B_D28
[5] DDR_B_MA11 DDR_B_MA12 A11 DQU3 DDR_B_D43 DDR_B_MA12 A11 DQU3 DDR_B_D26
M7 C2 M7 C2
[5] DDR_B_MA12 DDR_B_MA13 A12/BC_N DQU4 DDR_B_D40 DDR_B_MA13 A12/BC_N DQU4 DDR_B_D29
T8 C8 T8 C8 For layout requir swap UD6 bit 07/25
[5] DDR_B_MA13

2
A13 DQU5 D3 DDR_B_D47 A13 DQU5 D3 DDR_B_D30
DDR_B_WE# L2 DQU6 D7 DDR_B_D45 DDR_B_WE# L2 DQU6 D7 DDR_B_D25 RD275
[5] DDR_B_WE# DDR_B_CAS# WE_N/A14 DQU7 DDR_B_CAS# WE_N/A14 DQU7
M8 M8 0_0201_5%
D [5] DDR_B_CAS# DDR_B_RAS# L8 CAS_N/A15 +1.2V DDR_B_RAS# L8 CAS_N/A15 +1.2V DDR_B_CS0# 1 2 1/20W_39_5%_0201 D
RD247
[5] DDR_B_RAS# RAS_N/A16 D1 RAS_N/A16 D1 DDR_B_ODT0 RD259 1 2 1/20W_39_5%_0201 @

1
SB_CLK_DDR#0 K8 VDD1 J1 SB_CLK_DDR#0 K8 VDD1 J1
[5] SB_CLK_DDR#0 SB_CLK_DDR0 CK_C VDD2 SB_CLK_DDR0 CK_C VDD2 DDR_B_CKE0
[5] SB_CLK_DDR0 K7 L1 K7 L1 RD283 1 2 1/20W_39_5%_0201
CK_T VDD3 R1 CK_T VDD3 R1
DDR_B_CKE0 K2 VDD4 B3 DDR_B_CKE0 K2 VDD4 B3 DDR_B_MA0 RD258 1 2 1/20W_39_5%_0201
[5] DDR_B_CKE0 CKE VDD5 CKE VDD5 DDR_B_MA1
G7 G7 RD278 1 2 1/20W_39_5%_0201
DDR_B_DQS#4 F3 VDD6 B9 DDR_B_DQS#2 F3 VDD6 B9 DDR_B_MA2 RD274 1 2 1/20W_39_5%_0201
DDR_B_DQS4 G3 DQSL_C VDD7 J9 DDR_B_DQS2 G3 DQSL_C VDD7 J9 DDR_B_MA3 RD273 1 2 1/20W_39_5%_0201
DDR_B_DQS#5 A7 DQSL_T VDD8 L9 DDR_B_DQS#3 A7 DQSL_T VDD8 L9
DDR_B_DQS5 B7 DQSU_C VDD9 T9 DDR_B_DQS3 B7 DQSU_C VDD9 T9 DDR_B_MA4 RD241 1 2 1/20W_39_5%_0201
DQSU_T VDD10 DQSU_T VDD10 DDR_B_MA5 RD248 1 2 1/20W_39_5%_0201
DDRA_MB_DM5 E2 A1 DDRA_MB_DM3 E2 A1 DDR_B_MA6 RD262 1 2 1/20W_39_5%_0201
[5] DDRA_MB_DM5 DDRA_MB_DM4 NF/UDM_N/UDBI_N VDDQ1 [5] DDRA_MB_DM3 DDRA_MB_DM2 NF/UDM_N/UDBI_N VDDQ1 DDR_B_MA7 UD5_DDR_B_UZQ
[5] DDRA_MB_DM4 E7 C1 [5] DDRA_MB_DM2 E7 C1 RD267 1 2 1/20W_39_5%_0201
NF/LDM_N/LDBI_N VDDQ2 G1 NF/LDM_N/LDBI_N VDDQ2 G1
DDR_B_BA0 N2 VDDQ3 F2 DDR_B_BA0 N2 VDDQ3 F2 DDR_B_MA8 RD282 1 2 1/20W_39_5%_0201
[5] DDR_B_BA0 DDR_B_BA1 BA0 VDDQ4 DDR_B_BA1 BA0 VDDQ4 DDR_B_MA9
N8 J2 N8 J2 RD277 1 2 1/20W_39_5%_0201
[5] DDR_B_BA1 BA1 VDDQ5 BA1 VDDQ5 DDR_B_MA10
F8 F8 RD250 1 2 1/20W_39_5%_0201
DDR_B_ACT_N L3 VDDQ6 J8 DDR_B_ACT_N L3 VDDQ6 J8 DDR_B_MA11 RD270 1 2 1/20W_39_5%_0201 UD6_DDR_B_UZQ
[5] DDR_B_ACT_N DDR_B_CS0# ACT_N VDDQ7 DDR_B_CS0# ACT_N VDDQ7
L7 A9 L7 A9
[5] DDR_B_CS0# DDR_B_ALERT_N P9 CS_N VDDQ8 D9 DDR_B_ALERT_N P9 CS_N VDDQ8 D9 DDR_B_MA12 1 2 1/20W_39_5%_0201
RD256
[5] DDR_B_ALERT_N ALERT_N VDDQ9 +2.5V ALERT_N VDDQ9 +2.5V DDR_B_MA13
G9 G9 RD252 1 2 1/20W_39_5%_0201
DDR_B_BG0 M2 VDDQ10 DDR_B_BG0 M2 VDDQ10 DDR_B_WE# RD253 1 2 1/20W_39_5%_0201
[5] DDR_B_BG0 BG0 BG0 DDR_B_CAS# UD7_DDR_B_UZQ
B1 B1 RD271 1 2 1/20W_39_5%_0201
DDR_B_ODT0 K3 VPP1 R9 DDR_B_ODT0 K3 VPP1 R9
[5] DDR_B_ODT0 ODT VPP2 +VREF_CA_CHB ODT VPP2 +VREF_CA_CHB
DDR_B_PARITY T3 M1 DDR_B_PARITY T3 M1 DDR_B_RAS# RD244 1 2 1/20W_39_5%_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
[5] DDR_B_PARITY PAR VREFCA PAR VREFCA DDR_B_BG0 1 2 1/20W_39_5%_0201
RD240

1000P 25V K X7R 0201

1000P 25V K X7R 0201

TEN_UD7_B 1 1 TEN_UD6_B 1 1 DRAM_DDR_B_BG1 UD8_DDR_B_UZQ

CD521

CD534

CD518

CD532
RD269 1 210K_0402_5% N9 E1 RD276 1 210K_0402_5% N9 E1 RD266 1 2 1/20W_39_5%_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
TEN VSS1 K1 TEN VSS1 K1 @
VSS2 1 1 VSS2 1 1
DDR4_B_DRAMRST#_R P1 N1 DDR4_B_DRAMRST#_R P1 N1 DDR_B_BA0 1 2 1/20W_39_5%_0201

CD415

CD525

CD349

CD523
RD264
RESET_N VSS3 T1 2 2 RESET_N VSS3 T1 2 2 DDR_B_BA1 RD281 1 2 1/20W_39_5%_0201
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

1
F1 VSS4 B2 F1 VSS4 B2

1/20W_240_1%_0201

1/20W_240_1%_0201

1/20W_240_1%_0201

1/20W_240_1%_0201
VSSQ1 VSS5 2 2 VSSQ1 VSS5 2 2 DDR_B_ACT_N

@ RD249

@ RD265

@ RD239

@ RD280
1 H1 G8 1 H1 G8 RD251 1 2 1/20W_39_5%_0201
A2 VSSQ2 VSS6 K9 A2 VSSQ2 VSS6 K9 DDR_B_PARITY 1 2 1/20W_39_5%_0201
CD431

CD432
RD260
D2 VSSQ3 VSS8 RD289 D2 VSSQ3 VSS8 RD290
E3 VSSQ4 T7 1 2 E3 VSSQ4 T7 1 2

2
2 A8 VSSQ5 VSS7 @ 0_0402_5% 2 A8 VSSQ5 VSS7 @ 0_0402_5%
@ D8 VSSQ6 @ D8 VSSQ6
E8 VSSQ7 M9 DRAM_DDR_B_BG1 E8 VSSQ7 M9 DRAM_DDR_B_BG1
C9 VSSQ8 VSS9 C9 VSSQ8 VSS9
VSSQ9 UD7_DDR_B_UZQ VSSQ9 UD6_DDR_B_UZQ
RD249 RD265 RD239 RD280 will install different
H9 E9 H9 E9
VSSQ10 VSS10 F9 UD7_DDR_B_LZQ VSSQ10 VSS10 F9 UD6_DDR_B_LZQ
ZQ ZQ

value base on SDP or DDP.control by Virtual symbol

1

1
RD245 RD255
K4AAG165WA-BCWE_FBGA96 K4AAG165WA-BCWE_FBGA96 1/20W_240_1%_0201
@ 1/20W_240_1%_0201 @
2

2
C +1.2V C

Layout Note: Place near DRAM

1 1 1 1 1 1 1 1 1 1 1 1 3A@1.5V

47P_25V_J_NPO_0201

27P_25V_J_NPO_0201

27P_25V_J_NPO_0201

27P_25V_J_NPO_0201

27P_25V_J_NPO_0201

27P_25V_J_NPO_0201

27P_25V_J_NPO_0201

47P_25V_J_NPO_0201

27P_25V_J_NPO_0201

47P_25V_J_NPO_0201

47P_25V_J_NPO_0201

27P_25V_J_NPO_0201
CD540 CD553 CD554 CD549 CD555 CD556 CD552 CD538 CD551 CD541 CD539 CD550
+1.2V

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@
2 2 2 2 2 2 2 2 2 2 2 2
follow SCL 20pcs 0.22uf

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201
UD5 1 1 1 1 1 1 1 1 1 1
UD8 CD486 CD496 CD476 CD472 CD489 CD474 CD485 CD493 CD482 CD497
DDR_B_MA0 P3 G2 DDR_B_D6
DDR_B_MA1 P7 A0 DQL0 F7 DDR_B_D5 DDR_B_MA0 P3 G2 DDR_B_D51
DDR_B_MA2 R3 A1 DQL1 H3 DDR_B_D7 DDR_B_MA1 P7 A0 DQL0 F7 DDR_B_D48 2 2 2 2 2 2 2 2 2 2
DDR_B_MA3 N7 A2 DQL2 H7 DDR_B_D0 DDR_B_MA2 R3 A1 DQL1 H3 DDR_B_D54
DDR_B_MA4 N3 A3 DQL3 H2 DDR_B_D2 DDR_B_MA3 N7 A2 DQL2 H7 DDR_B_D49
DDR_B_MA5 P8 A4 DQL4 H8 DDR_B_D1 DDR_B_MA4 N3 A3 DQL3 H2 DDR_B_D50
DDR_B_MA6 P2 A5 DQL5 J3 DDR_B_D3 DDR_B_MA5 P8 A4 DQL4 H8 DDR_B_D52
DDR_B_MA7 R8 A6 DQL6 J7 DDR_B_D4 DDR_B_MA6 P2 A5 DQL5 J3 DDR_B_D55
DDR_B_MA8 A7 DQL7 DDR_B_D11 DDR_B_MA7 A6 DQL6 DDR_B_D53
3A@1.5V @
R2 A3 R8 J7
DDR_B_MA9 R7 A8 DQU0 B8 DDR_B_D13 DDR_B_MA8 R2 A7 DQL7 A3 DDR_B_D59
DDR_B_MA10 M3 A9 DQU1 C3 DDR_B_D15 DDR_B_MA9 R7 A8 DQU0 B8 DDR_B_D56 +1.2V
DDR_B_MA11 T2 A10/AP DQU2 C7 DDR_B_D8 DDR_B_MA10 M3 A9 DQU1 C3 DDR_B_D62
DDR_B_MA12 M7 A11 DQU3 C2 DDR_B_D10 DDR_B_MA11 T2 A10/AP DQU2 C7 DDR_B_D60
DDR_B_MA13 T8 A12/BC_N DQU4 C8 DDR_B_D12 DDR_B_MA12 M7 A11 DQU3 C2 DDR_B_D63
A13 DQU5 D3 DDR_B_D14 DDR_B_MA13 T8 A12/BC_N DQU4 C8 DDR_B_D61 +1.2V +0.6VS +2.5V
DDR_B_WE# DQU6 DDR_B_D9 A13 DQU5 DDR_B_D58

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201
L2 D7 D3
DDR_B_CAS# M8 WE_N/A14 DQU7 DDR_B_WE# L2 DQU6 D7 DDR_B_D57
DDR_B_RAS# CAS_N/A15 +1.2V DDR_B_CAS# WE_N/A14 DQU7 1 1 1 1 1 1 1 1 1 1
L8 M8 CD490 CD466 CD481 CD499 CD479 CD487 CD471 CD478 CD495 CD498
RAS_N/A16 D1 DDR_B_RAS# L8 CAS_N/A15 +1.2V
SB_CLK_DDR#0 K8 VDD1 J1 RAS_N/A16 D1

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

SB_CLK_DDR0 K7 CK_C VDD2 L1 SB_CLK_DDR#0 K8 VDD1 J1 2 2 2 2 2 @ 2 2 2 2 2
CK_T VDD3 CK_C VDD2 1 1 1 1 1 1 1 1
R1 SB_CLK_DDR0 K7 L1

CD569

CD570

CD571

CD572

CD573

CD574

CD575

CD576
DDR_B_CKE0 K2 VDD4 B3 CK_T VDD3 R1
CKE VDD5 G7 DDR_B_CKE0 K2 VDD4 B3 @ @
DDR_B_DQS#0 F3 VDD6 B9 CKE VDD5 G7 2 2 2 2 2 2 2 2
DDR_B_DQS0 G3 DQSL_C VDD7 J9 DDR_B_DQS#6 F3 VDD6 B9 @
DDR_B_DQS#1 A7 DQSL_T VDD8 L9 DDR_B_DQS6 G3 DQSL_C VDD7 J9 +1.2V @ @
DDR_B_DQS1 B7 DQSU_C VDD9 T9 DDR_B_DQS#7 A7 DQSL_T VDD8 L9 +1.2V
DQSU_T VDD10 DDR_B_DQS7 B7 DQSU_C VDD9 T9
DDRA_MB_DM1 E2 A1 DQSU_T VDD10
[5] DDRA_MB_DM1 DDRA_MB_DM0 NF/UDM_N/UDBI_N VDDQ1 DDRA_MB_DM7
E7 C1 E2 A1
[5] DDRA_MB_DM0 NF/LDM_N/LDBI_N VDDQ2 [5] DDRA_MB_DM7 DDRA_MB_DM6 NF/UDM_N/UDBI_N VDDQ1

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201
G1 E7 C1
DDR_B_BA0 VDDQ3 [5] DDRA_MB_DM6 NF/LDM_N/LDBI_N VDDQ2
N2 F2 G1 1 1 1 1
DDR_B_BA1 N8 BA0 VDDQ4 J2 DDR_B_BA0 N2 VDDQ3 F2 CD467 CD468 CD469 CD470
BA1 VDDQ5 DDR_B_BA1 BA0 VDDQ4 1 1
B F8 N8 J2 B
DDR_B_ACT_N L3 VDDQ6 J8 BA1 VDDQ5 F8 CD506 CD504
DDR_B_CS0# ACT_N VDDQ7 DDR_B_ACT_N VDDQ6 2 2 2 2

@
L7 A9 L3 J8 22P_50V_J_NPO_0402 22P_50V_J_NPO_0402
DDR_B_ALERT_N P9 CS_N VDDQ8 D9 DDR_B_CS0# L7 ACT_N VDDQ7 A9 2 2
ALERT_N VDDQ9 G9 +2.5V DDR_B_ALERT_N P9 CS_N VDDQ8 D9 RF_NS@ RF_NS@
DDR_B_BG0 M2 VDDQ10 ALERT_N VDDQ9 G9 +2.5V
BG0 B1 DDR_B_BG0 M2 VDDQ10
DDR_B_ODT0 K3 VPP1 R9 BG0 B1
ODT VPP2 +VREF_CA_CHB DDR_B_ODT0 K3 VPP1 R9
DDR_B_PARITY T3 M1 ODT VPP2 +VREF_CA_CHB
1U_6.3V_K_X5R_0201
0.1U_6.3V_K_X5R_0201

PAR VREFCA DDR_B_PARITY T3 M1 +0.6VS

1U_6.3V_K_X5R_0201
0.1U_6.3V_K_X5R_0201
1000P 25V K X7R 0201

TEN_UD5_B 1 1 PAR VREFCA

1 210K_0402_5% N9 E1
CD527

CD533

RD272
0.1U_6.3V_K_X5R_0201

1000P 25V K X7R 0201

TEN VSS1 TEN_UD8_B 1 1
K1 1 210K_0402_5% N9 E1
follow SCL 10pcs 0.22uf

CD520

CD531
RD242

0.1U_6.3V_K_X5R_0201
DDR4_B_DRAMRST#_R P1 VSS2 1 1 TEN VSS1 RF Requirement
CD418

CD519

N1 K1 1 1
RESET_N VSS3 T1 2 2 DDR4_B_DRAMRST#_R P1 VSS2 N1 +1.2V

CD400

CD526
0.1U_6.3V_K_X5R_0201

VSS4 RESET_N VSS3 2 2

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201
F1 B2 T1
4700P_25V_K_X7R_0201

H1 VSSQ1 VSS5 G8 2 2 F1 VSS4 B2

1 VSSQ2 VSS6 VSSQ1 VSS5 2 2 1 1 1 1 1 1 1 1 1 1
A2 K9 H1 G8
CD429

1 CD492 CD488 CD465 CD473 CD477 CD480 CD500 CD475 CD491 CD494
D2 VSSQ3 VSS8 RD292 A2 VSSQ2 VSS6 K9
E3 VSSQ4 T7 1 2 D2 VSSQ3 VSS8
CD430

RD291
2 A8 VSSQ5 VSS7 @ 0_0402_5% E3 VSSQ4 T7 1 2 2 2 2 2 2 2 2 2 2 2
@ VSSQ6 2 VSSQ5 VSS7
D8 A8 @ 0_0402_5%

12P_50V_J_NPO_0201

12P_50V_J_NPO_0201

12P_50V_J_NPO_0201

12P_50V_J_NPO_0201

2.2P_25V_C_COG_0201

2.2P_25V_C_COG_0201

2.2P_25V_C_COG_0201

2.2P_25V_C_COG_0201
VSSQ7 DRAM_DDR_B_BG1 VSSQ6 1 1 1 1 1 1 1 1
E8 M9 D8

RF_NS@ CD54

RF_NS@ CD55

RF_NS@ CD56

RF_NS@ CD57

RF_NS@ CD64

RF_NS@ CD65

RF_NS@ CD66

RF_NS@ CD67
C9 VSSQ8 VSS9 E8 VSSQ7 M9 DRAM_DDR_B_BG1
H9 VSSQ9 E9 UD5_DDR_B_UZQ C9 VSSQ8 VSS9 @ @
VSSQ10 VSS10 F9 UD5_DDR_B_LZQ H9 VSSQ9 E9 UD8_DDR_B_UZQ 2 2 2 2 2 2 2 2
ZQ VSSQ10 VSS10 F9 UD8_DDR_B_LZQ @
1

ZQ +0.6VS +0.6VS +2.5V

1

RD254
K4AAG165WA-BCWE_FBGA96 1/20W_240_1%_0201 RD261
@ K4AAG165WA-BCWE_FBGA96 1/20W_240_1%_0201

180P_50V_J_NPO_0402
@
2

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201
1 1
2

CD568
1 1 1 1
CD483 CD484 CD507
CD508 CD505 22P_50V_F_COG_0201
22P_50V_F_COG_0201 22P_50V_F_COG_0201 2 2
2 2 2 2 RF_NS@
DDR4_B_DRAMRST# RF_NS@ RF_NS@
RD502 1 2 0_0402_5% DDR4_B_DRAMRST#_R
[5] DDR4_B_DRAMRST#

+1.2V
@
0.1U_6.3V_K_X5R_0201

1
CD357 RD268
+VREF_CA_CHB
1K_0402_1%
2
15mil
2

A A
1

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

1000P 25V K X7R 0201

1 1 1
CD522

CD524

CD412

RD246

1K_0402_1% @ @ @
2

2 2 2

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 DDRVI MD
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 15 of 45
5 4 3 2 1
 5 4 3 2 1

+3VS +LCDVDD
LCD POWER CIRCUIT Touch Srceen Power control,
Remove MS Power coontrol 0727
UG5
5
IN OUT
1
DICM BOARD POWER +3VALW TO +3VS_TS
2 +3VS_CAMERA +3VS INRUSCH 1.1A ACTIVE 0.2A +3VS_TS
GND +3VS
1 RI18 FI1 RG49
4 3 W=40mils
[6] PCH_ENVDD EN OCB
@ CG1 1 2 1/10W_0_5%_0603
1 2 1 2 1/10W_0_5%_0603
0.1U_6.3V_K_X5R_0201 SY6288C20AAC_SOT23-5
2

10U 6.3V M X5R 0402

0.1U_6.3V_K_X5R_0201
1 1A_32V_ERBRD1R00X 1 1
@ CI12 CI13 CI14

0.1U_6.3V_K_X5R_0201
0.1U_6.3V_K_X5R_0201 @ @
D 2 2 2 D
Touch Srceen Power control, 1
+LCDVDD +LCDVDD_CON Remove MS Power coontrol 0726
CG46
2

1 CG8 1 CG9 1 CG10

10U 6.3V M X5R 0402

0.1U_6.3V_K_X5R_0201

@ 33P_50V_J_NPO_0201
RF_NS@

2 2 2

+3VS_TS

JTS
1
Change Touch screen 2 1
2
from USB2.0 to I2C APU_TS_RST RG60 1 2 0_0402_5% 3
LED POWER Jevon@190613
[8]
[7]
APU_TS_RST
APU_TS_INT#
APU_TS_INT# RG61
APU_TS_STOP RG62
1
1
2 0_0402_5%
2 0_0402_5%
4
5
3
4
B+ +LEDVDD [30] APU_TS_STOP 5
6
RG6 TS_I2C2_SDA 6
FG2 7
1 2 1/10W_0_5%_0603
1 2 TOUCH SCREEN TS_I2C2_SCL 8
9
7
8
3A_32V_ERBRD3R00X 10 9
11 10
2 1 1 GND1
CG5 CG6 12

100P 25V J NPO 0201

100P 25V J NPO 0201

@ CG11 10U_0805_25V6K 0.1U_25V_K_X5R_0201 GND2

EMC_NS@

EMC_NS@
C 1 1 C
0.1U_25V_K_X5R_0201 HIGHS_WS83100-S0171-HF
1 2 2 TS_I2C2_SDA_RRG46 1 2 0_0402_5% TS_I2C2_SDA
[7] TS_I2C2_SDA_R ME@
2 2

CI33

CI34
TS_I2C2_SCL_R RG47 1 2 0_0402_5% TS_I2C2_SCL
[7] TS_I2C2_SCL_R

Camera
RI19 1 2 0_0402_5%

LI1 EMC_NS@
USB20_N2 4 3 USB20_N_CAMERA
[9] USB20_N2 4 3

USB20_P2 1 2 USB20_P_CAMERA
[9] USB20_P2 1 2
+3VS RG54 1 2 0_0402_5% +DMIC_PWR
EXC24CH900U_4P
+1.8VS RG55 1 2 0_0402_5%
B B
@
RI20 1 2 0_0402_5% JEDP

+LEDVDD 1
2 1
3 2
4 3
5 4
DISPOFF# 6 5
7 6
+LCDVDD_CON 7
8
INVT_PWM 9 8
APU_EDP_HPD 10 9
+3VS [6] APU_EDP_HPD 10
11
CG12 2 1 0.1U_6.3V_K_X5R_0201 EDP_AUX 12 11
[6] APU_EDP_AUX 12
CG13 2 1 0.1U_6.3V_K_X5R_0201 EDP_AUX# 13
[6] APU_EDP_AUX# 13
2

14
RG3 CG14 2 1 0.1U_6.3V_K_X5R_0201 EDP_TX0+ 15 14
+3VS [6] APU_EDP_TX0+ 15
4.7K_0402_5% CG15 2 1 0.1U_6.3V_K_X5R_0201 EDP_TX0- 16
[6] APU_EDP_TX0- 16
@ 17
CG16 2 1 0.1U_6.3V_K_X5R_0201 EDP_TX1+ 18 17
[6] APU_EDP_TX1+
1

18
2

CG17 2 1 0.1U_6.3V_K_X5R_0201 EDP_TX1- 19

[6] APU_EDP_TX1- 19
BKOFF# RG4 1 2 0_0402_5% DISPOFF# RG9 20
[30] BKOFF# USB20_N_CAMERA 20
1K_0402_5% 21
@ USB20_P_CAMERA 22 21
23 22
1

PCH_ENBKLRG5 1 2 0_0402_5% ENBKL RG8 1 2 0_0402_5% INVT_PWM 24 23

[6] PCH_ENBKL ENBKL [30] [6] PCH_EDP_PWM AUDIO_DMIC_CLK DMIC_CLK 24
RI46 1 2 0_0402_5% 25
25
1

[33] AUDIO_DMIC_CLK AUDIO_DMIC_DATA RI47 1 2 0_0402_5% DMIC_DATA 26

RG39 [33] AUDIO_DMIC_DATA 27 26
RG10 +DMIC_PWR 27
100K_0402_5% 28
100K_0402_5% 28
+3VS_CAMERA 29 31
30 29 GND1 32
2

30 GND2

HIGHS_FC5AF301-3181H
ME@
A A

DMIC_CLK INVT_PWM DISPOFF# DMIC_DATA

470P_50V_K_X7R_0201

470P_50V_K_X7R_0201
100P 25V J NPO 0201

100P 25V J NPO 0201

EMC_NS@

EMC_NS@

1 1 1 1
EMC_NS@

EMC_NS@

2 2 2 2 Security Classification LC Future Center Secret Data Title

CG36
CG2

CG4

CG3

Issued Date 2013/08/08 Deciphered Date 2013/08/05 eDP/CMOS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 16 of 45
5 4 3 2 1
 5 4 3 2 1

+3VS +3VS +3VS +3VS +3VS

RG36 RG37

1
1 2 1/10W_0_5%_0603 VDDIO_PS8203 1 2 1/10W_0_5%_0603 VDD_PS8203
RG41 RG43 RG45
1 1 1 1 1 1 4.7K_0402_5% 4.7K_0402_5% @ 4.7K_0402_5%

CG37
1U_6.3V_M_X5R_0201

CG38
0.1u_0201_10V6K

CG39
0.1u_0201_10V6K

CG40
1U_6.3V_M_X5R_0201

CG41
0.1u_0201_10V6K

CG42
0.1u_0201_10V6K

2
2 2 2 2 2 2
HDMI_EQ HDMI_PRE HDMI_DCIN

1
RG42 RG44
@ 4.7K_0402_5% @ 4.7K_0402_5%
D D

2
UG1
PS8203TQFN32GTR-A3_TQFN32_3X6

30 VDDIO_PS8203
APU_HDMI_TX2+ CG27 1 2 0.1u_0201_10V6K APU_HDMI_TX2+_C 1 VDDIO
[6] APU_HDMI_TX2+ APU_HDMI_TX2- APU_HDMI_TX2-_C IN_D2P APU_HDMI_DDC_DATA
CG28 1 2 0.1u_0201_10V6K 2 32
[6] APU_HDMI_TX2- APU_HDMI_HPD APU_HDMI_HPD_R IN_D2N SDA_SRC APU_HDMI_DDC_CLK APU_HDMI_DDC_DATA [6]
RG38 1 2 0_0402_5% 3 31
[6] APU_HDMI_HPD APU_HDMI_TX1+ APU_HDMI_TX1+_C HPD_SRC SCL_SRC APU_HDMI_DDC_CLK [6]
CG29 1 2 0.1u_0201_10V6K 4
[6] APU_HDMI_TX1+ APU_HDMI_TX1- 1 2 0.1u_0201_10V6K APU_HDMI_TX1-_C 5 IN_D1P 29 HDMIDAT_R
CG30 Add HDMI Redriver
[6] APU_HDMI_TX1- APU_HDMI_TX0+ APU_HDMI_TX0+_C IN_D1N SDA_SNK HDMICLK_R
CG31 1 2 0.1u_0201_10V6K 6 28
[6] APU_HDMI_TX0+ IN_D0P SCL_SNK
[6] APU_HDMI_TX0-
APU_HDMI_TX0- CG32 1 2 0.1u_0201_10V6K APU_HDMI_TX0-_C
HDMI_DCIN
7
IN_D0N HDMI_TX2+_C
Jevon@190611
8 27
APU_HDMI_CLK+ CG33 1 2 0.1u_0201_10V6K APU_HDMI_CLK+_C 9 DCIN_EN OUT_D2P 26 HDMI_TX2-_C
[6] APU_HDMI_CLK+ APU_HDMI_CLK- APU_HDMI_CLK-_C IN_CKp OUT_D2N HDMI_DET
CG34 1 2 0.1u_0201_10V6K 10 25
[6] APU_HDMI_CLK- IN_CKn HPD_SNK HDMI_TX1+_C
24
VDD_PS8203 11 OUT_D1P 23 HDMI_TX1-_C
VDD OUT_D1N 22 HDMI_TX0+_C
1 PAD 12 OUT_D0P 21 HDMI_TX0-_C
TG1 HDMI_EQ 13 PD# OUT_D0N 20 1
TG2 PAD
EQ CFG 19 HDMI_CLK+_C
HDMI_PRE 15 OUT_CKp 18 HDMI_CLK-_C
16 PRE OUT_CKn
REXT

EPAD
17

GND
CEXT
1

14

33
RG40 CG43
3.9K_0402_1% 0.1u_0201_10V6K
2

2
SVT Modify RG40 5.9K to 3.9K_0109

HDMI Redriver

C C

RG32 1 2 0_0402_5% HDMI_CLK-_CON

EMC_HCMC@ LG3
1

HDMI_CLK-_C 2 1 DG3
2 1 HDMI_DET 1 1 HDMI_DET
RG56 10 9
270_0402_1%
HDMI_CLK+_C 3 4 HDMICLK_R 2 2 9 8 HDMICLK_R
3 4
2

EXC24CH900U_4P HDMIDAT_R 4 4 7 7 HDMIDAT_R

RG31 1 2 0_0402_5% HDMI_CLK+_CON
+5VS_HDMI 5 5 6 6 +5VS_HDMI

3 3

RG26 1 2 0_0402_5% HDMI_TX0-_CON 8

EMC_HCMC@ LG4
1

HDMI_TX0-_C 2 1 AZ1045-04F_DFN2510P10E-10-9
2 1 RG57 EMC_NS@
270_0402_1%
HDMI_TX0+_C 3 4
3 4 EMC
2

EXC24CH900U_4P
RG24 1 2 0_0402_5% HDMI_TX0+_CON

RG27 1 2 0_0402_5% HDMI_TX1-_CON

+5VS +5VS_HDMI_F +5VS_HDMI
EMC_HCMC@ LG5 LP2301ALT1G_SOT23-3
1

HDMI_TX1-_C 2 1 FG1
2 1 RG58 1 3 QG3 1 2

S
B 270_0402_1% B
HDMI_TX1+_C 3 4 1.1A_8V_1206L110THYR
3 4

G
2

2
EXC24CH900U_4P
RG25 1 2 0_0402_5% HDMI_TX1+_CON
1 2
CG26 CG35
0.1u_0201_10V6K 10U 6.3V M X5R 0402

2
1
@
2 1 RPG1
HDMI_TX2-_CON [32] SUSP
RG30 1 2 0_0402_5% 2.2K_0404_4P2R_5%

EMC_HCMC@ LG6

3
4
1

HDMI_TX2-_C 2 1
2 1 RG59
270_0402_1%
HDMI_TX2+_C 3 4 +5VS_HDMI
3 4 JHDMI ME@
2

EXC24CH900U_4P
RG28 1 2 0_0402_5% HDMI_TX2+_CON 18 15 HDMICLK_R
+5V_Power SCL 16 HDMIDAT_R
SDA
HDMI_TX0+_CON 7
HDMI_TX0-_CON 9 TMDS_Data0+ 13
HDMI_TX1+_CON 4 TMDS_Data0- CEC 17
HDMI_TX1-_CON 6 TMDS_Data1+ DDC/CEC_Ground 19 HDMI_DET
HDMI_TX2+_CON 1 TMDS_Data1- Hot_Plug_Detect
HDMI_TX2-_CON 3 TMDS_Data2+
TMDS_Data2-
8 14

1
5 TMDS_Data0_Shield Utility
2 TMDS_Data1_Shield RG20
TMDS_Data2_Shield 27K_0402_5%
EMC 20 @
11 GND1 21

2
HDMI_CLK+_CON 10 TMDS_Clock_Shield GND2 22
HDMI_CLK-_CON 12 TMDS_Clock+ GND3 23
TMDS_Clock- GND4

ALLTO_C128AF-K1935-L

DG6 DG7
HDMI_CLK-_CON 1 1 10 9 HDMI_CLK-_CON HDMI_TX1-_CON 1 1 10 9 HDMI_TX1-_CON
A A

HDMI_CLK+_CON 2 2 9 8 HDMI_CLK+_CON HDMI_TX1+_CON 2 2 9 8 HDMI_TX1+_CON

HDMI_TX0-_CON 4 4 7 7 HDMI_TX0-_CON HDMI_TX2-_CON 4 4 7 7 HDMI_TX2-_CON

HDMI_TX0+_CON 5 5 6 6 HDMI_TX0+_CON HDMI_TX2+_CON 5 5 6 6 HDMI_TX2+_CON

3 3 3 3

8 8

AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9
EMC_NS@ EMC_NS@ Security Classification LC Future Center Secret Data Title
EMC Issued Date 2013/08/15 Deciphered Date 2013/08/15 HDMI_CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 17 of 45
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 18 of 45
5 4 3 2 1
 A B C D E

1 1

2 2

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 USB3.0 PORT (LEFT)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 19 of 45
A B C D E
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 M.2 SSD

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 20 of 45
5 4 3 2 1
 5 4 3 2 1

+3VS_SSD +3VS_SSD +3VS_SSD

SSD Reset control 1

0.1U_6.3V_K_X5R_0201
Jevon@190617

1
@

1
RF42 CF31
10K_0201_5% 2 RF34
@ 10K_0201_5%

5
UF2 @

VCC

2
PLT_RST# RF43 1 2 0_0201_5% 1
[7,26,28] PLT_RST# IN1 SSD_RST#
4
APU_SSD_RST# 2 OUT

GND
D [7] APU_SSD_RST# IN2 D

1
RF35 MC74VHC1G08DFT2G_SC70-5

3
+3VS_SSD 10K_0402_5%
+3VS
MAX 3A

2
RF44
1 2 1/10W_0_5%_0603

Change RF28 0603 R to J14 07/27

Follow S550 intel use precision resister 0802

+3VS_SSD

10U 6.3V M X5R 0402

0.1U_6.3V_K_X5R_0201

4.7U_6.3V_K_X5R_0402
1 1 1

CF8

CF9

CF10
JSSD

1 2 2 2 2
3 GND_1 3.3V_1 4 @
GND_2 3.3V_2 @
5 6
[4] PCIE_PRX_DTX_N0 7 PERN3 N/C_2 8
C [4] PCIE_PRX_DTX_P0 9 PERP3 N/C_3 10 C
PCIE_PTX_C_DRX_N0 11 GND_3 DAS/DSS# 12
[4] PCIE_PTX_C_DRX_N0 PCIE_PTX_C_DRX_P0 PETN3 3.3V_3
13 14
[4] PCIE_PTX_C_DRX_P0 PETP3 3.3V_4
15 16
[4] PCIE_PRX_DTX_N1 17 GND_4 3.3V_5 18
19 PERN2 3.3V_6 20 +3VS_SSD
[4] PCIE_PRX_DTX_P1 21 PERP2 N/C_4 22
PCIE_PTX_C_DRX_N1 23 GND_5 N/C_5 24
[4] PCIE_PTX_C_DRX_N1 PCIE_PTX_C_DRX_P1 PETN2 N/C_6
25 26
[4] PCIE_PTX_C_DRX_P1 PETP2 N/C_7

1
27 28
29 GND_6 N/C_8 30 RF41
[4] PCIE_PRX_DTX_N2 31 PERN1 N/C_9 32 @ 10K_0402_5%
[4] PCIE_PRX_DTX_P2 33 PERP1 N/C_10 34 S550_ICL PULL UP TO +3VS_SSD
RB521CM-30T2R_VMN2M-2
PCIE_PTX_C_DRX_N2 35 GND_7 N/C_11 36 D29
[4] PCIE_PTX_C_DRX_N2

2
PCIE_PTX_C_DRX_P2 37 PETN1 N/C_12 38 2 @1
[4] PCIE_PTX_C_DRX_P2 PETP1 DEVSLP SATA_DEVSLP1 [7]
39 40
41 GND_8 N/C_13 42 RF14 10K_0402_5%
[4] PCIE_PRX_DTX_P3 43 PERN0/SATA-B+ N/C_14 44 1 2
[4] PCIE_PRX_DTX_N3 45 PERP0/SATA-B- N/C_15 46 @
PCIE_PTX_C_DRX_N3 47 GND_9 N/C_16 48
[4] PCIE_PTX_C_DRX_N3 PCIE_PTX_C_DRX_P3 49 PETN0/SATA-A- N/C_17 50 SSD_RST#
[4] PCIE_PTX_C_DRX_P3 51 PETP0/SATA-A+ PERST# 52 SSD_CLKREQ_Q# 1 2 0_0402_5%
RF15 SSD_CLKREQ# [8]
53 GND_10 CLKREQ# 54 1 @ TF2
[8] CLK_PCIE_SSD# REFCLKN PEWAKE#
55 56
[8] CLK_PCIE_SSD REFCLKP N/C_18
57 58
GND_11 N/C_19
59 NC NC 60
@
61 NC NC 62 RF16 1 2 0_0402_5%
63 NC NC 64 SUSCLK_R [26]
65 NC NC 66
67 68 SUSCLK_SSD1
SSD_DET 69 N/C_1 SUSCLK 70
71 PEDET 3.3V_7 72 +3VS_SSD
73 GND_12 3.3V_8 74
75 GND_13 3.3V_9
GND_14

0.1U_6.3V_K_X5R_0201

4.7U_6.3V_K_X5R_0402
77 76 1 1 1 1
PEG1 PEG2 CF41
B B

CF39

CF40
CF38
ARGOS_NASM0-S6701-TS40
2 2 2 2

47U_6.3V_M_X5R_0603

47U_6.3V_M_X5R_0603
ME@ @ @
@
change to new symbol NASM0-S6701-TS40 0711

+3VALW_APU

SSD_SATA_PCIE_DET1#
2

SATA Device GND RF18

PCIE Device NC 2.2K_0402_5% Modify RF18 100K to 2.2k for SSD Lose_0109
1

RF19 1 2 0_0402_5% SSD_DET

[7] SSD_SATA_PCIE_DET1#
1

10K_0402_5% SSD_DET#
RF20 0--SATA
@
1--PCIE
2

RF20 unstuff follow X395

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 21 of 45
5 4 3 2 1
 5 4 3 2 1

+VBUS_CONN +5VALW +PD_LDO_3V3

1
RT1 RT2 RT3
@
RA=RT3
200K_0402_1% 200K_0402_1% 0_0402_5%

2
D LOC_PWR_MON ADDR_CFG D
VMON

1
RT5 RT6 RT7 RB=RT7
10K_0402_1% 10K_0402_1% 10K_0402_1%

2
+VBUS_CONN

1
+VCON_IN RT39
4.7_1206_5%
Change RT39 to 4.7R_1206 0803

2
RT13
1 2 1/10W_0_5%_0603 +VCON_IN_R

+5V_IN

0.1U_50V_K_X5R_0402
1 1

CT14
CT17
1 4.7U_50V_K_X5R_0805

10U 6.3V M X5R 0402

2 2

0.1U_6.3V_K_X5R_0201
CT5 1 1 CT17 Need to modify above 50V
10U_0603_10V6K
2 CT17 TBG Material 0821

CT6

CT15
Change CT17 to LBG material 1124_sit
C 2 2 C
Change CT17 to LBG Material SE00001BY00
CT5 use TBG material ,0821
Chang CT5 SE00000XO0T to SE00000XO0J(TBG to LBG material)_1124 SIT

+PD_LDO_3V3

4.7U_6.3V_K_X5R_0402
1 1

CT8
CT16
0.1U_6.3V_K_X5R_0201
+PD_LDO_3V3 2 2 RT30 Need to modify 2R_0805
DP2_AUXN_R
RT30 Modify 2.2ohm 5 % 0823
RT321 2 100K_0402_5%
UT3 RT26 1 @ 2 0_0402_5%

33

31

32

11
RT351 2 100K_0402_5% DP2_AUXP_R RTS5457V-GR_QFN40_5X5
1/8W_2.2_5%_0805

3V3_OUT

VBUS_IN

5V_IN

VCONN_IN
RT301 2 CT11 2 1 0.1U_50V_K_X5R_0402
+PD_LDO_3V3
RT31 1 2 200K_0402_1%

@
ADDR_CFG 26 9 CT9 1 2 220P_50V_K_X7R_0201
LOC_PWR_MON 28 ADDR_CFG/MGPIO17 DB_CFG 17
VMON 29 LOC_PWR_MON/MGPIO16 VBCAP 10 USBC0_CC1
SRC_PS_FLT VMON/MGPIO14 CC1 USBC0_CC2 USBC0_CC1 [24]
27 12
[23] SRC_PS_FLT DP2_AUXP_R IMON/MGPIO15 CC2 USBC0_CC2 [24] SRC_PS_EN
CT12 2 1 0.1U_6.3V_K_X5R_0201 14 16 SBU1 SBU1 [24] RT22 1 @ 2 4.7K_0402_5%
[6] DP2_AUXP DP2_AUXN_R AUX_P/MGPIO8 SBU1/MGPIO10
CT13 2 1 0.1U_6.3V_K_X5R_0201 13 15 SBU2 CT10 1 2 220P_50V_K_X7R_0201
[6] DP2_AUXN DP2_HPD AUX_N/MGPIO9 SBU2/MGPIO11 SBU2 [24] SRC_PS_FO
[6] DP2_HPD
2 23 RT23 1 @ 2 4.7K_0402_5%
18 HPD/GPIO3 C_DP_A/MGPIO0 22 IT9 IT10
19 H_DP/MGPIO4 C_DM_A/MGPIO1 21 @ @
25 H_DM/MGPIO5 C_DP_B/MGPIO2 20
24 BB_DP C_DM_B/MGPIO3 34 VBUS_DSCHG

1
[30] EC_SMB_CK2 EC_SMB_CK2 RT25 1 EC_SMB_CK2_R
2 0_0402_5% 3 BB_DM GPIO21 35 APU_RST#_PD +3VL
[30] EC_SMB_DA2 EC_SMB_DA2 RT24 1 EC_SMB_DA2_R
2 0_0402_5% 4 SCL1/GPIO4 GPIO20 38 PDC_SCL
[30] EC_PD_INT# EC_PD_INT# RT21 1 INT#_TYPEC_R
2 0_0402_5% 5 SDA1/GPIO5 SCL4/GPIO13 37 PDC_SDA PDC_SCL [9]
6 INT1/GPIO6 SDA4/GPIO14 36 I2C1_IRQ# RT20 1 @ 2 0_0402_5% INT#_TYPEC1_CPU PDC_SDA [9]
SRC_PS_FO SCL2/GPIO7 INT4/GPIO15 PD_ACK_SNK1 INT#_TYPEC1_CPU [8]
[23] SRC_PS_FO RT33 1 2 0_0402_5% 7 1
SRC_PS_EN SDA2/GPIO8 SCL3/GPIO10 PD_VBUS_C_CTRL1 PD_ACK_SNK1 [39]
[23] SRC_PS_EN 8 40
B INT2/GPIO9 SDA3/GPIO11 PD_VBUS_C_CTRL1 [39] B
1
1/16W_6.2K_1%_0402 2 RT37 30 39 1 RPT1
REXT INT3/GPIO12 TT5 @ EC_SMB_CK2 1 8
EPAD EC_SMB_DA2 2 7
EC_PD_INT# 3 6
4 5

1/16W_4.7K_5%_8P4R_0804
41

Chang UT3 SA0000ACM00 to SA0000ACM10(Fw Change)_1124 SIT

+PD_LDO_3V3

RPT2
1 8
I2C1_IRQ# 2 7
+3VS PDC_SDA 3 6
PDC_SCL 4 5
1

1/16W_4.7K_5%_8P4R_0804
+3VALW RT38
+VBUS_CONN 4.7K_0402_5%
@
1

RT36
100K_0402_5% APU_RST#_PD
@
1

RT27
3

QT4B
150_0603_5%
D2

5
High enable discharge
2

G2
Low disable discharge
S2
6

QT4A
4
1

D PJT7838_SOT363-6
D1

VBUS_DSCHGRT28 1 2 0_0402_5% 2 QT3 2 @

[6] APU_RST# G1
A G 2N7002KW_SOT323-3 A
S1
1

S
3

RT29
PJT7838_SOT363-6
1

100K_0402_5% Max Vds ≥30V @

Max Vgs ≥5V
2

Id ≥200mA

APU_RST# RT34 1 2 0_0402_5% APU_RST#_PD

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 Cardreader

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 22 of 45
5 4 3 2 1
 5 4 3 2 1

+5VALW +VCON_IN

RT187
1 2 1/10W_0_5%_0603

+5V_IN

D D
RT191
1 2 1/10W_0_5%_0603

+VBUS_CONN

@ UT4
DT2 2 1 RB751V-40_SOD323-2 3 4
IN OUT
1 6
ADJ
Vr＞ 28V CT148 RT193 1 2 1/16W_100K_5%_0402 1
EN 1 1

1
CT149 CT150
If＞ 150mA 2.2U_50V_K_X5R_0603 RGB( 0,255,128) 5 2 RT194
2 GND NC 47P_25V_J_NPO_0201 2.2U_10V_K_X5R_0402
RGB( 0,255,128) @
SYV634DEC_DFN6_2X2 1/16W_73.2K_1%_0402 2 2
@ @ @
SA00008EQ00

2
@

1
D @
PD_VIN_CTRL 2
[30] PD_VIN_CTRL G QT5 vref0.6V

1
2N7002KW_SOT323-3
RT195 S SB000019400 RT196

3
@
1/16W_100K_5%_0402 1/16W_10K_1%_0402

2
@ @

C ADD Reserved LEO 0805 C

+5VALW

+VBUS_CONN
1 1
CT33 CT34 3A

1
100U_1206_6.3V6M1U_10V_K_X5R_0603
2 2 J13

1
JUMP_43X118
@

2
2
+PD_LDO_3V3
DT4 @
SCS00006S00
1

UT2 RB751V-40_SOD323-2
RT67 A1 B1 2 1
10K_0402_1% A2 VIN1 VCP1 B2
VIN2 VCP2 C1
VCP3
2

SRC_PS_FLT A4 C2
[22] SRC_PS_FLT FLT# VBUS1 D1
B [22] SRC_PS_EN SRC_PS_EN B4 VBUS2 D2 B
EN VBUS3
[22] SRC_PS_FO SRC_PS_FO C4 A3
FO ILIM

1
B3

1/16W_16K_1%_0402
GND1
2
1

1
C3 RT68
RPT8 GND2 D3 CT36
GND3 D4 4.7U_0805_25V6-K
1/16W_100K_5%_4P2R_0404

2
CAP
close UT2.D2

2
NX5P3290UKZ_WLCSP16 1
3
4

SA00008BS00
CT35
1000P_0402_50V_X7R_0402
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 23 of 45
5 4 3 2 1
 5 4 3 2 1

+VBUS_CONN

D D

0.1U_25V_K_X5R_0201

0.1U_25V_K_X5R_0201

0.1U_25V_K_X5R_0201

0.1U_25V_K_X5R_0201
1 1 1 1
USBC0_SBU1_CON

CT78

CT79

CT80

CT81
SBU1 RT182 1 2 0_0402_5%
[22] SBU1

SBU2 RT183 1 2 0_0402_5% USBC0_SBU2_CON Rated current=5A 2 2 2 2

[22] SBU2

USBC0_CC1 RT184 1 2 0_0402_5% USBC0_CC1_CON

[22] USBC0_CC1
SIV:Change RT184/185 0201 to 0402 0922 close to JTC PIN A4,A9,B4,B9
USBC0_CC2 RT185 1 2 0_0402_5% USBC0_CC2_CON
[22] USBC0_CC2

RT111 1 2 0_0402_5%

LT3 EMC_NS@
USBC0_RX_N1 CT141 1 2 USBC0_RX_N1_C 2 1 USBC0_RX_N1_CON
[9] USBC0_RX_N1 2 1
0.33U_25V_K_X5R_0402

USBC0_RX_P1 CT140 1 2 USBC0_RX_P1_C 3 4 USBC0_RX_P1_CON

[9] USBC0_RX_P1 3 4
0.33U_25V_K_X5R_0402
EXC24CH900U_4P

RT116 1 2 0_0402_5%

C C

RT105 1 2 0_0402_5%
DT39 EMC_NS@ EMC_NS@DT40

LT4 EMC_NS@ USBC0_CC1_CON 1 2 2 1 USBC0_CC2_CON

1 2 2 1
[9]

[9]
USBC0_RX_N2

USBC0_RX_P2
USBC0_RX_N2

USBC0_RX_P2
CT143

CT142
1

1
2

2
USBC0_RX_N2_C
0.33U_25V_K_X5R_0402

USBC0_RX_P2_C
2

3
2

3
1

4
1

4
USBC0_RX_N2_CON

USBC0_RX_P2_CON
PESD5V0H1BSF SOD962 PESD5V0H1BSF SOD962 Type C Connector
0.33U_25V_K_X5R_0402 DT41 EMC_NS@ EMC_NS@ DT42
EXC24CH900U_4P
USBC0_SBU1_CON 1 2 2 1 USBC0_SBU2_CON
1 2 2 1
RT112 1 2 0_0402_5%
PESD5V0H1BSF SOD962 PESD5V0H1BSF SOD962
+VBUS_CONN
DT43 EMC_NS@ EMC_NS@ DT44

USB20_P0_CON_AB 1 2 2 1 USB20_N0_CON_AB
RT117 1 2 0_0402_5% 1 2 2 1

PESD5V0H1BSF SOD962 PESD5V0H1BSF SOD962

LT7 EMC_NS@
USBC0_TX_P1 CT74 1 2 USBC0_TX_P1_C 2 1 USBC0_TX_P1_CON
[9] USBC0_TX_P1 2 1
0.22U_25V_K_X5R_0402

USBC0_TX_N1 CT75 1 2 USBC0_TX_N1_C 3 4 USBC0_TX_N1_CON

[9] USBC0_TX_N1 3 4
0.22U_25V_K_X5R_0402 JTC ME@
EXC24CH900U_4P
A1 B12
RT118 1 2 0_0402_5% GND1 GND4
DT45 EMC_NS@ EMC_NS@DT46 USBC0_TX_P1_CON A2 B11 USBC0_RX_P1_CON
SSTXp1 SSRXp1
USBC0_TX_P1_CON 1 2 2 1 USBC0_TX_N1_CON USBC0_TX_N1_CON A3 B10 USBC0_RX_N1_CON
1 2 2 1 SSTXn1 SSRXn1
A4 B9
RT119 1 2 0_0402_5% PESD5V0H1BSF SOD962 PESD5V0H1BSF SOD962 Vbus1 Vbus4
B USBC0_CC1_CON USBC0_SBU2_CON B
A5 B8
DT47 EMC_NS@ EMC_NS@DT48 CC1 SBU2
LT8 EMC_NS@ USB20_P0_CON_AB A6 B7 USB20_N0_CON_AB
USBC0_TX_P2 CT76 1 2 USBC0_TX_P2_C 2 1 USBC0_TX_P2_CON USBC0_RX_N1_CON 1 2 2 1 USBC0_RX_P1_CON Dp1 Dn2
[9] USBC0_TX_P2 2 1 1 2 2 1 USB20_N0_CON_AB USB20_P0_CON_AB
0.22U_25V_K_X5R_0402 A7 B6
Dn1 Dp2
USBC0_TX_N2 CT77 1 2 USBC0_TX_N2_C 3 4 USBC0_TX_N2_CON PESD5V0H1BSF SOD962 PESD5V0H1BSF SOD962 USBC0_SBU1_CON A8 B5 USBC0_CC2_CON
[9] USBC0_TX_N2 3 4 SBU1 CC2
0.22U_25V_K_X5R_0402
EXC24CH900U_4P DT49 EMC_NS@ EMC_NS@DT50 A9 B4
Vbus2 Vbus3
RT121 1 2 0_0402_5% USBC0_RX_P2_CON 1 2 2 1 USBC0_TX_N2_CON USBC0_RX_N2_CON A10 B3 USBC0_TX_N2_CON
1 2 2 1 SSRXn2 SSTXn2
USBC0_RX_P2_CON A11 B2 USBC0_TX_P2_CON
PESD5V0H1BSF SOD962 PESD5V0H1BSF SOD962 SSRXp2 SSTXp2
A12 B1
@ DT51 EMC_NS@ EMC_NS@DT52 GND2 GND3
RT120 1 2 0_0402_5%
USBC0_RX_N2_CON 1 2 2 1 USBC0_TX_P2_CON 28 25
1 2 2 1 29 GND8 GND5 26
LT5 EMC@ 30 GND9 GND6 27
USB20_P0 2 1 USB20_P0_CON_AB PESD5V0H1BSF SOD962 PESD5V0H1BSF SOD962 GND10 GND7
[9] USB20_P0 2 1

DT53 HIGHS_UB11245-B200W-1H
USB20_N0 3 4 USB20_N0_CON_AB EMC@
[9] USB20_N0 3 4
EXC24CH900U_4P +VBUS_CONN 1 2
@ 1 2
RT122 1 2 0_0402_5%

SPHV24-01ETG-C_SOD882-2

A A

ESD 5G

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 24 of 45
5 4 3 2 1
 5 4 3 2 1

REMOTE1+_R RS16 1 2 0_0201_5% REMOTE1+

REMOTE1+
Near CHARGER REMOTE2+ Near CPU
1 1

1
REMOTE1-_R RS17 1 2 0_0201_5% REMOTE1- CS7 C CS2 C
100P 25V J NPO 0201 2 QS2 100P 25V J NPO 0201 2 QS1
@ B MMBT3904WH_SOT323-3 @ B MMBT3904WH_SOT323-3
REMOTE2+_R RS14 1 2 0_0201_5% REMOTE2+ 2 E 2 E

3
REMOTE1- REMOTE2-

REMOTE2-_R RS15 1 2 0_0201_5% REMOTE2-

D D
Close to U1 Near heat pipe
REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-: REMOTE1+_R
Trace width/space:10/10 mil 1
+3VALW
CS1
+3VS Trace length:<8" 2200P_25V_K_X7R_0201
2 REMOTE1-_R
US1

1
RS1
1 10 EC_SMB_CK0 13.7K_0402_1%
VDD SCLK EC_SMB_CK0 [6,30]
1 REMOTE1+_R 2 9 EC_SMB_DA0

2
D1+ SDA EC_SMB_DA0 [6,30] NTC_V1
CS3
REMOTE1-_R 3 8
Close to U1 [25,30] NTC_V1

1
0.1U_6.3V_K_X5R_0201 D1- ALERT# REMOTE2+_R
2 REMOTE2+_R 4 7 1 2 100K_0201_5% RS13
RS2 +3VS 1
D2+ TCRIT# CS6 100K_0402_1%_NCP15WF104F03RC
REMOTE2-_R 5 6 @ 2200P_25V_K_X7R_0201
D2- GND

2
2 REMOTE2-_R
NCT7719W_MSOP10

C C
+5VLP +5VLP
+5VLP

HW thermal sensor

2
1 RS3 RS4
CS4 21.5K_0402_1% 21.5K_0402_1%
0.1U_6.3V_K_X5R_0201 @ @
@

1
2 @
US2
1 8 TMSNS1 RS6 1 @ 2 0_0402_5% NTC_V1
VCC TMSNS1 NTC_V1 [25,30]
2 7 PHYST1 RS7 1 @ 2 10K_0402_5%
GND RHYST1
3 6 TMSNS2
[30,41] EC_ON_5V OT1 TMSNS2
4 5 PHYST2 RS101 @ 2 10K_0402_5%
OT2 RHYST2
G718TM1U_SOT23-8

over temperature threshold:

RSET=3*RTMH
92+/-30C
Hysteresis temperature threshold.
RHYST=(RSET*RTML)/(3*RTML-RSET)
56+/-30C

B B

SIV:Change RS20(0402),CS10(0805)Footpring to 0603 0922

FAN CONN HALL Sensor CONN
+5VS +5VS_FAN

FAN RS20
1 2 1/10W_0_5%_0603 +3VL RS19 1 2 0_0201_5%
LID_SW# [30]
US3
1
1 1 1 CS5
CS11 2 OUTPUT 100P 25V J NPO 0201
CS10 0.1u_0201_10V6K 3 GND EMC_NS@
10U_0603_10V6K @ 4 NC 2
2 2 5 VDD
1 EP
CS8 AH1912-FA-7 X1-DFN1216
0.1U_6.3V_K_X5R_0201
2

+5VS_FAN FAN Conn

JFAN
EC_FAN_PWM 1
[30] EC_FAN_PWM EC_FAN_SPEED 2 1 Change US3 (AH1902-FA-7_X1-DFN1216-4) to H1912-FA-7 X1-DFN1216
[30] EC_FAN_SPEED 3 2
4 3
4
A 5 A
6 GND1
GND2

HIGHS_WS33040-S0351-HF
ME@

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Thermal sensor/FAN CONN/TPM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 25 of 45
5 4 3 2 1
 A B C D E

Mini-Express Card(WLAN/WiMAX)
MAX 1.6A
+3VS
+3VS +3VS_WLAN
+3VS_WLAN UN9 @
5 1
RN190 IN OUT
1 2 1/10W_0_5%_0603 2
GND
3V_WLAN_EN 4 3
1 [30] 3V_WLAN_EN EN OCB 1

SY6288C20AAC_SOT23-5
WLAN Power control,follow T14
Jevon@190617

+1.8VS

+1.8VS

QWLAN@ QWLAN@

2
RN178
RN179
100K_0402_5% 100K_0402_5% CN100 QWLAN@
UN1 1 2

1
1 5
NC VCC 0.1U_6.3V_K_X5R_0201
M2_UART_RX 2
A
3 4 UART0_RXD RN182 1 2 0_0402_5% APU_UART0_RXD
GND Y APU_UART0_RXD [8]
SN74LVC1G07DBV_23-5 QWLAN@
QWLAN@
+1.8VS
+3VS_WLAN

UN2 CN101 QWLAN@

+3VS 1 5 1 2
NC VCC

0.1U_6.3V_K_X5R_0201

0.01U_0402_25V_X7R_0402

10U 6.3V M X5R 0402

M2_UART_CTS# 2 0.1U_6.3V_K_X5R_0201
1 1 1 A

CN92

CN93

CN94
2 2
3 4 UART0_CTS# RN183 1 2 0_0402_5% APU_UART0_CTS#
GND Y APU_UART0_CTS# [8]
2 2 2 SN74LVC1G07DBV_23-5 QWLAN@
1 @
CN96 @ QWLAN@
0.1U_6.3V_K_X5R_0201
@
2
UN10 JWLAN ME@ +1.8VS
5 1 1 2
Vcc OE 3 GND1 3.3VAUX1 4 TN1
[9] USB20_P6 USB_D+ 3.3VAUX2
2 SUSCLK 5 6 1 @
IN_A [9] USB20_N6 USB_D- LED1#
7 8

2
SUSCLK_R 4 3 9 GND2 PCM_CLK/I2S_SCK 10 RN180
[21] SUSCLK_R OUT_Y GND SDIO_CLK PCM_SYNC/I2S_WS
11 12 RN181
13 SDIO_CMD PCM_IN/I2S_SD_IN 14
SDIO_DATA0 PCM_OUT/I2S_SD_OUT 1K_0402_5%
M74VHC1GT125DF2G_SC70-5 15 16 1 @ TN2 1K_0402_5%
17 SDIO_DATA1 LED#2 18 QWLAN@
@

1
19 SDIO_DATA2 GND11 20 RN186 1 2 0_0402_5% M2_UART_WAKE#
SDIO_DATA3 UART_WAKE# M2_UART_RX QWLAN@QWLAN@ UN4
21 22 RN177 1 2 0_0402_5%
23 SDIO_WAKE# UART_RXD QWLAN@ M2_UART_TX 4 3
SDIO_RESET# Y GND
+3VS 2 UART0_TXD RN184 1 2 0_0402_5% APU_UART0_TXD
A APU_UART0_TXD [8]
QWLAN@CN103
KEY E 1 2 5 1 QWLAN@
25 PIN24~PIN31 NC PIN 24 +3VS_WLAN VCC NC
27 26 0.1U_6.3V_K_X5R_0201
29 28 SN74LVC1G07DBV_23-5
UN3

1
31 30 QWLAN@
RN188 M2_UART_RTS# 4 3
33 32 RN174 1 QWLAN@2 0_0402_5% M2_UART_TX Y GND
GND3 UART_TXD 10K_0402_5%
35 34 RN175 1 QWLAN@2 0_0402_5% M2_UART_CTS# QWLAN@ +3VS 2 UART0_RTS# RN185 1 2 0_0402_5% APU_UART0_RTS#
[4] PCIE_PTX_C_DRX_P4 PETP0 UART_CTS A APU_UART0_RTS# [8]
37 36 RN176 1 QWLAN@2 0_0402_5% M2_UART_RTS#
[4] PCIE_PTX_C_DRX_N4

2
39 PETN0 UART_RTS 38 5 1 QWLAN@
41 GND4 VENDOR_DEFINED1 40 VCC NC
[4] PCIE_PRX_DTX_P4 PERP0 VENDOR_DEFINED2 1
43 42 QWLAN@ QWLAN@
[4] PCIE_PRX_DTX_N4 PERN0 VENDOR_DEFINED3 M2_BT_WAKE# M2_BT_WAKE#_R SN74LVC1G07DBV_23-5
45 44 RN187 1 2 QWLAN@ CN102
GND5 COEX3 M2_BT_WAKE#_R [30]
47 46 0_0402_5% 0.1U_6.3V_K_X5R_0201
3 [8] CLK_PCIE_WLAN REFCLKP0 COEX2 2 3
49 48
[8] CLK_PCIE_WLAN# REFCLKN0 COEX1 SUSCLK_R
51 50 RN161 1 2 0_0402_5%
WLAN_CLKREQ_Q# GND6 SUSCLK WLAN_PLT_RST# RN173 1 SUSCLK [8]
[8] WLAN_CLKREQ# RN162 1 2 0_0402_5% 53 52 2 0_0402_5%
RN163 1 2 0_0402_5% PCIE_WAKE#_R 55 CLKREQ0# PERST0# 54 BT_OFF# RN164 1 2 1K_0402_5% PLT_RST# [7,21,28]
[30] WLAN_WAKE# PEWAKE0# W_DISABLE2# WLAN_OFF# PCH_BT_OFF# [7]
57 56 RN166 1 2 0_0402_5%
GND7 W_DISABLE1# PCH_WLAN_OFF# [7]
@ RN172 2 1 0_0402_5% EC_RX +3VS_WLAN
@
59 58 WLAN_SMB_DATA RN160 1 2 0_0402_5%
RSRVD/PETP1 I2C_DATA WLAN_SMB_CLK EC_RX [30]
61 60 RN169 1 2 0_0402_5%
EC_TX [30]

1
+3VS_WLAN 63 RSRVD/PETN1 I2C_CLK 62
65 GND8 ALERT# 64 EC_TX_R RN171 2 1 0_0402_5% RN189

1
67 RSRVD/PERP1 RSRVD 66 @ 10K_0402_5%

2
69 RERVD/PERN1 UIM_SWP/PERST1# 68 RN170

G
71 GND9 UIM_POWER_SNK/CLKREQ1# 70 100K_0402_5%

2
RN6 1 210K_0402_5% PCIE_WAKE#_R 73 RSRVD/REFCLKP1 UIM_POWER_SRC/GPIO1/PEWAKE1# 72
RSRVD/REFCLKN1 3.3VAUX3 QWLAN@
75 74

2
GND10 3.3VAUX4 New add pin 54/64 RX/TX,,,07/29 M2_UART_WAKE# 3 1 M2_UART_WAKE#_APU
@ M2_UART_WAKE#_APU [7]

D
77 76
GND15 GND14
+3VS_WLAN QN7
ARGOS_NASE0-S6701-TS40 L2N7002KWT1G_SOT323-3
QWLAN@

0.1U_6.3V_K_X5R_0201

0.01U_0402_25V_X7R_0402

10U 6.3V M X5R 0402

1 1 1
CN97

CN98

CN99
@
2 2 2@
@

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 NGFF WLAN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 26 of 45
A B C D E
 5 4 3 2 1

BUTTON
RTC +3VL
+3VL +3VL

2
1
RNOV1 VCCRTC RRTC1
100K_0402_5% RBUT1 0_0402_5%
100K_0402_5%

1
RNOV2 RBUT2 DRTC1 RTC_VCC

2
D NOVO_BTN# D
1 2 0_0402_5% ON/OFF 1 2 0_0402_5% ON/OFFBTN# BAT54CW_SOT323-3
NOV_BTN# [30] [30] ON/OFF
2

SHORT PADS
2

SHORT PADS

J3
don't short @ 1

J2
@

1
1
3 RRTC3 2 1 1K_0603_5%

1
CRTC1
1U_6.3V_M_X5R_0201
2 @

+3VALW +3VALW_IO

RX8
1 2 0_0402_5% Redriver

+5VALW
USB POWER SW
C UX1 +USB_VCCB C
1
+USB_VCCA JPIO
CX1 5 1 1
IN OUT +USB_VCCB 1
@ 0.1u_0201_10V6K 2
2 2 3 2
GND 4 3
1
4 3 5 4
ENB OCB USB_OC1# [9] CX21 6 5
RX7 1 USB_ON#_R
2 0_0201_5% SY6288D20AAC_SOT23-5 0.1u_0201_10V6K 7 6
[30] USB_ON# 2 7
@ 8
9 8
USB30_RX_N4 10 9
[9] USB30_RX_N4 USB30_RX_P4 11 10
[9] USB30_RX_P4 12 11
USB-A Port2 --USB3.0 USB30_TX_N4 13 12
[9] USB30_TX_N4 USB30_TX_P4 14 13
[9] USB30_TX_P4 15 14
USB30_TX_P1 16 15
[9] USB30_TX_P1 USB30_TX_N1 17 16
[9] USB30_TX_N1 18 17
USB-A Port1 --USB3.0 AOU USB30_RX_P1 19 18
[9] USB30_RX_P1 USB30_RX_N1 20 19
[9] USB30_RX_N1 20
USB Charger USB-A Port1 --USB2.0 USB20_P1_C
21
22 21
22
USB20_N1_C 23
24 23
+5VALW 2.2A [9] USB20_N4
USB20_N4
USB20_P4
25 24
25
USB-A Port2 --USB2.0 26
UX2 [9] USB20_P4 27 26
SN1702001RTER_WQFN16_3X3 USB20_N5 28 27
Caedreader [9] USB20_N5 USB20_P5 29 28
1 16 ILIM_HI RX5 1 2 1/20W_20K_5%_0201 [9] USB20_P5 30 29
IN ILIM_HI 31 30
USB20_N1 2 15 ILIM_LO RX6 1 @ 2 1/20W_20K_5%_0201 FP@ 32 31
[9] USB20_N1 DM_OUT ILIM_LO FPR_LED_GREEN# 1 2 220_0402_1% 33 32
USB20_P1 [30] FPR_LED_GREEN# 33
3 14 RI3016 ON/OFFBTN# 34
[9] USB20_P1 DP_OUT GND NOVO_BTN# 35 34
ILIM_SEL 4 13 36 35
B ILIM_SEL FAULT USB_OC0# [9] [30] PWR_LED_WIT# 36 B
37
USB_CHG_EN RTC_VCC 37
5 12 38
[30] USB_CHG_EN EN OUT +USB_VCCA +3VALW_IO 38
39 41
CHG_MOD1 USB20_N1_C +3VS 39 GND1
6 11 40 42
[30] CHG_MOD1 CLT1 DM_IN 40 GND2
1
7 10 USB20_P1_C
CLT2 DP_IN CX20
E_PAD

CHG_MOD3 8 9 0.1u_0201_10V6K ELCO_046809640410846+

[30] CHG_MOD3 CLT3 STATUS STATUS# [30] 2
@ ME@

1
17

CX2
@ 0.1u_0201_10V6K
2

CLT1 CLT2 CLT3 ILIM_SEL MOD +5VALW

* 0 0 0 X DCH OUT held low RX1 1 2 10K_0201_5%STATUS#

* 1 1 1 1 CDP Data Connected and Load Detect Active +5VALW

RX2
1 1 1 0 SDP2 Data Connected 1 2 0_0402_5% ILIM_SEL
*
1 @ USB_CHG_EN
* 1 1 0 X SDP1 Data Connected RX3 2 100K_0201_5%

1 @
A
* 0 1 0 X SDP1 Data Connected RX4 2 100K_0201_5% ILIM_SEL A

* 1 0 0 X DCP_Short Device Forced to stay in DCP BC 1.2 charging mode

* 1 0 1 X DCP_Divider Device Forced to stay in DCP Divider 1 Charging Mode

* 0 1 1 X DCP_Auto Data Disconnected and Load Detect Active

Security Classification LC Future Center Secret Data Title

* 0 0 1 X DCP_Auto Data Disconnected and Load Detect Active

Issued Date 2016/08/16 Deciphered Date 2017/08/15 IO CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 27 of 45
5 4 3 2 1
 5 4 3 2 1

+1.8VS
+1.8V_TPM
1A
RM3 2 @ 1 0_0402_5%
+1.8VALW

RM4 2 TPM@1 0_0402_5%

+3VALW +1.8V_TPM
D D

2
RM5 RM6
TPM@ @ RTPM28 stuff for NationZ
+1.8VS +1.8V_TPM 1/10W_0_5%_0603 1/10W_0_5%_0603
+1.8V_TPM

1
1

1
RM7 RM8
TPM@ TPM@
10K_0402_5% 10K_0402_5%
2

2
DM1
2 1 1 1 1 2
2 1 TPM_SPI_PIRQ# CM1 CM2 CM3 CM4 CM5 CM6
[8] PCH_SPI_PIRQ#
@ TPM@ 0.1U_6.3V_K_X5R_0201 0.1U_6.3V_K_X5R_0201 TPM@ @
TPM@ 10U_0603_6.3V6M 4.7U_0402_6.3V6M TPM@ TPM@ 1U_0402_6.3V6K 10U_0603_6.3V6M
RB751V-40_SOD323-2 1 2 2 2 2 1
SCS00008K00

UM1

22

1
TPM@

VPS

NiC2

NiC1
C C
TPM_SPI_PIRQ# 18
SPI_PIRQ 3 TPM_GP2 RM9 2 TPM@ 1 10K_0402_5%
NiC6 TPM_PIN4 RM10 +1.8V_TPM
4 2 @ 1 0_0402_5%
TPM_SPI_MOSI SPI_SI_R NiC7 +1.8V_TPM
RM22 2 TPM@1 0_0402_5% 21 5
[8] TPM_SPI_MOSI TPM_SPI_MISO SPI_SO_R MOSI NiC8
RM23 2 TPM@1 0_0402_5% 24 10
[8] TPM_SPI_MISO MISO NiC9 11
NiC10 12
NiC11 13
SPI_CS_R# 20 NiC12 14
SPI_CS NiC13 +1.8V_TPM
15
TPM_SPI_CLK RM24 2 TPM@1 0_0402_5% SPI_CLK_R 19 NiC14 16
[8] TPM_SPI_CLK SPI_CLK NiC15 25
TPM_PLT_RST# 17 NiC16 26
+1.8V_TPM SPI_RST NiC17 27 TPM_PIN27 RM14 1 @ 2 10K_0402_5%
6 NiC18 28
GPIO NiC19 31
NiC20
1

7
RM15 PP
TPM@
10K_0402_5% 29 TPM_PIN29 PIN29 reserve for TPM MS low power mode
NiC21

1
30
2

NiC22

GND1

GND2
RM16

NiC4

NiC5
NiC3
TPM_PLT_RST# @
B +5VALW 10K_0402_5% B

23

32

33
ST33HTPH2E32AHB4_VQFN32_5X5 +1.8V_TPM
1

1TPM_PIN2
RM17
10K_0402_5%

1
TPM@

RM1
RM18
2

D @
2 QM1A 10K_0402_5%

0_0402_5%
G 2N7002KDWH_SOT363-6

2
TPM@ TPM_PIN29 RM19 2 @ 1 0_0402_5% PLT_RST#
S
1

2
DM3
3

D
5 QM1B 2 1
[7,21,26] PLT_RST#
G 2N7002KDWH_SOT363-6 TPM@
TPM@ @
S RB751V-40_SOD323-2
4

SCS00008K00

+1.8VALW +1.8V_TPM
2

A A
RM2 RM20
10K_0402_5% @
TPM@ TPM@ 10K_0402_5%
RM21 2 1 0_0402_5% SPI_CS_R# Title
[8] SPI_CS#_TPM Security Classification LC Future Center Secret Data
1

Issued Date 2016/08/16 Deciphered Date 2017/08/15 TPM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 28 of 45
5 4 3 2 1
 A B C D E F G H

1 1

HDD Power control, MAX 3A

follow S145API 07/26

+5VS +5VS_HDD
RF40
1 2 1/10W_0_5%_0603

0.1u_0201_10V6K

33P_50V_J_NPO_0201

33P_50V_J_NPO_0201
CF18

CF19

CF20

CF21
10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

1 1 1 1 1 1 1

CF22

CF23 RF_NS@

CF24 RF_NS@
@ @

@
2 2 2 2 2 2 2

2 2

For EMC

Change CF18~21 to 10U 6.3V/follow S550 Intel for limit hight 0806

SATA HDD Conn.

ME@
HIGHS_FC5AF101-2931H
1
[4] SATA_PTX_DRX_P0
SATA_PTX_DRX_P0 CF17 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_P0 2 1
[4] SATA_PTX_DRX_N0
SATA_PTX_DRX_N0 CF16 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_N0 3 2
4 3
[4] SATA_PRX_DTX_N0 SATA_PRX_DTX_N0 CF14 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_N0 5 4
[4] SATA_PRX_DTX_P0 SATA_PRX_DTX_P0 CF15 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_P0 6 5
7 6
8 7 12
3 9 8 GND2
3
10 9 11
10 GND1
+5VS_HDD

JHDD

Mirror JHDD For Pin number as same intel S550_1123

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 HDD CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 29 of 45
A B C D E F G H
 5 4 3 2 1

RE1
1 2 1/10W_0_5%_0603
+3VL +3VL_EC +5VALW
@
SUSP# RE4357 1 2 100K_0402_5% USB_ON# RE15 1 2 10K_0402_5%
+3VL_EC +3VL_EC_R +3VL_EC RE3 1 @ 2 1/10W_0_5%_0603
LE1 +3VALW
1 2 1/10W_0_5%_0603
All capacitors close to EC +3VL_EC +3VS

CD@

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
1 1
CE4 CE5 1 1 1 @ 1 1 @ 1 RPE5
0.1U_6.3V_K_X5R_0201 1000P 25V K X7R 0201 EC_SMB_CK0 4 1 2.2K_0404_4P2R_5%
EC_SMB_DA0 3 2
LE2 2 2
EC_AGND 2 2 2 2 2 2

CE11
1 2 1/10W_0_5%_0603 @
+3VL_EC_R

CE10
CE6

CE7

CE8

CE9
+3VL_EC

RPE8
EC_AGND EC_SMB_CK3 4 1 2.2K_0404_4P2R_5%
follow L340 API EC_SMB_DA3 3 2

+3VS +1.8VALW
VCC:power supply of LPC
D VSTBY_FSPI: power supply of SPI flash D

2
RE4377
1/10W_0_5%_0603
+3VL_EC
RPE7

11 1
EC_SMB_CK1 4 1 2.2K_0404_4P2R_5%
UE1

114
121

106

127
EC_SMB_DA1 3 2

26
50
92

74
IT8227E-CX_LQFP128_16X16
RE1000 1 2 0_0402_5% EC_LPC_AD0 10 87 EC_SMB_CK0 +3VS
PD Controller==>APU/Thermal

VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VCC

AVCC

VSTBY(PLL)
VFSPI
[8] LPC_AD0 EC_LPC_AD1 EIO0/LAD0/GPM0(3) SMCLK0/GPF2 EC_SMB_DA0 EC_SMB_CK0 [6,25]
[8] LPC_AD1 RE1001 1 2 0_0402_5% 9 88
EC_SMB_DA0 [6,25]
RE1002 1 2 0_0402_5% EC_LPC_AD2 8 EIO1/LAD1/GPM1(3) SMDAT0/GPF3 115 EC_SMB_CK1 SERIRQ RE4356 1@ 2 10K_0402_5%
[8] LPC_AD2 EC_LPC_AD3 EIO2/LAD2/GPM2(3) SM BUS SMCLK1/GPC1 EC_SMB_DA1 EC_SMB_CK1 [39,40] Charger IC, Battery EC_TP_OFF#
[8] LPC_AD3 RE1003 1 2 0_0402_5% 7 116
EC_SMB_DA1 [39,40] RE4325 1@ 2 10K_0402_5%
APU_LPC_RST# 22 EIO3/LAD3/GPM3(3) SMDAT1/GPC2 117 EC_SMB_CK2 ENBKL RE4324 1@ 2 100K_0402_5%
[8,13]
[8]
APU_LPC_RST#
CLK_PCI_EC RE31 1 2 0_0402_5% CLK_PCI_EC_R 13 ERST#/LPCRST#/GPD2
ESCK/LPCCLK/GPM4(3)
PECI/SMCLK2/GPF6(3)
SMDAT2/PECIRQT#/GPF7(3)
118 EC_SMB_DA2 EC_SMB_CK2
EC_SMB_DA2
[22]
[22]
Thermal sensor, APU=>PD
RE32 1 2 0_0402_5% LPC_FRAME#_R 6 EC_FAN_PWM RE4327 1@ 2 10K_0402_5%
+3VL_EC [8] LPC_FRAME# ECS#/LFRAME#/GPM5(3) EC_FAN_SPEED
RE4372 1 2 0_0402_5%
STATUS# [27] RE4328 1 2 10K_0402_5%

QWLAN@ +3VALW
DE2 @1 2 P_APU_OCPL_10 126 RE4371 2 1 0_0402_5%
[44] P_APU_OCPL_10 GA20/GPB5(3) STATUS#_R M2_BT_WAKE#_R [26] EC_PCIE_WAKE#
SERIRQ 5 85 RE4331 1@ 2 10K_0402_5%
[8,13] SERIRQ EC_SMI# ALERT#/SERIRQ/GPM6(3) PS2CLK0/CEC/TMB0/GPF0 PBTN_OUT# WLAN_WAKE#
15 86 2 1 0_0402_5% 1@ 2 10K_0402_5%
RB751V-40_SOD323-2 [7] EC_SMI# EC_SCI# PLTRST#/ECSMI#/GPD4(3)LPC PS2DAT0/TMB1/GPF1 EC_PCIE_WAKE_R# PBTN_OUT# [7] RE27 @ EC_PCIE_WAKE# [7] RE4332
23 PS/2 89
[8] EC_SCI# ECSCI#/GPD3 PS2CLK2/GPF4
RE8 1 2 100K_0402_5% WRST# 14 90 ENBKL
WRST# PS2DAT2/GPF5 ENBKL [16]
KBRST# RE4373 1 2 0_0402_5% 4 RI80 1 2 0_0402_5%
1
CE12
[8] KBRST# KBRST#/GPB6(3)
IT8227E-CX PWM0/GPA0
24 PWR_LED_WIT#
PWR_LED_WIT# [27]
FPR_SCL [34]
EC_3V_USM RE4364 1 2 100K_0402_5%
1U_0402_6.3V6K BATT_CHG_LED# EC_0.75VALW_EN
2
[39] EC_ADP_CTRL RE4369 1 EC_ADP_CTRL_R
2 0_0402_5%
EC_MUTE#
113
123 CRX0/GPC0
LQFP128 PWM1/GPA1
PWM2/GPA2
PWM3/GPA3
25
28
29
30
EC_KB_BKL_EN
BATT_LOW_LED#
BATT_CHG_LED#
EC_KB_BKL_EN
BATT_LOW_LED#
[31]
[31]
[31] FPR_LED_GREEN# GPG2
RE4362

RE4355
1

1@
2 100K_0402_5%

2 100K_0402_5%
[33] EC_MUTE# CTX0/TMA0/GPB2(3) CIR SMCLK5/PWM4/GPA4 PD_VIN_CTRL FPR_LED_GREEN# [27]
31 GPA5 RE4368 1 @ 2 0_0201_5%
SMDAT5/PWM5/GPA5 PD_VIN_CTRL [23] 2_5VEN RE4329 1 2 100K_0402_5%

H_PROCHOT#_EC
PWM 3V_WLAN_EN
80 RE4330 1@ 2 10K_0402_5%
RE342 @1 2 0_0402_5% 119 DAC4/DCD0#/GPJ4(3) 47 EC_FAN_SPEED
[11] EC_RTCRST#_ON EC_VR_ON DSR0#/GPG6 TACH0A/GPD6(3) APU_TS_STOP EC_FAN_SPEED [25]
33 48 BKOFF# RE4334 1 2 10K_0402_5%
[44] EC_VR_ON GINT/CTS0#/GPD5 TACH1A/TMA1/GPD7(3) APU_TS_STOP [16]
EC_0.75VALW_EN 81 120 USB_CHG_EN EC_VR_ON RE4336 1 2 100K_0402_5%
[42] EC_0.75VALW_EN DAC5/RIG0#/GPJ5(3) TMRI0/GPC4(3) USB_CHG_EN [27]
124 SUSP#
EC_TX TMRI1/GPC6(3) SUSP# [32,42,43] EC_RSMRST#
17 RE4339 1@ 2 100K_0402_5%
[26] EC_TX EC_RX TXD/SOUT0/LPCPD#/GPE6
16
[26] EC_RX RXD/SIN0/PWUREQ#/BBO/SMCLK2ALT/GPC7(3) SUSP# RE4337 1 2 100K_0402_5%
ADP_I 71 107 EC_ON_R_5V RE343 1 2 0_0402_5%
[42] 2_5VEN 2_5VEN [40] ADP_I 2_5VEN_R ADC5/DCD1#/GPI5(3) GPE4 PM_SLP_S3# EC_ON_5V [25,41]
RE4353 1 2 0_0402_5% 72 UART port 18
PM_SLP_S3# [7]
SYSON RE4338 1 2 100K_0402_5%
PSYS 73 ADC6/DSR1#/GPI6(3) WAKE UP RI1#/GPD0(3) 21 EC_ON_R_3V RE4315 1 2 0_0402_5% EC_ON_3V#
[40] PSYS USB_ON# ADC7/CTS1#/GPI7(3) RI2#/GPD1
35 CE29 2 1 0.1U_6.3V_K_X5R_0201
[27] USB_ON# RTS1#/GPE5
C [31] EC_TP_OFF#
EC_TP_OFF# 34
PWM7/RIG1#/GPA7 EC_3V_USM_R
For EMC C
SYSON 122 112 RE4363 1 2 0_0402_5% @
EC_SMB_DA3 DTR1#/SBUSY/GPG1/ID7 RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7 ON/OFF_R EC_3V_USM [41]
95 110 RE326 1 2 0_0402_5%
[42] EC_SMB_DA3 EC_SMB_CK3 CTX1/SOUT1/GPH2/SMDAT3/ID2 PWRSW/GPB3 APU_THERMTRIP#_RRE328 1 ON/OFF [27]
PMIC 94 111 2 0_0402_5%
[42] EC_SMB_CK3 CRX1/SIN1/SMCLK3/GPH1/ID1 GPB4 LID_SW# APU_THERMTRIP# [6] +3VL_EC
109
EC_SPI_CLK GPB1 LID_SW# [25]
Please do not place any pull-up resistor 105 108 ACPRN
[8] EC_SPI_CLK EC_SPI_CS1# FSCK GPB0
101 GPG2 RE4351 1 2 100K_0402_5%
on GPG0, GPG2, and GPG6 (Reserved [8] EC_SPI_CS1# EC_SPI_SI 102 FSCE# RE341 1 @ 2 0_0201_5%
hardware strapping). [8] EC_SPI_SI EC_SPI_SO FMOSI EXTERNAL SERIAL FLASH WLAN_WAKE#_R WLAN_WAKE# [26] LID_SW#
103 66 RI30171 FP@ 2 0_0402_5% RE4323 1 2 100K_0402_5%
KSO[0..17] [8] EC_SPI_SO FMISO ADC0/GPI0(3) 67 BATT_TEMP FPR_DELINK [8,34]
[31] KSO[0..17] ADC1/GPI1(3) NTC_V1 BATT_TEMP [39,40] +CAPS_LED#
KSO16 56 68 NTC_V1 [25] RE4366 1 2 100K_0402_5%
KSO17 57 KSO16/SMOSI/GPC3(3) ADC2/GPI2(3) 69 CHG_MOD3_R RE4359 1 2 0_0402_5%
EC_FAN_PWM KSO17/SMISO/GPC5(3) ADC3/GPI3(3) 3V_WLAN_EN_R RE4308 1 @ CHG_MOD3 [27] NUM_LED#
32 70 2 0_0201_5% RE4367 1 @ 2 100K_0402_5%
[25] EC_FAN_PWM PWM6/SSCK/GPA6 ADC4/GPI4(3) 3V_WLAN_EN [26]
GPG2 100 A/D D/A RI3018 1 2 0_0402_5% @
SSCE0#/GPG2 PMIC_PWR_EN [42]
TE4 @ 1 GPG0 125 SPI ENABLE EMC_NS@ EMC_NS@
SSCE1#/GPG0 76 EC_PD_INT# CLK_PCI_EC RE103 1 2 10_0402_5%CE48 1 2 10P_0201_25V8G
TACH2A/GPJ0 PM_SLP_S5# EC_PD_INT# [22]
SYSON RE99 1 2 0_0402_5% KSO0 36 77
1_2VEN [42] KSO0/PD0 TACH2B/GPJ1 VR_PWRGD PM_SLP_S5# [7,13] APU_LPC_RST#
KSO1 37 78 CE49 EMC_NS@ 1 2 220P_25V_K_X7R_0201
KSO1/PD1 DAC2/TACH0B/GPJ2(3) EC_ON_APU VR_PWRGD [44]
KSO2 38 79
KSO2/PD2 DAC3/TACH1B/GPJ3(3) EC_ON_APU [32] BATT_TEMP
KSO3 39 CE31 @ 1 2 100P_50V_J_NPO_0201
KSO4 40 KSO3/PD3
KSO5 41 KSO4/PD4 APU_THERMTRIP# CE44 @ 1 2 100P_50V_J_NPO_0201
KSO6 42 KSO5/PD5
KSO7 43 KSO6/PD6 LID_SW# CE34 EMC_NS@ 1 2 0.1U_6.3V_K_X5R_0201
KSO8 44 KSO7/PD7
S145API 0~17 KSO9 45 KSO8/ACK# VR_PWRGD CE46 @ 1 2 0.01U_6.3V_K_X7R_0201
KSO10 46 KSO9/BUSY
KSO11 51 KSO10/PE 2 APUALW_PWRGD APUALW_PWRGD CE50 @ 1 2 0.1U_6.3V_K_X5R_0201
KSO11/ERR# GPJ7 AC_PRESENT APUALW_PWRGD [42]
KSO12 52 CLOCK 128
KSO12/SLCT GPJ6 AC_PRESENT [7]
KSO13 53 ON/OFF CE57 @ 1 2 0.1U_6.3V_K_X5R_0201
RE324 1 2 0_0402_5% KSO14 54 KSO13 org: EC_APU_ALWEN enable 1.8VALW/0.75VALW
[40] VR_HOT# APU_PROCHOT# [6] KSO14
KSO15 55 84 NUM_LED# Now:Separater enable 0725
KSI[0..7] KSO15 KBMX EGCLK/GPE3 EC_APU_ALWEN_R RE11 NUM_LED# [31]
83 1 2 0_0402_5%
EGCS#/GPE2
2

H_PROCHOT#_EC RE325 1 2 0_0402_5% [31] KSI[0..7] 82 CHG_MOD1_R RE4358 1 2 0_0402_5% EC_1.8VALW_EN [42]
1 EGAD/GPE1
KSI0 58 CHG_MOD1 [27] +3VL_EC
RE323 CE43 KSI1 59 KSI0/STB#
KSI1/AFD#
AC IN
100_0402_5% 47P_25V_J_NPO_0201 KSI2 60 19 FPR_AL0 ACPRN RE25 1 2 100K_0402_5%
2 KSI2/INIT# SMCLK4/L80HLAT/BAO/GPE0 FP_EC_PWRON FPR_AL0 [34]
@ EMC_NS@ KSI3 61 20
1 1

KSI4 62 KSI3/SLIN# SMDAT4/L80LLAT/GPE7 FP_EC_PWRON [34] 1 2 0_0402_5%

GPIO RE26
KSI4 DCIN_ATTACHED_EC ACIN [40]
D KSI5 63 3
H_PROCHOT#_EC KSI5 GPH7 NOV_BTN# DCIN_ATTACHED_EC [39]
2 @ KSI6 64 99 DE1 22 11 @ RB751VM-40TE-17_UMD2M2
KSI6 ID6/GPH6 NOV_BTN# [27]
G QE3 KSI7 65 98 BKOFF#
KSI7 ID5/GPH5 +CAPS_LED# BKOFF# [16]
L2N7002KWT1G_SOT323-3 97
ID4/GPH4 EC_SYS_PWRGD +CAPS_LED# [31]
S 96 1 2 CE14 100P_50V_J_NPO_0201

VCORE
EC_SYS_PWRGD [7]
3

ID3/GPH3 EC_RSMRST#_R RE4350 1

AVSS
93 2 0_0402_5%

VSS1
VSS2
VSS3
VSS4
VSS5
CLKRUN#/ID0/GPH0 EC_RSMRST# [7]
@

1
27
49
91
104

75

12
B FP_EC_PWRON B
RE4365 1 2 100K_0402_5%

VCOREVCC
+3VALW
RPE9
1 4 KSO1 EC_AGND 2
Close EC
2 3 KSO2
CE3
10K_0404_4P2R_5% 0.1U_6.3V_K_X5R_0201
1
@ TE1 @ 1 KSI7
TE2 @ 1 KSI6
RPE9 Reserve for vender suggest 5/30 TE3 @ 1 WRST#

+5VALW
DE6
RE4352 1 @ 2 ALW_PWRGD_R @1 2 EC_RSMRST#
[41] ALW_PWRGD
0_0402_5%
RB521CS-30GT2RA_VMN2-2 +3VL_EC +3VL_EC +3VL_EC +3VALW
2

RE4343

2
100K_0201_5%

2
+3VL RE4347 RE4340 RE4346
RE4374 100K_0201_5% 100K_0201_5% 100K_0402_5%
1

100K_0201_5% @
@

1
2

1
RE311 PMIC_PWR_EN EC_ON_5V EC_1.8VALW_EN
100K_0201_5% EC_ON_3V [41]

2
1

@
RE4375 RE4344 RE4345
100K_0402_5% 100K_0402_5% 100K_0402_5%
1

@ @ @

1
Q19
SSM3K15AMFV_2-1L1B
EC_ON_3V# 2
3

@
2

A RE312 A
S550-ARE EC_ON_3V# LOW Valid, 100K_0201_5%
add this circuit 0806
1

RE102
1 2

0_0402_5%

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 EC ITE8586LQFP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 30 of 45
5 4 3 2 1
 5 4 3 2 1

K/B Connector KB Backlight Connector Follow yogo530-ARR Change BL Control 07/28

JP1 ME@
RI53 1 2 0_0402_5% PWR_CAPS/NUM_LED 1 Change QI1 (SB00000QP0J) to RI9 07/28
+3VALW 1 2 200_0402_1% CAPS_LED#_R 2 1
RI15
[30] +CAPS_LED# 2 RI10
KSO15 3
KSO10 4 3 1 LED_KB_C
2 1/10W_0_5%_0603 +5VS +VCC_KB_LED
KSO11 5 4
KSI[0..7] KSO14 6 5
KSI[0..7] [30] 7 6 1 RI9
KSO13
KSO[0..17] KSO12 8 7 D 1 2 1/10W_0_5%_0603
KSO[0..17] [30] 9 8 1 2 0_0201_5% 2
KSO3 RI1
KSO6 10 9 [30] EC_KB_BKL_EN
1 G
KSO8 11 10

0.1u_0201_10V6K
S 1
11

1
12

100K_0402_5%
KSO7 CI8 BL@
KSO4 13 12 RI62 3 Q8 BL@ CI6
KSO2 14 13 2 PJA138K_SOT23-3 0.1u_0201_10V6K
100P 25V J NPO 0201 EMC_NS@ 2 1 CI1 PWR_CAPS/NUM_LED KSI0 15 14 BL@ BL@ 2
KSO1 16 15

2
D
KSO5 17 16 D

100P 25V J NPO 0201 EMC@ 2 1 CI2 CAPS_LED#_R KSI3 18 17

KSI2 19 18
KSO0 20 19
DI1 EMC@ KSI5 21 20
KSI4 22 21
2 1 KSO9 23 22
2 1 KSI6 24 23
KSI7 25 24
AZ5123-01F.R7GR_DFN1006P2X2 KSI1 26 25 +VCC_KB_LED ME@
KSO16 27 26
KSO17 28 27 6
DI9 EMC@ RI54 1 2 200_0402_1% NUM_LED#_R 29 28 5 GND2
[30] NUM_LED# 30 29 GND1
2 1 NUM_LED#_R RI79 1 2 0_0402_5% PWR_Fnlk/Mute/Mic_LED 31 30 35 4
2 1 +3VALW Fnlk_LED# 32 31 GND2 36 3 4
33 32 GND1 2 3
33 1 2
AZ5123-01F.R7GR_DFN1006P2X2 34 LED_KB_C 1
34 CI9 1
DI10 EMC@ 0.1u_0201_10V6K @
HIGHS_FC8AF341-3201H 2 HIGHS_FC1AF040-1201H
2 1 Fnlk_LED# JKBL
2 1
7/11 Update JKBL1 symbol follow S550-ICL
AZ5123-01F.R7GR_DFN1006P2X2 Fellow S550 Intel sit for EMC require 0925

Fnlk_LED# +3VALW

1
RI72
300_0402_5%

2
RI73
RI76 1 2 0_0402_5% 1 2 Fnlk_LED#

1
D 200_0402_1%
FN_LED# 2 Q14
[9] FN_LED# G 2N7002KW_SOT323-3

1
1 @ S

3
RI78
C CI32 100K_0402_5% C
EMC@
2 100P_50V_J_NPO_0201 @

2
TP Power control,

+3VALW TO TP_PWR
MAX 0.1A
+3VS TP_PWR
RI34
1 2 1/10W_0_5%_0603

0.1U_6.3V_K_X5R_0201
1

CI23
2
Remove TP MS Circuit
TP Power Follow S145 API 07/26

TP_PWR

EC_TP_OFF# RI21 1@ 2 10K_0402_5%

B B

TP/B Connector

JTP
RI3 1 2 0_0402_5% EC_TP_OFF#_R 1
[30] EC_TP_OFF# TP_INT# 1
RI4 1 2 0_0402_5% 2
[7] PCH_TP_INT# 3 2
4 3
5 4
Remove RI5/RI6, use levelshift channel 07/28 TP_I2C3_SDA 6 5
TP_I2C3_SCL 7 6
8 7
TP_PWR 8

100P 25V J NPO 0201

100P 25V J NPO 0201

0.1U_6.3V_K_X5R_0201
EMC_NS@

EMC_NS@
1 1 1 9
10 GND1
GND2

CI30
TP_I2C3_SCL HIGHS_FC5AF081-2931H
2 2 2

CI4

CI5
ME@
TP_I2C3_SDA

1
1

1
+3VALW DI2 DI3
AZ5123-01F.R7GR_DFN1006P2X2 AZ5123-01F.R7GR_DFN1006P2X2
LED1 EMC_NS@ EMC_NS@ TP_PWR
TP_PWR

2
1 2 300_0402_5% 1 2 R143
[30] BATT_LOW_LED#

2
1
L-C192JFCT-LCFC_SUPER_AMBER
RPI1
+3VALW
2.2K_0404_4P2R_5%

5
G

3
4
LED2

1 2 300_0402_5% 1 2 R144
[30] BATT_CHG_LED# TP_I2C3_SDA_R TP_I2C3_SDA
RI7 1 2 0_0402_5% 3 4

S
[7,13] TP_I2C3_SDA_R

D
L-C192WDT-LCFC_WHITE QI5B

2
A 2N7002KDWH_SOT363-6 A

G
BATT_CHG_LED# TP_I2C3_SCL_R RI8 1 2 0_0402_5% 6 1 TP_I2C3_SCL

S
[7,13] TP_I2C3_SCL_R

D
QI5A
BATT_LOW_LED# 2N7002KDWH_SOT363-6
1

LED Stute LED Behavior

1

D18 D19 EMC_NS@

Battery only OFF AZ5123-01F.R7GR_DFN1006P2X2
EMC_NS@ AZ5123-01F.R7GR_DFN1006P2X2
Charge LED
2

Amber_on(battery： 1%~90%) Title

Charging
Security Classification LC Future Center Secret Data
2

White_on(battery： 91%~100%)
Issued Date 2016/08/16 Deciphered Date 2017/08/15 KBD/PWR/IO/LED/TP Conn.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
SVT Modify D19 From az5725 to AZ5123 Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 31 of 45
5 4 3 2 1
 A B C D E

Load Switch +3VS, C173 --> 2.74ms

+5VLP +5VALW
+5VALW To +5VS +5VS, C176 --> 2.03ms
+3VALW To +3VS VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=16mohm
+3VALW +3VS

1
UX3
J11 @
RX9 RX10 +3VS_LS
1 14 1 2
100K_0402_5% 100K_0402_5% RX16 1 2 0_0402_5% 3VSON IN1_1 OUT1_2 1 2
2 13
@ IN1_2 OUT1_1
1 JUMP_43X79 1 CX11
3VSON 3 12 CX9 1 2 2200P_25V_K_X7R_0402 Need Short
2

2
1 EN1 CT1 @ 0.1u_0201_10V6K 1
CX14
SUSP 1U_0402_6.3V6K
[17] SUSP +5VALW 4 11
2 @ VBIAS GND 2
SUSP# RX17 1 2 0_0402_5% 5VSON
5VSON 5 10 CX12 1 2 1000P_50V_K_X7R_0201
+5VALW EN2 CT2 +5VS
1 6 9 J12 @
D 1 1 IN2_1 OUT2_2 +5VS_LS
7 8 1 2
2 QX1 IN2_2 OUT2_1 1 2
[30,42,43] SUSP# G CX16
L2N7002KWT1G_SOT323-3 CX15
0.1u_0201_10V6K 1U_0402_6.3V6K 1 15 JUMP_43X79 1
Thermal Pad CX10
S CD@ 2 2 Need Short @ 0.1u_0201_10V6K
CD@ CX13
3

1U_0402_6.3V6K G2898KD1U_TDFN14P_2X3
2 2

For DisCharge APU Power control

+3VALW TO +3VALW_APU
SB00000QP0J LP2301ALT1G 1P SOT-23-3 MAX 0.25A
Load MOS N MOS Id =< -1.6A, Vgs(th) Max >= 1V
+3VS +5VS Vds max 20V, Vgs Max ±8V,Rds(on) >= 150mohm +3VALW 3VS Modify +3VALW 0726 +3VALW_APU
2 2
@
+3VALW RX18 1 2 1/2W_0.01_1%_0603_50PPM/C
1

RX24 RX25 LP2301ALT1G_SOT23-3

+3VL RX19
470_0603_5% 470_0603_5%
+3VALW_M

D
@ +3VALW Modify +3VL 726 QX5 3 1 1 2 1/10W_0_5%_0603

1
2

RX20
100K_0201_5%

G
2

0.1U_6.3V_K_X5R_0201
RX21

2
1

D D 1 2 EC_ON_APU 1
QX7 2 SUSP QX8 2 SUSP
2N7002KW_SOT323-3 G 2N7002KW_SOT323-3 G RX22 4.7K_0402_5%

1
0_0402_5% D 1 CX17
S S EC_ON_APU 1 2 2 QX6 2
[30] EC_ON_APU
3

G L2N7002KWT1G_SOT323-3 CX19
@

1
@ 0.1U_6.3V_K_X5R_0201
RX23 S 2

3
100K_0201_5%
@

2
@

3 3

AON6324
VDS=30V VGS=+_12V, ID=85A,
Rds=2.8mohm @ VGS=10V
+0.75VALW QX3 +0.75VS +/- 5% 2A VGS(th)=2.25V Max
+/- 2% AON6324_DFN8-5

1
2 1 1
1 5 3 CX5
0.01U_6.3V_K_X7R_0201

CX3 CX4 1U_0402_6.3V6K

10U_0603_6.3V6M 10U_0603_6.3V6M
1

@ 2 2
1 1
4

2 CX6 CX7 RX11

0.1U_6.3V_K_X5R_0201 470_0603_5%
@ @ @
2 2
B+
2

RX13 RX14 Change RX14 130K to 768K For QX3 GS 0819

+0.75VS_GATE_R 1 2 0_0402_5% 1 20.75VS_GATE 1 2
RX12 0_0402_5%
768K_0402_1%
1

1 D D
4 CX8 RX15 2 QX2 SUSP 2 QX4 4
0.01U_25V_K_X5R_0201 1M_0402_5% G L2N7002KWT1G_SOT323-3 G L2N7002KWT1G_SOT323-3
@
2 S S
2

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 DC V TO VS INTERFACE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 32 of 45
A B C D E
 5 4 3 2 1

HDA_BITCLK_AUDIO
[7] HDA_BITCLK_AUDIO
HDA_SYNC_AUDIO
[7] HDA_SYNC_AUDIO
HDA_SDOUT_AUDIO
[7] HDA_SDOUT_AUDIO
HDA_SDIN0
[7] HDA_SDIN0

AUDIO_DMIC_CLK
[16] AUDIO_DMIC_CLK
AUDIO_DMIC_DATA
[16] AUDIO_DMIC_DATA

D EC_MUTE# D
[30] EC_MUTE#

PCH_BEEP
[7] PCH_BEEP

+1.8V_AUDIO
ADD Reserved ALW Power(DVDD/+5VA/+5VALW) 07/28 DVDD DVDD_IO +5VD +5VA
Analog power for DACs, ADCs

+5VD
Note: DVDD-IO must be equal to or smaller than DVDD

0.1U_6.3V_K_X5R_0201

2.2U_0402_6.3V6M
+5VA
2 2

CA1

CA2
+3VALW DVDD_IO +3VS DVDD 1 1

18

46

41

40

20
3
RA1 1 @ 2 0_0402_5% RA2 1 2 0_0402_5% +1.8VS +1.8V_AUDIO UA1

CPVDD/AVDD2
PVDD2

PVDD1

AVDD1
DVDD-IO
DVDD
+1.8VS RA3 1 2 0_0402_5%

2.2U_0402_6.3V6M

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
1 2 SPKR_MUTE#

10U 6.3V M X5R 0402

RA4 1 @ 2 0_0402_5% 2 1 2

CA3
PDB

CA5

CA6 CD@
+1.8VALW

CA4
+1.8VALW 14 HDA_BITCLK_AUDIO
RA5 1 @ 2 0_0402_5% HPOUT_L 27 BCLK
2 1 HPOUT-L
RA6 1 2 0_0402_5% 1 2 15 HDA_SYNC_AUDIO
HPOUT_R 26 SYNC
HPOUT-R 47 7/11-Sense by software,RA8 change from 200K to 0R,RA7 unstuff
MIC2_VREFOL 28 JD2 RA7 2 @ 1 100K_0402_1%
MIC2-VREFO-L PLUG_IN +3VS
48 JSENSE RA8 1 2 0_0402_5%
MIC2_VREFOR 29 JD1
MIC2-VREFO-R
Close to Pin7 1
SPDIF-OUT/GPIO2/DMIC-DATA34/DMIC-CLK-IN
4 DMIC_DATA_R RA9 1 2 0_0402_5% AUDIO_DMIC_DATA
RING2_CONN 30 GPIO0/DMIC-DATA12
MIC2-L/RING2 5 DMIC_CLK_R RA10 1 2 0_0402_5% AUDIO_DMIC_CLK
RING3_CONN 31 GPIO1/DMIC-CLK
MIC2-R/SLEEVE 6
+5VS PC_BEEP 34 I2C-DATA
+5VA +5VS +5VD PCBEEP 7
I2C-CLK
+5VA
RA11 1 2 0_0402_5% LA1 1 2 EMC_NS@ 8
BLM15PD600SN1D_2P RA12 1 2 10K_0402_5% VDD_STB 33 NC1
5VSTB
0.1U_6.3V_K_X5R_0201

1U_0402_6.3V6K

9
RA13 NC2

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
2 2 1 1 2 2 LINE2-R 35
LINE2-R
CA9

CA10

CA11

CA12

CA13
1 2 1/10W_0_5%_0603 10
NC3
CA8

C LINE2-L 36 C
LINE2-L 11
1 1@ 2 2 1 1 NC4
12
NC5

CA14 1 2 1U_0402_6.3V6K CBP 23 45 SPK_R+

CBP SPK-OUT-R+
CBN 24 44 SPK_R-
CBN SPK-OUT-R-
43 SPK_L-
SPK-OUT-L-
42 SPK_L+
2.2U_0402_6.3V6M 2 1 CA15 MIC2-CAP32 SPK-OUT-L+
MIC2-CAP 13
2.2U_0402_6.3V6M 2 1 CA16 VREF 38 DC DET/EAPD
VREF
2.2U_0402_6.3V6M 1 2 CA17 LDO3-CAP19 16 SDATA_IN RA14 2 1 33_0402_5% HDA_SDIN0
LDO3-CAP SDATA-IN
EC_MUTE# SPKR_MUTE# 2.2U_0402_6.3V6M 1 2 CA18 LDO2-CAP21 17 HDA_SDOUT_AUDIO HDA_SDOUT_AUDIO
LDO2-CAP SDATA-OUT
1

2.2U_0402_6.3V6M 1 2 CA19 LDO1-CAP39

RA15 LDO1-CAP 25 CPVEE
RA16 1 2 0_0402_5% 10K_0402_5% CPVEE

Thermal Pad
2
@ CA20
1U_0402_6.3V6K

AVSS1

AVSS2
2

ALC3287-CG_MQFN48_6X6

37

22

49
DA2
@ RA18
PCH_BEEP 2 1PC_BEEP1 1 2PC_BEEP1_R CA22 1 2 0.1U_6.3V_K_X5R_0201 PC_BEEP

LRB751V-40T1G_SOD323-2 4.7K_0402_5%
1

RA19
10K_0402_5%
RA20 1 2 0_0402_5% @
Speaker
2

JSPK

SPK_R+ LA2 1 2 BLM15PX800SN1D_2P SPK_R+_CONN 1

SPK_R- LA3 1 2 BLM15PX800SN1D_2P SPK_R-_CONN 2 1
SPK_L+ LA4 1 2 BLM15PX800SN1D_2P SPK_L+_CONN 3 2 5
SPK_L- LA5 1 2 BLM15PX800SN1D_2P SPK_L-_CONN 4 3 GND1 6
4 GND2
B B

2200P_25V_K_X7R_0201

2200P_25V_K_X7R_0201

2200P_25V_K_X7R_0201

2200P_25V_K_X7R_0201

220P_25V_K_X7R_0201

220P_25V_K_X7R_0201

220P_25V_K_X7R_0201

220P_25V_K_X7R_0201
HIGHS_WS33041-S0191-HF

CA27

CA28

CA29

CA30
AUDIO_DMIC_CLK ME@

CA23 EMC@

CA24 EMC@

CA25 EMC@

CA26 EMC@
2 2 2 2 2 2 2 2
EMC_NS@
HDA_BITCLK_AUDIO_R 1 2 HDA_BITCLK_AUDIO AUDIO_DMIC_DATA
For EMC Near CODEC

CD@

CD@

CD@

CD@
RA28 1/16W_27_5%_0402
1 1 1 1 1 1 1 1
100P 25V J NPO 0201

100P 25V J NPO 0201

EMC@

EMC_NS@

1 1
33P_50V_J_NPO_0201

CA31

CA32
EMC_NS@

1
CA35

2 2

2 RA22 1 2 0_0402_5%

1 2 0_0402_5%
RA27

RA38 1 2 0_0402_5%

RA29 1 2 0_0402_5%
RING3_CONN
RING2_CONN
A_HP_OUTL_R
Audio Jack
A_HP_OUTR_R
PLUG_IN GND GNDA JHP

MIC2_VREFOL RA30 2 1 2.2K_0402_5% RING2_CONN 3 G/M

HPOUT_L A_HP_OUTL_R
AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

RA32 1 2 56_0402_5% 1
L
1

PLUG_IN
47P_25V_J_NPO_0201

LINE2-L CA37 1 @ 2 1U_0402_6.3V6K 5

5
EMC_NS@

1 DA3 DA4 DA5 DA6 DA7 RA31 CA39

1

1
CA38

0_0402_5% 470P_50V_K_X7R_0201 LINE2-R CA40 1 @ 2 1U_0402_6.3V6K 6

2A_HP_OUTL_R_C 1 A_HP_OUTL_R 6
EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC@

1 @ 2 @
HPOUT_R RA34 1 2 56_0402_5% A_HP_OUTR_R 2
2 R
MIC2_VREFOR RING3_CONN
2

RA36 2 1 2.2K_0402_5% 4
M/G
2

100P 25V J NPO 0201

100P 25V J NPO 0201

100P 25V J NPO 0201

100P 25V J NPO 0201

7

CA42

CA43

CA44

CA45
RA35 CA41 MS
1 2 1 1
0_0402_5% 470P_50V_K_X7R_0201
1 @ 2A_HP_OUTR_R_C 1 2 @ A_HP_OUTR_R ATOB_063-RT04-0601

For EMI ME@

EMC@

EMC@
2@ 1@ 2 2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 Codec & CR_RTS5199
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 33 of 45

5 4 3 2 1
 5 4 3 2 1

FP Power control,follow T14

Jevon@190617 +3VALW TO +3V_FPR
For ESD
SB00000QP0J LP2301ALT1G 1P SOT-23-3 +3V_FPR
Load MOS N MOS Id =< -1.6A, Vgs(th) Max >= 1V
+3VALW +3V_FPR
close to Conn
Vds max 20V, Vgs Max ±8V,Rds(on) >= 150mohm

1
+3VL RI39 1 @ 2 1/2W_0.01_1%_0603_50PPM/C RI85
+3VL 330_0402_1%
D EMC_NS@ D
1 2 1/2W_0.01_1%_0603_50PPM/C

200K_0402_1%
RI58 DI11

1
@ FPR_DELINK_R 10 1 FPR_DELINK_R

2
NC1 Line-1

RI83
FPR_AL0_R 9 2 FPR_AL0_R FP@
FP@
NC2 Line-2
LP2301ALT1G_SOT23-3 FPR_RESET_R 7 4 FPR_RESET_R

2
RI59 NC3 Line-3
FP@

0.047U_0402_25V_X7R_0402

1
FPR_SCL_R FPR_SCL_R

D
QI10 3 1 1 2 1/10W_0_5%_0603 6 5 QI12

1U_0402_6.3V6K
NC4 Line-4

0.1U_6.3V_K_X5R_0201
1

1
3

CI35

CI36
RI42 1
100K_0201_5% FP@ @ RI61 GND1 FPR_PWR_EN# 2

G
2
FP@ 0_0402_5% 8

2
2
RI43 1 2 0_0402_5% 2 1 2 FP_EC_PWRON CI26 GND2 SSM3K15AMFV_2-1L1B

3
FPR_PWR_EN# 2 AZ1143-04F-R7G_DFN2510P10E10
FP@
@
1

QI11 1
CI28
FP_EC_PWRON 2 0.1U_6.3V_K_X5R_0201
[30] FP_EC_PWRON 2@
FP@ SSM3K15AMFV_2-1L1B
3

C C

FPR_RESET_R

1
+3VS
Q16
RI63 @ 1/20W_2.2K_5%_0201 SSM3K15AMFV_2-1L1B
RI27 1 2 0_0402_5% 1 2 FPR_DELINK FPR_RESET 2

3
+3V_FPR RI67
LI2 @
USB20_N7 1 2 USB20_N7_CONN 10K_0402_5%
[9] USB20_N7 1 2 RI64 2 1 FPR_AL0
@ 1/20W_4.7K_5%_0201 @

2
USB20_P7 4 3 USB20_P7_CONN
[9] USB20_P7 4 3
RI65 2 1 FPR_RESET_R
EXC24CH900U_4P
@ 1/20W_4.7K_5%_0201
EMC_NS@
+3V_FPR
RI28 1 2 0_0402_5% RI81 2 1 FPR_SCL
@ 1/20W_4.7K_5%_0201
B
1
CI31
FPR CONN B

0.1U_6.3V_K_X5R_0201
FP@
2
USB20_N7_CONN +3V_FPR
Follow E14 now no connect APU&EC ,Tracking 07/30 JFP
USB20_P7_CONN 1
USB20_N7_CONN 2 1
2
AZ5725-01F.R7GR_DFN1006P2X2

USB20_P7_CONN 3
3
1

DI8 4
4
AZ5425-01F.R7GR DFN1006P2E

EMC_NS@

FPR_DELINK RI55 1 2 0_0402_5% FPR_DELINK_R 5

1
AZ5425-01F.R7GR DFN1006P2E

[8,30] FPR_DELINK 5
1

DI6 DI7 FPR_AL0 RI56 1 2 0_0402_5% FPR_AL0_R 6

[30] FPR_AL0 6
EMC@

EMC@

FPR_RESET RI57 1 2 0_0402_5% FPR_RESET_R 7

1

[8]
FPR_SCL FPR_RESET FPR_SCL_R 7
RI3019 1 2 0_0402_5% 8
[30] FPR_SCL 8

1/20W_47K_1%_0201
1

1
2

RI84
GND1

1
RI66 10
2

GND2
2

1/20W_4.7K_5%_0201 RI82
@ @ HIGHS_FC5AF081-2931H
2

ME@

2
100K_0201_5%

2
A A
FP@

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 Finger Print

DI6/DI7 SC400006510
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 34 of 45
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 Power sequence Block
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 35 of 45
5 4 3 2 1
 5 4 3 2 1

Hole

SH1 SH2 SH3

NH1 H2 1 1 1
HOLEA HOLEA 1 1 1

1
SHIELDING_SUL-15A3M_6X1P2_1P SHIELDING_SUL-15A3M_6X1P2_1P SHIELDING_SUL-15A3M_6X1P2_1P
ME@ ME@ ME@
D SH4 D
SH5
SH6
pad_c2p5d2p5n pad_ct7p0d2p5
@ @ 1
1 1
1 1
1

H4 H5 H6 H7
HOLEA HOLEA HOLEA HOLEA SHIELDING_SUL-15A3M_6X1P2_1P
SHIELDING_SUL-15A3M_6X1P2_1P
ME@ SHIELDING_SUL-15A3M_6X1P2_1P
ME@
ME@
SH7
SH8
1

1
SH9
1
1 1
1 1
1

PAD_C7P0D3P3 PAD_C7P0D3P3 PAD_C7P0D3P3 PAD_C7P0D3P3

@ @ @ @ SHIELDING_SUL-15A3M_6X1P2_1P
SHIELDING_SUL-15A3M_6X1P2_1P
ME@ SHIELDING_SUL-15A3M_6X1P2_1P
ME@
ME@
SH10
H8
HOLEA
1
1
1

SHIELDING_SUL-15A3M_6X1P2_1P
ME@
PAD_C6P0D2P5
@ MEMORY SHELDING
H9
HOLEA

C C
1

PAD_C7P0D3P3 PCB Fedical Mark PAD

@

FD1 FD2

H10
HOLEA

1
@ @
1

FD3 FD4

1
pad_ct7p0d3p7x3p2
@ @ @

FD5 FD6

NH11

1
HOLEA
@ @
1

pad_o2p5x3p0d2p5x3p0n
@

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Hole

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 36 of 45
5 4 3 2 1
 5 4 3 2 1

SVT Upgrate PCB to 1.0

PCB Modify DA800015610 _20200117 SVT Build 20200117
SVT PCB upgrade to 1.0, pcb update to pingban PN DAZ1NK00100 _20200120
APU type Modify R5_S1S1@ For new add 4511C31210R,4511C31210S_20200119 PCB ZZZ12 HDMI@

UC1 R7_PR@ UC1 R5_PR@ UC1 R3_PR@ ZZZ0 PCB@

HDMI Lable
RO00000040J
S IC RYZEN 100-000000371 1.8G BGA 1140 PR S IC RYZEN 100-000000375 2.1G BGA 1140 PR S IC RYZEN 100-000000376 2.6G BGA 1140 PR PCB 27J NM-D701 REV0 M/B
DA800019300
SA0000B9A10 SA0000B9B10 SA0000B9C10

20191227 New build

DRAM X76 BOM:SAM DRAM X76 BOM Micron DRAM X76 BOM:HYNIX

ZZZ1 RAM_S8G@ ZZZ2 RAM_S12G@ ZZZ3 RAM_S16G@ ZZZ4 RAM_S4G@ ZZZ5 RAM_M8G@ ZZZ6 RAM_M12G@ ZZZ7 RAM_M16G@ ZZZ8 RAM_H8G@ ZZZ9 RAM_H12G@ ZZZ10 RAM_H16G@

Samsung Samsung Samsung Samsung Micron Micron Micron HYNIX HYNIX HYNIX
X764CE12002
X764CE12004 X764CE12007 X764CE1200A X764CE12005 X764CE12008 X764CE12006 X764CE12009
X764CE12001 X764CE12003

ID[0~1], 00 :S 01:M 10:H 11:NEW hynix

D
CONFIGURE ID[2~3], 00 :4G 01:8G 10:16G 11:12g SDP OR DDP D

UD1 MD_S16Gb@ UD2 MD_S16Gb@ UD3 MD_S16Gb@ UD4 MD_S16Gb@ UD5 MD_S16Gb@ UD6 MD_S16Gb@ UD7 MD_S16Gb@ UD8 MD_S16Gb@ RC35 MD_S16Gb@ RC36 MD_S16Gb@ RC37 MD_S16Gb@ RC41 MD_S16Gb@

1 SAMSUNG 16G 3200 SDP

K4AAG165WA-BCWE K4AAG165WA-BCWE K4AAG165WA-BCWE K4AAG165WA-BCWE K4AAG165WA-BCWE K4AAG165WA-BCWE K4AAG165WA-BCWE K4AAG165WA-BCWE 2K +-5% 0402 2K +-5% 0402 2K +-5% 0402 2K +-5% 0402
SA0000AC020 SA0000AC020 SA0000AC020 SA0000AC020 SA0000AC020 SA0000AC020 SA0000AC020 SA0000AC020 SD02820018J SD02820018J SD02820018J SD02820018J
00 10

UD1 MD_NH16Gb@ UD2 MD_NH16Gb@ UD3 MD_NH16Gb@ UD4 MD_NH16Gb@ UD5 MD_NH16Gb@ UD6 MD_NH16Gb@ UD7 MD_NH16Gb@ UD8 MD_NH16Gb@
RC42 MD_NH16Gb@ RC43 MD_NH16Gb@ RC37 MD_NH16Gb@ RC41 MD_NH16Gb@
2
new Hynix 16G 3200 SDP
H5ANAG6NCJR-XNC H5ANAG6NCJR-XNC H5ANAG6NCJR-XNC H5ANAG6NCJR-XNC H5ANAG6NCJR-XNC H5ANAG6NCJR-XNC H5ANAG6NCJR-XNC H5ANAG6NCJR-XNC
SA0000B5K10 SA0000B5K10 SA0000B5K10 SA0000B5K10 SA0000B5K10 SA0000B5K10 SA0000B5K10 SA0000B5K10 10K_0402_5% 10K_0402_5% 2K +-5% 0402 2K +-5% 0402
SD02810028J SD02810028J SD02820018J SD02820018J
10 10

UD1 MD_M16G@ UD2 MD_M16G@ UD3 MD_M16G@ UD4 MD_M16G@ UD5 MD_M16G@ UD6 MD_M16G@ UD7 MD_M16G@ UD8 MD_M16G@ RC35 MD_M16G@ RC43 MD_M16G@ RC37 MD_M16G@ RC41 MD_M16G@

3
MT40A1G16KD-062E:E MT40A1G16KD-062E:E MT40A1G16KD-062E:E MT40A1G16KD-062E:E MT40A1G16KD-062E:E MT40A1G16KD-062E:E MT40A1G16KD-062E:E MT40A1G16KD-062E:E
Micron 16G 3200 2K +-5% 0402 10K_0402_5% 2K +-5% 0402 2K +-5% 0402
SDP
SA0000ADK00 SA0000ADK00 SA0000ADK00 SA0000ADK00 SA0000ADK00 SA0000ADK00 SA0000ADK00 SA0000ADK00 SD02820018J SD02810028J SD02820018J SD02820018J
01 10

UD1 MD_S8Gb@ UD2 MD_S8Gb@ UD3 MD_S8Gb@ UD4 MD_S8Gb@ UD5 MD_S8Gb@ UD6 MD_S8Gb@ UD7 MD_S8Gb@ UD8 MD_S8Gb@ RC35 MD_S8Gb@ RC36 MD_S8Gb@ RC44 MD_S8Gb@ RC48 MD_S8Gb@

4 Samsung 8G3200 SDP

K4A8G165WC-BCTD K4A8G165WC-BCTD K4A8G165WC-BCTD K4A8G165WC-BCTD K4A8G165WC-BCTD K4A8G165WC-BCTD K4A8G165WC-BCTD K4A8G165WC-BCTD 2K +-5% 0402 2K +-5% 0402 10K_0402_5% 10K_0402_5%
SA0000AC810 SA0000AC810 SA0000AC810 SA0000AC810 SA0000AC810 SA0000AC810 SA0000AC810 SA0000AC810 SD02820018J SD02820018J SD02810028J SD02810028J
00 01

UD1 MD_M8Gb@ UD2 MD_M8Gb@ UD3 MD_M8Gb@ UD4 MD_M8Gb@ UD5 MD_M8Gb@ UD6 MD_M8Gb@ UD7 MD_M8Gb@ UD8 MD_M8Gb@ RC35 MD_M8Gb@ RC43 MD_M8Gb@ RC44 MD_M8Gb@ RC48 MD_M8Gb@

5
Micron 8G 3200 SDP
MT40A512M16TB-062E:J MT40A512M16TB-062E:J MT40A512M16TB-062E:J MT40A512M16TB-062E:J MT40A512M16TB-062E:J MT40A512M16TB-062E:J MT40A512M16TB-062E:J MT40A512M16TB-062E:J 2K +-5% 0402 10K_0402_5% 10K_0402_5% 10K_0402_5%
SA00009R510 SA00009R510 SA00009R510 SA00009R510 SA00009R510 SA00009R510 SA00009R510 SA00009R510 SD02820018J SD02810028J SD02810028J SD02810028J
01 01
RC42 MD_NH8Gb@
UD1 MD_NH8Gb@ UD2 MD_NH8Gb@ UD3 MD_NH8Gb@ UD4 MD_NH8Gb@ UD5 MD_NH8Gb@ UD6 MD_NH8Gb@ UD7 MD_NH8Gb@ UD8 MD_NH8Gb@ RC43 MD_NH8Gb@ RC44 MD_NH8Gb@ RC48 MD_NH8Gb@

6 new Hynix 8G 3200 10K_0402_5%

SDP
H5AN8G6NCJR-XNC H5AN8G6NCJR-XNC H5AN8G6NCJR-XNC H5AN8G6NCJR-XNC H5AN8G6NCJR-XNC H5AN8G6NCJR-XNC H5AN8G6NCJR-XNC H5AN8G6NCJR-XNC SD02810028J 10K_0402_5% 10K_0402_5% 10K_0402_5%
SA0000AT510 SA0000AT510 SA0000AT510 SA0000AT510 SA0000AT510 SA0000AT510 SA0000AT510 SA0000AT510 SD02810028J SD02810028J SD02810028J
10 01

10 01
C C

4GB 8GB
UD1 MD_S12G@ UD2 MD_S12G@ UD3 MD_S12G@ UD4 MD_S12G@ UD5 MD_S12G@ UD6 MD_S12G@ UD7 MD_S12G@ UD8 MD_S12G@ RC35 MD_S12G@ RC36 MD_S12G@ RC37 MD_S12G@ RC48 MD_S12G@

7
SAMSUNG 12G 3200 SDP +SDP
K4AAG165WA-BCWE K4AAG165WA-BCWE K4AAG165WA-BCWE K4AAG165WA-BCWE K4A8G165WC-BCTD K4A8G165WC-BCTD K4A8G165WC-BCTD K4A8G165WC-BCTD 2K +-5% 0402 2K +-5% 0402 2K +-5% 0402 10K_0402_5%
SA0000AC810 SA0000AC810 SA0000AC810 SA0000AC810 SA0000AC020 SA0000AC020 SA0000AC020 SA0000AC020 SD02820018J SD02820018J SD02820018J SD02810028J

MD_NH12Gb@
UD1 MD_NH12Gb@ UD2 MD_NH12Gb@ UD3 MD_NH12Gb@ UD4 MD_NH12Gb@ UD5 UD6 MD_NH12Gb@ UD7 MD_NH12Gb@ UD8 MD_NH12Gb@ RC48 MD_NH12Gb@
RC42 MD_NH12Gb@ RC43 MD_NH12Gb@ RC37 MD_NH12Gb@
8
new Hynix 12G 3200 SDP +SDP
H5ANAG6NCJR-XNC H5ANAG6NCJR-XNC H5ANAG6NCJR-XNC H5ANAG6NCJR-XNC H5AN8G6NCJR-XNC
H5AN8G6NCJR-XNC H5AN8G6NCJR-XNC H5AN8G6NCJR-XNC 10K_0402_5%
SA0000AT510 SA0000AT510 SA0000AT510 SA0000AT510 SA0000B5K10 SA0000B5K10 SA0000B5K10 SA0000B5K10 10K_0402_5% 10K_0402_5% 2K +-5% 0402 SD02810028J
SD02810028J SD02810028J SD02820018J
MD_M12G@
UD1 MD_M12G@ UD2 MD_M12G@ UD3 MD_M12G@ UD4 MD_M12G@ UD5 MD_M12G@ UD6 MD_M12G@ UD7 MD_M12G@ UD8 MD_M12G@ RC35 MD_M12G@ RC43 MD_M12G@ RC37 MD_M12G@ RC48

Micron 12G 3200 SDP +SDP

MT40A1G16KD-062E:E MT40A1G16KD-062E:E MT40A1G16KD-062E:E MT40A1G16KD-062E:E H5AN8G6NCJR-XNC H5AN8G6NCJR-XNC H5AN8G6NCJR-XNC H5AN8G6NCJR-XNC 2K +-5% 0402 10K_0402_5% 2K +-5% 0402 10K_0402_5%
SA00009R510 SA00009R510 SA00009R510 SA00009R510 SA0000ADK00 SA0000ADK00 SA0000ADK00 SA0000ADK00 SD02820018J SD02810028J SD02820018J SD02810028J

UD1 MD_H12G@ UD2 MD_H12G@ UD3 MD_H12G@ UD4 MD_H12G@ RC42 MD_H12G@ RC36 MD_H12G@ RC37 MD_H12G@ RC48 MD_H12G@
UD5 MD_H12G@ UD6 MD_H12G@ UD7 MD_H12G@ UD8 MD_H12G@

H5ANAG6NCMR-XNC 96P H5ANAG6NCMR-XNC 96P H5ANAG6NCMR-XNC 96P H5ANAG6NCMR-XNC 96P

Hynix 12G 3200 10K_0402_5% 2K +-5% 0402 2K +-5% 0402 10K_0402_5%
SDP +DDP
SA0000AT510 SA0000AT510 SA0000AT510 SA0000AT510 H5ANAG6NCMR-XNC 96P H5ANAG6NCMR-XNC 96P H5ANAG6NCMR-XNC 96P H5ANAG6NCMR-XNC 96P SD02810028J SD02820018J SD02820018J SD02810028J
SA0000AC520 SA0000AC520 SA0000AC520 SA0000AC520

B B

UD1 MD_H16G@ UD2 MD_H16G@ UD3 MD_H16G@ UD4 MD_H16G@ RC42 MD_H16G@ RC36 MD_H16G@ RC37 MD_H16G@ RC41 MD_H16G@
UD5 MD_H16G@ UD6 MD_H16G@ UD7 MD_H16G@ UD8 MD_H16G@

DDP
H5ANAG6NCMR-XNC 96P H5ANAG6NCMR-XNC 96P H5ANAG6NCMR-XNC 96P H5ANAG6NCMR-XNC 96P
Hynix 16G 3200 10K_0402_5% 2K +-5% 0402 2K +-5% 0402 2K +-5% 0402
SA0000AC520 SA0000AC520 SA0000AC520 SA0000AC520 H5ANAG6NCMR-XNC 96P H5ANAG6NCMR-XNC 96P H5ANAG6NCMR-XNC 96P H5ANAG6NCMR-XNC 96P self check ok proto plan page evt
SD02810028J SD02820018J SD02820018J SD02820018J
SA0000AC520 SA0000AC520 SA0000AC520 SA0000AC520
10 10

RC35 MD_M4G@ RC43 MD_M4G@ RC44 MD_M4G@ RC41 MD_M4G@

UD1 MD_M4G@ UD2 MD_M4G@ UD3 MD_M4G@ UD4 MD_M4G@

Micron 4G 3200 SDP A

2K +-5% 0402 10K_0402_5% 10K_0402_5% 2K +-5% 0402
MT40A512M16TB-062E:J MT40A512M16TB-062E:J MT40A512M16TB-062E:J MT40A512M16TB-062E:J SD02820018J SD02810028J SD02810028J SD02820018J
SA00009R510 SA00009R510 SA00009R510 SA00009R510
01 00

MD_S4G@
RC35 MD_S4G@ RC36 RC44 MD_S4G@ RC41 MD_S4G@
UD1 MD_S4G@ UD2 MD_S4G@ UD3 MD_S4G@ UD4 MD_S4G@

SAMSUNG 4G 3200 SDP A

2K +-5% 0402 2K +-5% 0402 10K_0402_5% 2K +-5% 0402
K4A8G165WC-BCWE K4A8G165WC-BCWE K4A8G165WC-BCWE K4A8G165WC-BCWE SD02820018J SD02820018J SD02810028J SD02820018J
SA0000AC810 SA0000AC810 SA0000AC810 SA0000AC810
00 00

UD1 MD_H4G@ UD2 MD_H4G@ UD3 MD_H4G@ UD4 MD_H4G@ RC42 MD_H4G@ RC43 MD_H4G@ RC44 MD_H4G@ RC41 MD_H4G@

HYNIX 4G 3200 SDP A

H5AN8G6NCJR-XNC H5AN8G6NCJR-XNC H5AN8G6NCJR-XNC H5AN8G6NCJR-XNC 10K_0402_5% 10K_0402_5% 10K_0402_5% 2K +-5% 0402
SA0000AT510 SA0000AT510 SA0000AT510 SA0000AT510 SD02810028J SD02810028J SD02810028J SD02820018J
10 00

SDP A_UZQ B_UZQ A_T7 PIN B_T7 PIN CHA CHB

RD233 SDPA@ RD232 SDPA@ RD231 SDPA@ RD228 SDPA@ RD249 SDPB@ RD265 SDPB@ RD239 SDPB@ RD280 SDPB@ RD234 SDPA@ RD275 SDPB@

0_0201_5% 0_0201_5% 0_0201_5% 0_0201_5% 0_0201_5% 0_0201_5% 0_0201_5% 0_0201_5% 0_0201_5% 0_0201_5%
A SD04300008J SD04300008J SD04300008J SD04300008J SD04300008J SD04300008J SD04300008J SD04300008J SD04300008J SD04300008J A

CHB
DDP A_UZQ B_UZQ A_T7 PIN B_T7 PIN CHA
RD233 DDPA@ RD232 DDPA@ RD231 DDPA@ RD228 DDPA@ RD249 DDPB@ RD265 DDPB@ RD239 DDPB@ RD280 DDPB@ RD284 DDPA@ RD285 DDPA@ RD286 DDPA@ RD287 DDPA@ RD289 DDPB@ RD290 DDPB@ RD291 DDPB@ RD292 DDPB@ RD238 DDPA@ RD229 DDPA@ RD257 DDPB@ RD266 DDPB@

1/20W_240_1%_0201 1/20W_240_1%_0201 1/20W_240_1%_0201 1/20W_240_1%_0201 1/20W_240_1%_0201 1/20W_240_1%_0201 1/20W_240_1%_0201 1/20W_240_1%_0201 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0201_5% 1/20W_39_+-5%_0201 0_0201_5% 1/20W_39_+-5%_0201
SD00000WA00 SD00000WA00 SD00000WA00 SD00000WA00 SD00000WA00 SD00000WA00 SD00000WA00 SD00000WA00 SD02800008J SD02800008J SD02800008J SD02800008J SD02800008J SD02800008J SD02800008J SD02800008J SD04300008J SD000021800 SD04300008J SD000021800

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Virtual symbol

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS E 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Wednesday, January 27, 2021 Sheet 37 of 45
5 4 3 2 1
 5 4 3 2 1

Richtek +1.8VS/2A
+5VALW
+5VALW/10A RT8068AZQW
D
Convertor D

FOR +1.8VALW
Sylergy +5VLP/ 100mA SUSP# EN
SY8386B
SY8370C
Converter +3VLP/ 100mA
FOR 3V/5VALW
EC_ON_3V EN

EC_ON_5V EN +3VALW/6A
PGOOD ALW_PWRGD

Two Adaptor
Type-C 95W
Round ADP 65W

+5VALW
C
0.75VALW/4A C

EC_APU_ALWEN EN
TI
Silergy +1.8VALW/2A
BQ25700A LV5028RPC APUALW_PWRGD
B+ B+
Battery Charger PMIC
SYSON EN FOR VDDQ,VTT,VPP VDDQ/10A
Buck-Boost +0.75VALW
+3VALW +1.8VALW
2.5V_EN EN
VDDQ_VPP 500mA

VDDQ
SMBus VDDQ_TX/ 1A
SUSP# EN

VDDQ_PGOOD
PGOOD
Battery
4S1P or 3S1P

B Richtek VDDC_VDD/44A B

RT3663BCGQW
controller VDDCR_SOC/13A
APU_SVI2 VIDs FOR CPU CORE&SOC
EC_VR_ON EN VR_APU_PWRGD
PGOOD

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 Power Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 38 of 45
5 4 3 2 1
 5 4 3 2 1

ME@ EVT_verify PL103 PL104 DFC +ADIN_1 PQ102

+ADIN_2
PQ101
JDCIN1 PL103 AONR21357_DFN8 AONR21357_DFN8 PL101
HIGHS_PJSSR26-D1005-1H HCB2012KF-121T50_0805 1 8 8 1 HCB2012KF-121T50_0805 PJ101
1 1 2 +ADIN_1 2 7 7 2 1 2 2 1
1 2
GND1 3 EMC@ 3 6
5
6
5
3 EMC@
2 1
@ +CHARGER_IN
JUMP_43X79
GND2 4 PL104 PL102
GND3 5

1000P_0402_50V_X7R_0402

1000P_0402_50V_X7R_0402
HCB2012KF-121T50_0805 HCB2012KF-121T50_0805

402K_0402_1%

402K_0402_1%
4

4
GND4 6

1
1 2 1 2
GND5 7

1
PR101

PC105

PR119

PC111
GND6 EMC@ EMC@
100P_50V_J_NPO_0201

100P_50V_J_NPO_0201
D D
EMC_NS@

EMC_NS@

22U_B2_25VM_R100M
2

2
1 1 1

200K_0402_1%

2
1
PC112

PC113

100P_0402_50V8J

100P_0402_50V8J
1000P_0402_50V_X7R_0402

1000P_0402_50V_X7R_0402
PC101EMC@

PC102EMC@

PC103EMC@

PC104EMC@
+

PR116

PC115
1

1
100K_0402_1%

100K_0402_1%
2 2

499K_0402_1%
1

1
2

2
PR102

PR103

PR121
@

300K_0402_1%
1 Vdiv=6.66V
2 1
PR114 Vin：4.8V~9V~20V

2
PR117
Vth：0.8V~1.5V~3.33V

2
100K_0402_1%
2

L2N7002KDW1T1G_SOT363-6

L2N7002KDW1T1G_SOT363-6
RC：8.3us RC：10ms （Vth）

3
RC：4.5ms Vdiv=3.03V DCIN_ATTACHED 18.3ms（Vend） 2 D D
PC123
1 3 1 2 5 1000P_0402_50V_X7R_0402

PQ106A

PQ106B
DCIN_ATTACHED_EC [30]
G G 1 2

0.1U_25V_K_X5R_0402
C_AD in,then plug A_AD in PR104 PDCHG@
0.1U_25V_K_X5R_0402

1000P_0402_50V_X7R_0402
PQ107 100K_0402_1% S S

100K_0402_1%
53.6K_0402_1%

notice EC A_AD plug in

4
2

1
SSM3K15AMFV_2-1L1B PR128
1

1
1.EC set limit for A_AD 1 2
PC110

PR115

PC106

PR105

PC109
2.EC notice PD close C_AD SW
402K_0402_1%
2

2
PDCHG@
1

2
PQ117

1
2
3
SSM3K15AMFV_2-1L1B

SSM3K15AMFV_2-1L1B
PR129

1
4 1 2 1 3

PQ103
2
100K_0402_5%

PD_VBUS_C_CTRL1_R
PDCHG@ PDCHG@

2
AONR21357_DFN8

PD_VBUS_C_CTRL1_R
8
7
6
5
PQ109
type C 95W pull high
+PD_LDO_3V3
otherS pull low

SSM3K15AMFV_2-1L1B
1
C SW_ON_EN Low to ACK Low：16ms C

PQ108
SW_Off_EN High to ACK High：4us

100K_0402_1%

1
EC_ADP_CTRL 2
[30] EC_ADP_CTRL

PR108
100K_0402_1%
1

3
PR123

PU101

2
PD_VBUS_C_CTRL1_EN#
2

1
Open drain LOW_ON HIGH_OFF D1
VINT4 C1

PQ105
PR120 1U_25V_K_X5R_0402

SSM3K15AMFV_2-1L1B
100K_0402_1% A3 VINT3 B1 PC108
2 1 2 EN# VINT2 A1 2 1
[22] PD_VBUS_C_CTRL1 VINT1
E3
GND3

1
D3 E2
+VBUS_CONN

1M_0402_5%

3
C3 GND2 VBUS5 E1

PR122
PR118 1 2100K_0402_1% GND1 VBUS4 D2
+PD_LDO_3V3 VBUS3
A2 C2
[22] PD_ACK_SNK1 ACK VBUS2

1
B3 B2 2 1

2
OVLO VBUS1

PQ104
SSM3K15AMFV_2-1L1B
OVLO short to GND PC107
DCIN_ATTACHED 2 1U_25V_K_X5R_0402
Vovlo set to 23V NX20P5090UK_WLCSP15

3
BATT+
JBATT5
1
2 1
PR112 1 2 100_0402_1% EC_SMCA 3 2
[30,40] EC_SMB_CK1 EC_SMDA 3
PR113 1 2 100_0402_1% 4
[30,40] EC_SMB_DA1 BATT_TEMP 4
B 5 B
[30] BATT_TEMP 5
9 6
GND1 10 7 6
GND2 11 8 7
GND3 12 8
GND4
HIGHS_WS33081-S120C-1H
ME@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 DCIN / RTC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 39 of 45
5 4 3 2 1
 A

+ADIN_R B+

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

EMC@

EMC@
0.1U_25V_K_X5R_0402

0.1U_25V_K_X5R_0402
5

5
1 1 1 1 1 1 1 1

1
PQ301

PQ304

PC300

PC301

PC302

PC303

PC304

PC305

PC337

PC338

PC339

PC340
AON6324_DFN8-5

AON7380_DFN8-5

2
2 2 2 2 2 2 2 2
4 4
3CELL_52.5W,B+ 12.6V,1C 4.76A
4CELL_70W，B+16.8V,1C 4.76A
+CHARGER_IN 6.0mohm/12A/18A

3
2
1

1
2
3
PQ305
PR300 AON7405_DFN8-5 BATT+
0.01_1206_1% PL300 2.2UH_CMMB103T-2R2MS_13.2A_20% 1
PR303
1 4 1 2 2 PL302
switch frequency is 800kHZ 3 5 1 4 1 2
2 3 HCB2012KF-121T50_0805
for 2.2UH inductor
10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
22U_B2_25VM_R100M

0.1U_25V_K_X5R_0402
EMC@
1 1 1 1 1 2 3 EMC@

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
1

0.047U_0402_25V_X7R_0402
EMC_NS@

5
PC306

PC307

PC308

PC309

PC312

4.7_0603_5%

100P_0402_50V8J
4
1
0.047U_0402_25V_X7R_0402

EMC_NS@
+

PQ302

PQ303
PL303
PC341

PR301
Ciss lower than 5nF 1 1

4.7_0603_5%
D
AON6324_DFN8-5
0.01_1206_1%

1
AONR32340C_DFN8-5
1 2

PC313

PC314

PC321

PC322

PC317
@ SRN close to Batt+

1_0603_5%
2
2 2 2 2 HCB2012KF-121T50_0805

PR304

PR302
2
EMC@

2
700_LG14 4700_LG2 2 2

2
G

2
S1
S2
S3
1

1
1/16W_4.99_1%_0402

1/16W_4.99_1%_0402
PC323

2
EMC_NS@
1 2

PR305

PR306

0_0402_5%

0.1U_25V_K_X5R_0402

0.1U_25V_K_X5R_0402
3
2
1

1
2
3
1

1
EMC_NS@
PR309

PR307

PC316
0_0402_5% 0.1U_25V_K_X5R_0402

PC315
2

0.1U_25V_K_X5R_0402

0.1U_25V_K_X5R_0402
1

1
PU300
BQ25700ARSNR_QFN32_4X4

0.47U_0402_25V6K
0.033U_25V_K_X7R_0402

0.033U_25V_K_X7R_0402

1
PC326

PC327
700_BTST1 30 25 700_BTST2
1 BTST1 BTST2
1

1
PC319

PC320

PC324

2
700_PH1 32 23 700_PH2
SW1 SW2
2

2
2 700_LG1 29 26 700_LG2
LODRV1 LODRV2 CHRG_GND CHRG_GND

700_BATDRV
700_UG1 31 24 700_UG2
HIDRV1 HIDRV2 PC325 1 2 0.1U_25V_K_X5R_0402
700_VBUS 1 22
CHRG_GND CHRG_GND VBUS VSYS
700_ACN 2 21 700_BATDRV_N PR308 2 1 0_0402_5%
REGN
ACN BATDRV#
REGN 700_ACP 700_SRP
PR311 3 20 PR310 2 1 1/16W_10_1%_0402
10_0603_5% ACP SRP
1 2 700_VDDA 7 19 700_SRN PR312 2 1 1/16W_10_1%_0402
174K_0402_1% VDDA SRN
divide voltage 2.79V IDPM Set 4.47A for 95W
REGN

1/16W_82K_1%_0402
PR313
divide voltage 2.2V IDPM Set 3A for 65W

33.2K_0402_1%
1

1
1 2 700_ILIM 6 28 PC329 1 2 2.2U_10V_K_X5R_0603
ILIM_HIZ REGN

PR315

PR334
PC330 1 21800P_50V_K_X7R_0402 PR314 1 2 40.2K_0402_1% PC331 1 2 15P_0402_50V8J +3VL
100K_0402_1%
1U_0402_10V6K

700_COMP116 17 700_COMP2
CHRG_GND COMP1 COMP2 CHRG_GND
1

PC332 1 2 33P_0402_50V8J PR316 2 1 10K_0402_1% PC333 2 1 680P_0402_50V_X7R_0402

PC328

PR317

Reserve @

2
75%_4CELL

100K_0402_1%
55%_3CELL

1
PR318 2 1 0_0402_5% 700_PROCH11 18 700_PRES
[30] VR_HOT#
2

A PROCHOT# CELL_BATPRES PC334 1 2 100P_0402_50V8J

A

PR330
OD:+3VS_APU_Pull High CHRG_GND
2

1
PR319 2 1 0_0402_5% 700_SCL 13 PR320 2 1 0_0402_5%
[30,39] EC_SMB_CK1 SCL ADP_I [30]

1
8 700_IADP PR326 1 2 137K_0402_1%

PQ307
+3VL_Pull High

100K_0402_1%

SSM3K15AMFV_2-1L1B
700_SDA IADPT CHRG_GND
PR321 2 1 0_0402_5% 12

PR322
[30,39] EC_SMB_DA1

2
CHRG_GND SDA 9 700_IDCHG PC336 1 2 100P_0402_50V8J 2
700_CHGOK 4 IBAT CHRG_GND charger reads inductance through BATT_TEMP [30]
PR323 2 1 0_0402_5%
[30] ACIN CHRG_OK PR326 before the converter starts up

1
10 700_PSYS PC335 1 2 100P_0402_50V8J
OD:+3VL_Pull High

1M_0402_1%
CHRG_GND

3
PR328 2 1 100K_0402_1% 700_OTG 5 PSYS PR324 2 1 0_0402_5%

PR333
CHRG_GND EN_OTG PSYS [30]
Pull low disable OTG function 27 PR327 1 2 30K_0402_1% CHRG_GND
15 PGND
CMPOUT Vpsys=Psys_ratio*30K 1W=0.03 V
33 CHRG_GND

2
14 PAD
CMPIN

CHRG_GND

PJ300
1 2

JUMPER
@

CHRG_GND

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 PWR_Charger

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 40 of 45
A
 A B C D

PJ6201
2 1
+3VLP 2 1 +3VL
3V5V_VIN +5VLP +3VLP JUMP_43X39 1A

@
Vout=5V+-5%
Vset=5.06V+-1.5%

0.1U_25V_K_X5R_0402
1
FSW=500KHz

PC6201
3V5V_VIN 1 1 TDC=10A OCP=16A

PC6203

PC6204
4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
B+ 3V5V_VIN

1
1
2 1

62K_0402_1%

24K_0402_1%
OVP=Vout*113%

PR6201

PR6214
PJ6202 +3VALW 2 2 UVP=Vout*52%
2 1
2 1

2
10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
JUMP_43X118

0.1U_25V_K_X5R_0402

0.1U_25V_K_X5R_0402
+3V5V_CS2

+3V5V_CS1

+5VLP

+3VLP
1 1 1 1 1 1

2
PC6206

PC6207

PC6208

PC6209

PC6210

PC6211
PR6215
+5VALW

EMC_NS@

EMC_NS@
100K_0402_1%
Vout=3.3V+-5%
2 2 2 PU6201 2 2 2
Vset=3.3V+-1.5%

12

13
5

5
PQ6201

1
FSW=600KHz

5
AONR32340C_DFN8-5 PQ6203

CS2

CS1

LDO5

LDO3
VIN
21 AON7380_DFN8-5
TDC=8A OCP=13A

D
+3VALW GND

1
[30] ALW_PWRGD 7
PGOOD
OVP=Vout*113% PJ6207

1
16 +5V_UG 4
UGATE1 JUMP_43X118
1

UVP=Vout*52% G
4 +3V_UG 10
UGATE2
PR6207

2
PJ6206 PR6206 2.2_0603_5% PC6213
1

+5V_BST1 2+5V_BST_R1

@
PC6212 2.2_0603_5% 17 2 1.5UH_PCMB063T-1R5MS_10A_20%

S1
S2
S3
JUMP_43X118

2
1.5UH_PCMB063T-1R5MS_10A_20% 1 2 +3V_BST_R 1 2 +3V_BST 9 BOOT1

3
2
1
BOOT2 RT6585CGQW_WQFN20_3X3 PL6202
2

0.1U_25V_K_X5R_0402
8A

1
2
3
PL6201
@

0.1U_25V_K_X5R_0402 18 +5V_LX 1 2 +5VALW_P

8A
2

+3VALW_P 1 2 +3V_LX 8 PHASE1

PHASE2

@
1/8W_4.7_5%_0805
5

2
+5V_LG

EMC_NS@
15

330P_0402_50V_X7R_0402
PQ6202

1/8W_4.7_5%_0805
LGATE1

2
+3V_LG 11

EMC_NS@

PR6208

330K_0402_1%
0.01U_0402_25V_X7R_0402330P_0402_50V_X7R_0402
AONR32340C_DFN8-5 PJ6203

AON6380_DFN8-5
LGATE2

SKIPSEL

1
JUMPER @

PR6210
14

1/16W_680K_1%_0402
JUMPER

1
BYP1

1
PQ6204
PJ6204

PR6220

PC6232
220U_B2_6.3VM_R25M

22UC_6.3VC_MC_X5RC_0603

EN2

EN1
1

FB2

FB1
PC6214

PR6209
@
22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

1
1

+5V_FB_R
PC6221

+5V_LX_R

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
1

2
1

1
PC6215

PC6216

PC6217

PC6218

PC6219

PC6220

PC6222

20

2
19
G

1
+ +3V_FB_R
PC6237

PC6224

PC6225
+3V_LX_R
2

2
@ +5V_LX_R2

0.01U_0402_25V_X7R_0402
1000P_50V_J_COG_0402
S1
S2
S3
2

EMC_NS@
1000P_50V_J_COG_0402

3
2
1

2
1

2
2

+3V5V_CLK
+3V_LX_S

PC6226

PC6233
13K_0402_1%

30K_0402_1%

0.1U_25V_K_X5R_0402
2

1
2
3
2

1
EMC_NS@

PR6212
0.1U_25V_K_X5R_0402

2 @

1
PR6211

PC6228

PC6229
@

2 2

2
@

+5V_FB
PC6227

@
2
1
1

PC6230

1
1 @
@

2
+3V_FB +5V_FB
2

100K_0402_5%
[30] EC_ON_3V

1
PR6216 1 2 EC_ON_3V_R
PR6219
20K_0402_1% PR6202 0_0402_5% Vout=2V*(1+PR6212/PR6217)

1M_0402_5%
1 2

0.1u_0201_10V6K
PR6217
1 +3VLP
1

PC6202

PR6204
19.6K_0402_1%

2
Vout=2V*(1+PR6211/PR6216) 2

1
@
PR6221
PQ6205 2 EC_USM_R 2 1
SSM3K15AMFV_2-1L1B

3
PR6203 0_0402_5%
[25,30] EC_ON_5V 2 1 EC_ON_5V_R EC_USM_S

220U_B2_6.3VM_R25M

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
1

1
1M_0402_5%
1

1
0_0402_5%

PR6205

PC6231

PC6234

PC6235

PC6236
0.1u_0201_10V6K
1 PR6213
EC_3V_USM [30]

PC6205
+

PC6238
1K_0402_5%

2
2

2
2 2
@

@
3 3

RT6585C RT6575D&TPS51275B
Mode DEM/USM USM/CCM
3V FSW 600K 355K
5V FSW 500K 300K
CSx Rlimit=(Ilimit*Rdson)*8/50uA Rlimit=(Ilimit*Rdson)*8/10uA

RT6585B&TPS51285B BOM to BOM

RT6575D&TPS51275B BOM to BOM
4
RT6585B&RT6575D PIN to PIN, with different work mode, FSW, and CS setting 4

Security Classification LCFC Highly Confidential Information Title

S540-TGL
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PWR_3VALW/5VALW
Date: Tuesday, November 03, 2020 Sheet 41 of 45
A B C D
 5 4 3 2 1

LV5075_VCC
PR1901 0_0402_5%
PR1907 1 2 10_0603_5% 1 2
+5VLP PMIC_PWR_EN [30]

PC1902 2 1 2.2U_10V_K_X5R_0603 PC1903 1 2 0.1U_10V_K_X5R_0402

@

0.75VALW enable after EC communicate with PMIC, PR1909 1 2 10_0402_5%

D
avoid 0.75VALW defalut 1V power on +1.2V_B+ D

LV5075_PMIC_EN
LV5075_VSYS
PC1901 1 2 1U_25V_K_X5R_0402

PR1913 0_0402_5%
1 2 LV5075_0.75VALW_EN
[30] EC_0.75VALW_EN

28

27

41
9
PR1923 1 2 100K_0402_5%

PMIC_EN
VCC

GND
VSYS
PR1925 0_0402_5%
PR1928 1 2 10K_0402_1% 29 25 LV5075_EC_SMB_DA2 1 2
EN_LDO1 SDA EC_SMB_DA3 [30]
PR1908 0_0402_5% PR1926 0_0402_5%
1 2 LV5075_1.8VALW_EN LV5075_2.5V_EN 1 26 LV5075_EC_SMB_CK2 1 2
[30] EC_1.8VALW_EN EN_LDO2 SCL EC_SMB_CK3 [30]

LV5075_LX_0.75VALW
LV5075_0.75VALW_EN 11
OD pull high 3VL support 1.8V SPI mirror code 24

LV5075_LX_1.8VALW
EN_V1P0A OT
PC1906 1 2 0.1U_10V_K_X5R_0402 LV5075_1.8VALW_EN 16 22 PR1927 2 1 100K_0402_5%
@
EN_V1P8A PG_V1P0A +3VALW

22UC_6.3VC_MC_X5RC_0603
LV5075_VDDQ_EN 31 21 APUALW_PWRGD
EN_VDDQ PG_V1P8A APUALW_PWRGD [30]
PJ1901 LV5075_VTT_EN 36 23
EN_VTT PG_VDDQ

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
PR1902 0_0402_5% 1 2 LV5075_0.75VALW_VIN

[30] 1_2VEN
1 2 LV5075_VDDQ_EN +5VALW 1 2
@ LV5075_LX_0.75VALW
PL1901
+0.75VALW_P
PJ1902
SYSON-1_2VEN JUMP_43X39 1 LX_V1P0A1
12 1 2 2
2 1
1
+0.75VALW

2
EMC_NS@

EMC_NS@
7 13 0.47UH_PCMB063T-R47MS_18A_20%

PC1910
@

4.7_0603_5%

4.7_0603_5%
8 VIN_V1P0A1 LX_V1P0A2 14 JUMP_43X79
VIN_V1P0A2 LX_V1P0A3 1 1 1 1

22UC_6.3VC_MC_X5RC_0603
PC1909 1 2 0.1U_10V_K_X5R_0402 15

PC1912

PC1913

PC1914

PC1915

PR1918

PR1919
2 LX_V1P0A4
@ PJ1903 10

1
1 2 LV5075_V1.8VALW_VIN VO_V1P0A 2 2 2 2
PR1911
1
0_0402_5%
2 LV5075_2.5V_EN
+5VALW 1 2
@ 1
17 LV5075_LX_1.8VALW
JUMP_43X39 PL1902 PJ1904

PC1918
[30] 2_5VEN LX_V1P8A1 +1.8VALW_P
EC-2_5VEN 19
VIN_V1P8A LX_V1P8A2
18 1 2 2
2 1
1
+1.8VALW

680P_0402_50V_X7R_0402

680P_0402_50V_X7R_0402
EMC_NS@

EMC_NS@
1UH_PH041H-1R0MS_3.8A_20% @

1
2 20 JUMP_43X79
1.8VALW:

PC1930

PC1931
VO_V1P8A

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
PC1904 1 2 0.1U_10V_K_X5R_0402
C @ +1.2V_P
1 1 APU_VDD18=2A(TDC) C
+1.2V_P TDC=3A

2
LV5075_UG_1.2V
→ 38
33

PC1920

PC1921
2 UGATE_VDDQ
SUSP#
PR1904
1
0_0402_5%
2 LV5075_VTT_EN PC1924 VIN_VTT 32 LV5075_BST_1.2V
PC1925
1 2
OCP=6A
[30,32,43] SUSP# BS_VDDQ 2 2 OVP=120%
← 39
10U_0603_6.3V6M
1
VTT
.1U_0603_25V_X7R_0603 Fsw=1M
34 LV5075_LX_1.2V
PJ1905 LX_VDDQ
PC1908 1 2 0.1U_10V_K_X5R_0402
1 2 +0.6VS_P 40 35 LV5075_LG_1.2V
@
+0.6VS 1 2
@
VSNS_VTT LGATE_VDDQ

22UC_6.3VC_MC_X5RC_0603
JUMP_43X39 PR1917 37 +1.2V_P
1 2 LV5075_CS 30 VSNS_VDDQ
CS_VDDQ
1 1/16W_33K_1%_0402
Rocset=Rdson*Ivalley*12/Iocset 5

PC1926
6
VIN_LDO1 LDO1
2

3
4 LDO2 +2.5V
+3VALW VIN_LDO2
FB_LDO2
2

10U_0603_6.3V6M
2

24.9K_0402_1%
1
PU1901

PC1935
2

10U_0603_6.3V6M
LV5028RPC_QFN40_5X5
2.5V:

PC1934

PR1920
1 TDC=1A
1 FB=0.75V

2
+2.5V_FB

10.5K_0402_1%
PR1921
2
B B

+1.2V_B+
PJ1908
+1.2V_B+ 2 1
2 1
@ B+
JUMP_43X39

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
EMC@
0.1U_25V_K_X5R_0402
1 1

1
5

PC1929
PQ1901

PC1932

PC1933
D

AONR32340C_DFN8-5

2
2 2

LV5075_UG_1.2V 4
G
+1.2V_P

S3
S2
S1
PL1903
0.47UH_PCMB063T-R47MS_18A_20% PJ1911

3
2
1
LV5075_LX_1.2V 1 2 +1.2V_P 2 1
2 1
@ +1.2V

2
JUMP_43X118

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
PR1922

PQ1902
AON7380_DFN8-5
1/8W_4.7_5%_0805
EMC_NS@ 1.2V:
1 1 1 1
TDC=10A

1
LV5075_LG_1.2V 4

PC1937

PC1938

PC1939

PC1940
OCP=15~18A（Rocset by HW pin）

1
PC1943
680P_0402_50V_X7R_0402 2 2 2 2 OVP=120%
Fsw=1M
EMC_NS@

3
2
1

2
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 PWR_DDR/+1.8V/+0.75VALW

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 42 of 45
5 4 3 2 1
 A B C D

1 1

+3VALW

100K_0402_1%
2
PL2101

PR2101
2 PJ2101 1UH_PH041H-1R0MS_3.8A_20% PJ2102 2

+5VALW
2
2 1
1 +1.8VS_VIN +1.8VS_LX 1 2 +1.8VS_P 2
2 1
1 +1.8VS

EMC_NS@ EMC_NS@
680P_0402_50V_X7R_0402 4.7_0603_5%
10U_0603_6.3V6M

10U_0603_6.3V6M
@ @

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
2
JUMP_43X39 @ JUMP_43X79

PR2102

2200P_25V_K_X7R_0402
1/16W_102K_1%_0402
2 2

PC2101

PC2102

0.1U_25V_K_X5R_0402
4

EMC_NS@

EMC_NS@
68P_0402_50V8J
1

PC2109

PC2108
10 1 1 1

PG

1 1
PVIN2 LX1

1
1 1

PR2103

PC2104

PC2105

PC2106
PC2103
9 2

2
PVIN1 LX2 2

2
8 3 2 2

2
SVIN1 LX3

PR2105
[30,32,42] SUSP# 1 2 +1.8VS_EN 5 6 +1.8VS_FB

GND
EN FB

NC
0.47U_0402_25V6K

1/16W_51K_1%_0402
1/16W_16K_1%_0402 PU2101

7
11
2

1
1M_0402_1%
1 RT8068AZQW_WDFN10_3X3

PR2106

PC2107

PR2104
2

2
3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 PWR_1.8VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 43 of 45
A B C D
 5 4 3 2 1

B+

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
0.1U_25V_K_X5R_0402

22U_B2_25VM_R100M

22U_B2_25VM_R100M
EMC@
1 1 1 1 1

PC5623

PC5624

PC5625

PC5626

PC5627
+ +

5
2 2 2

AON6380_DFN8-5
2 2
D D

PQ5601
P_VDDC_VDD_UG1_30 4

3
2
1
PL5601
0.15UH_CMME063T-R15MS0R905_38A_20%
P_VDDC_VDD_PH1_30 1 2
+VDDC_VDD
@ @

2
1000P_0402_50V_X7R_0402 0_0805_5%
AON6324_DFN8-5

PR5656
PJ5601 PJ5602 Base on 25W config
JUMPER JUMPER
APU_VDDCR

1
PQ5602
FSW=400KHz

2
P_VDDC_VDD_LG1_30 4 Slew rate:12.5mv/us

1
PR5657 TDC=44A EDC=70A
2K_0402_1% OCP=105A

PC5628
OVP=VID+300mV

3
2
1
1.RT3663BH change to RT3663BM Load Line=0.7mohm

2
PC5629
2.VDD chock change to DCR 5% PN

2
1 2 Ripple:+/-20mv
3.PWR_OK sequency confirm VOTFC missing issue change to MAX AC: VID_VDDC +95mv
0.1U_25V_K_X5R_0402
RT3663BM ES 09/27 MP 10/15 MIN AC: VID_VDDC -80mv
P_VDDC_VDD_ISEN1P_10
PU5601 100K_0402_1% 1/16W_2.2_1%_0402
+P_APU_VCC_20 PR5633 PR5632
P_APU_TONSET_10 1 2 2 1
PR5602 1 2 10_0603_5% 28 4 B+
+5VALW VCC TONSET Fsw_Max 413K 1
PC5601 2 1 2.2U_10V_K_X5R_0402 PC5611
0.1U_25V_K_X5R_0402
PR5601 1 2 2.2_0603_5% P_APU_PVCC_20 50 PR5635 PC5612 2
+5VALW PVCC 46 P_VDDC_VDD_BOOT1_30 2 1 2 1 P_VDDC_VDD_PH1_30 P_VDDC_VDD_ISEN1N_10
PC5602 2 1 2.2U_10V_K_X5R_0402 BOOT1
PR5603 47 P_VDDC_VDD_UG1_30 2.2_0603_5% 0.22U_0603_25V_X7R_0603
1 2 PR5604 2 1 100K_0402_1% P_APU_TONSETA_10 40 UGATE1
B+ TONSETA 48 P_VDDC_VDD_PH1_30
1 Fsw_Max 411K PHASE1
1/16W_2.2_1%_0402 PC5603
0.1U_25V_K_X5R_0402 B+

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
0.1U_25V_K_X5R_0402
2
P_VDDCR_SOC_PH1_30 1 2 1 2 P_VDDCR_SOC_BOOT1_30 42 49 P_VDDC_VDD_LG1_30
BOOTA1 LGATE1
P_VDDCR_SOC_UG1_30 1 1 1

PC5630

PC5631

PC5632
EMC@
PC5604 PR5605 43
0.22U_0603_25V_X7R_0603 2.2_0603_5% UGATEA1

5
P_VDDCR_SOC_PH1_30 44
PHASEA1 P_VDDC_VDD_ISEN1P_10 2 2 2

AON6380_DFN8-5
8
ISEN1P
7 P_VDDC_VDD_ISNE1N_R_10 PR5636 2 1 1/16W_732_1%_0402 P_VDDC_VDD_ISEN1N_10
ISEN1N

PQ5603
1 P_VDDC_VDD_UG2_30
PC5613 4
P_VDDCR_SOC_LG1_30 45 0.1U_25V_K_X5R_0402
LGATEA1
PR5637 PC5614 2
2 P_VDDC_VDD_BOOT2_30 2 1 2 1 P_VDDC_VDD_PH2_30

3
2
1
P_VDDCR_SOC_ISEN1P_10 36 BOOT2 PL5602
ISENA1P 1 P_VDDC_VDD_UG2_30 2.2_0603_5% 0.22U_0603_25V_X7R_0603 0.15UH_CMME063T-R15MS0R905_38A_20%
0.1U_25V_K_X5R_0402

P_VDDCR_SOC_ISEN1N_10 1 2 P_VDDCR_SOC_ISNE1N_R_10 35 UGATE2 P_VDDC_VDD_PH2_30 1 2

ISENA1N
PHASE2
52 P_VDDC_VDD_PH2_30 +VDDC_VDD
1 PR5606 @ @

2
1000P_0402_50V_X7R_0402 0_0805_5%
PC5605

1/16W_732_1%_0402

AON6324_DFN8-5

PR5659
PJ5603 PJ5604
51 P_VDDC_VDD_LG2_30
C JUMPER JUMPER C

1
2 LGATE2

PQ5604

2
P_VDDC_VDD_LG2_30 4

1
5 P_VDDC_VDD_ISEN2P_10
41 ISEN2P PR5660
PWMA2 6 P_VDDC_VDD_ISNE2N_R_10 PR5638 2 1 1/16W_732_1%_0402 P_VDDC_VDD_ISEN2N_10 2K_0402_1%

1
ISEN2N

PC5633
1

3
2
1
PC5615

2
PC5634
0.1U_25V_K_X5R_0402

2
1 2
10K_0402_1% 2
PR5671 0.1U_25V_K_X5R_0402
1 2 33
+5VALW ISENA2P 3 P_VDDC_VDD_PWM3_10
NOT USE,Connect to 5VALW PWM3 P_VDDC_VDD_ISEN2P_10
34
ISENA2N
330P_0402_50V_X7R_0402 56P_50V_J_NPO_0402
PC5606 PC5607
1 2 1 2 P_SOC_COMP_10

30
10K_0402_1% 47.5K_0402_1% COMPA 9 P_VDDC_VDD_ISEN3P_10
PR5631 1 2 1/16W_10_1%_0402 1 PR5607 2 1 PR5608 2 ISEN3P
[6] VDDCR_SOC_VCC_SENSE P_VDDC_VDD_ISNE3N_R_10 P_VDDC_VDD_ISEN3N_10 P_VDDC_VDD_ISEN2N_10
10 PR5639 2 1 1/16W_732_1%_0402
ISEN3N
VDDCR_SOC_VSS_SENSE merge with VDDCR_VSS_SENSE P_VDDCR_SOC_FB_10 1
31 PC5616
FBA 0.1U_25V_K_X5R_0402
2
+VDDCR_SOC PR5630 1 2 100_0402_1% 32 PC5617 PC5618
VSENA 13 P_VDDC_VDD_COMP_10 1 2 1 2
COMP
56P_50V_J_NPO_0402 220P_0402_50V_X7R_0402 B+

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
VDD/DOC offset 0mV PR5640 PR5641

0.1U_25V_K_X5R_0402
PR5610 2 @ 1 10K_0402_1% 1 2 1 2
+P_APU_VCC_20
PR5612 1 2 10K_0402_1% P_VDDCR_SOC_OFS_10 24 34.8K_0402_1% 10K_0402_1%
OFSA P_VDDC_VDD_FB_10 1 1 1

PC5636

PC5637
EMC@
12
P_VDDCR_CPU_OFS_10 FB

PC5635
PR5611 2 @ 1 10K_0402_1% 23
+P_APU_VCC_20

5
OFS
2 2 2

AON6380_DFN8-5
PR5613 1 2 10K_0402_1%
PR5677 1 2 40.2_0402_1%
OPR SET VDD/SOC: +P_APU_VCC_20 PR5614 2 1 124K_0402_1% PR5616 2 1 1K_0402_1% P_APU_SET1_10 +VDDC_VDD

PQ5605
PR5618 2 1 20.5K_0402_1% PR5620 2 1 200_0402_1% 25 11 PR5676 1 2 1/16W_10_1%_0402
OCP_TDC≠OCP_SPIKE SET1 VSEN VDDCR_VCC_SENSE [6]
PR5665 4

2
VID up compensate LL 18mv PR5615 1 2 33.2K_0402_1% PR5617 2 1 60.4_0402_1% P_APU_SET2_10 26 2.2_0603_5%
Ramp 100%/QRTH 39mV +P_APU_VCC_20 PR5621 1 2 110_0402_1% PR5619 1 2 1/16W_8.45K_1%_0402 SET2 PC5620 1 2 Driver_VCC PR5666 PC5641
1000P_0402_50V_X7R_0402
+5VALW 4 2 1 1 2
Offset disable

1
PC5640 2 1 1U_0402_10V6K 8 BOOT
OCP trigger delay 10ms

3
2
1
53 14 P_APU_RGND_10 PR5675 1 2 1/16W_10_1%_0402 VCC 3 2.2_0603_5% 0.22U_25V_K_X5R_0402 P_VDDC_VDD_UG3_30 PL5603
GND RGND VDDCR_VSS_SENSE [6] P_VDDC_VDD_PWM3_10 5 UGATE 0.15UH_CMME063T-R15MS0R905_38A_20%
PR5674 1 2 40.2_0402_1% PWM 2 P_VDDC_VDD_PH3_30 1 2
100K（>1%）*20uA=2V, for internal analog circuits
PR5622 1 P_APU_IBIAS_10 2 100K_0402_1% PR5644 1 2 0_0402_5% Driver_VCC PR5667 1 2 0_0402_5% 1
EN
PHASE
P_VDDC_VDD_LG3_30
+VDDC_VDD

EMC_NS@
EC_VR_ON [30] Connect to output Cap GND 7
@ @

2
P_APU_EN_10 LGATE

1000P_0402_50V_X7R_0402 0_0805_5%
Pull up with +1.8VALW follow CRB 29 37 PC5621 1 2 0.1U_10V_K_X5R_0402 6
IBIAS EN GND1

AON6324_DFN8-5

PR5662
PR5623 1 2 2.2_0603_5% 9 PJ5605 PJ5606
+1.8VALW GND2
→18 PH5602 PR5650 JUMPER JUMPER

1
PC5610 2 1 1U_0402_6.3V6K P_APU_VDDIO_20 VDDIO 2 1 2 1 PU5602

PQ5606
Pull up with +1.8VALW follow CRB 1/16W_23.2K_1%_0402 RT9610CGQW_WDFN8_2X2

2
PR5673 1 2 0_0402_5%
→19 PR5649 100K_0402_1%_NCP15WF104F03RC 6.49K_0402_1% 4

1
[6] APU_PWROK PWROK 17 P_VDDCR_SOC_IMON_10 2 1 PR5648 2 1 20K_0402_1%
IMONA

EMC_NS@
20 PR5663

1
[6] APU_SVC SVC

PC5638
PC5647 1 2 @ 0.1U_25V_K_X5R_0402 PH5601 PR5647 2K_0402_1%
21 15 P_VDDC_VDD_IMON_10 2 1 2 1 2 1

3
2
1
[6] APU_SVD 1 2 @ 0.1U_25V_K_X5R_0402 SVD IMON
PC5648

2
22 PC5639
PR5646 100K_0402_1%_NCP15WF104F03RC 12.4K_0402_1%
[6] APU_SVT 1 2 @ 0.1U_25V_K_X5R_0402 SVT
PC5649 7.32K_0402_1% PR5645 2 1 14K_0402_1% 1 2
38
B
PR5628 2 1 10K_0402_1% PGOODA 0.1U_25V_K_X5R_0402 B
+3VS POR,Vdiv=2150mV:current gain ratio 25%
[30] VR_PWRGD ←39 PGOOD
P_APU_V064_20
after POR,V064 clamp voltage =0.64V
P_VDDC_VDD_ISEN3P_10
PR5629 1 @ 2 10K_0402_1% 27 16 2 1 2 1
+1.8VS OCP_L V064/SET3 +P_APU_VCC_20
[30] P_APU_OCPL_10 PR5672 1 @ 2 0_0402_5% PR5651 PR5652

19.6K_0402_1%
330_0402_1% 26.1K_0402_1%

2
RT3663BRGQW_WQFN52_6X6

2
PR5653

PR5654
1 0_0402_5%

P_VDDC_VDD_ISEN3N_10

1
0.022U_0402_25V_X7R_0402

1/16W_340_1%_0402
2
2

PC5622

PR5655
1

B+

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
0.1U_25V_K_X5R_0402
1 1 1

PC5643

PC5644
PC5642

EMC@
5
2 2 2

AON6380_DFN8-5
PQ5607
P_VDDCR_SOC_UG1_30 4

3
2
1
PL5604
0.36UH_PCMB063T-R36MS3R205_20A_20%
P_VDDCR_SOC_PH1_30 1 2
+VDDCR_SOC
@ @

2
1000P_0402_50V_X7R_0402 0_0805_5%
AON6324_DFN8-5
PJ5607 PJ5608

PR5668
JUMPER JUMPER

1
PQ5608

4.75K_0402_1%
P_VDDCR_SOC_LG1_30 4

1
VDDCR_SOC

PR5669
FSW=300KHz

PC5646
Slew rate :12.5mv/us

3
2
1
PC5645 TDC=13A EDC=17A

2
1 2 OCP=26A
OVP=VID+300mA
0.1U_25V_K_X5R_0402 Loadline=2.1mohm
PR5678 Ripple:+/-20mv
P_VDDCR_SOC_ISEN1P_10 1 2 MAX AC: VID_VDDCR_SOC +70mv
MIN AC: VID_VDDCR_SOC -40mv
1/16W_1.87K_1%_0402

A A

P_VDDCR_SOC_ISEN1N_10

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 PWR_VDD/SOC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-15 AMD UMA
Date: Tuesday, November 03, 2020 Sheet 44 of 45
5 4 3 2 1
 A
B
C
D

5
5

@
2
1
+
PC5775
220U 2.5V Y D ESR6M SR H1

@
2
1
PC5770
22UC_6.3VC_MC_X5RC_0603

@
2
1
PC5771
22UC_6.3VC_MC_X5RC_0603

@
2
1
PC5772
22UC_6.3VC_MC_X5RC_0603

@
2
1
PC5773
22UC_6.3VC_MC_X5RC_0603

@
2
1
PC5774
22UC_6.3VC_MC_X5RC_0603

2
1
PC5731
22UC_6.3VC_MC_X5RC_0603

2
1
+VDDC_VDD

PC5732
22UC_6.3VC_MC_X5RC_0603

2
1
PC5733
22UC_6.3VC_MC_X5RC_0603

4
4

2
1
PC5734
22UC_6.3VC_MC_X5RC_0603

2
1
2
1

PC5735 PC5719
22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603

2
1
2
1

PC5736 PC5720
22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603

2
1
2
1

PC5737 PC5721
22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603

2
1
2
1

PC5738 PC5722
22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603
2
1
2
1

PC5739 PC5723
2
1
+

22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603
PC5769
2
1
2
1

330U_2.5V_M_B2_ESR9M_H1.9
@

PC5740 PC5724 2 1
2
1
+

22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603
PC5705 PC5701
2
1
2
1

0.1U_25V_K_X5R_0402 330U_2.5V_M_B2_ESR9M_H1.9
@

PC5741 PC5725 EMC_NS@

2
1
+

22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603 2 1
PC5702
2
1
2
1

PC5706 330U_2.5V_M_B2_ESR9M_H1.9
@

PC5742 PC5726 0.1U_25V_K_X5R_0402

22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603 EMC_NS@
2
1
+

2 1
2
1
2
1

PC5703
@

PC5743 PC5727 PC5707 330U_2.5V_M_B2_ESR9M_H1.9

22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603 0.1U_25V_K_X5R_0402
2
1
+

EMC_NS@
2
1
2
1

2 1 PC5704
@

PC5744 PC5728 330U_2.5V_M_B2_ESR9M_H1.9

22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603 PC5708
0.1U_25V_K_X5R_0402
2
1
2
1

PC5745 PC5729
EMC_NS@
22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603

3
3

2
1
2
1

PC5746 PC5730
22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603

Issued Date
2
1
+VDDCR_SOC

PC5747

Security Classification
22UC_6.3VC_MC_X5RC_0603
2
1

PC5748
22UC_6.3VC_MC_X5RC_0603
2
1
2
1

PC5749 PC5754
22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603
2
1
2
1

PC5750 PC5755
2013/08/15
2
1
+

22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603
PC5768
2
1

470U_D2_2VM_R4.5M
2
2

PC5751
22UC_6.3VC_MC_X5RC_0603
2
1
2
1
2
1
+

PC5752 PC5756 PC5767

22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603 330U_D2_2V_Y
2
1
2
1

PC5753 PC5757
22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603
Deciphered Date
EVT verify DFN

2
1

PC5758
22UC_6.3VC_MC_X5RC_0603
LC Future Center Secret Data
2
1

@
change 2pcs 47uf_0603

PC5759
22UC_6.3VC_MC_X5RC_0603
2
1

PC5760
22UC_6.3VC_MC_X5RC_0603
2013/08/15

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
base on S540 picasso SDLE result

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size

Date:
Title

Custom
Document Number

1
1

Tuesday, November 03, 2020

PWR_VDD/SOC decoupling cap

Sheet
45
of
45
S550-15 AMD UMA
Rev
1.0
A
B
C
D