Department of Computer Science and Engineering

United College of Engineering & Research, Prayagraj

Pin - 211010 (India)

Unit wise Important Questions & Solutions

Course Name: Digital Electronics

AKTU Course Code: BOE-410

Unit-5
Section-A
Ques. Short Answer Type Questions Marks
No.
1. Discuss logic family and its use. 2
A logic family is a group of digital logic circuits that are constructed using the same
underlying semiconductor technology and share similar characteristics in terms of speed,
power consumption, voltage levels, and switching behavior.
2. Give the difference between PAL and PLA. 2
PLA and PAL are both types of Programmable Logic Devices (PLDs) used in digital circuit
design, but they differ in their internal architecture. PLA features a programmable AND
array followed by a programmable OR array, while PAL has a programmable AND array but
a fixed OR array
3. Define term propagation delay. 2
Propagation delay in a logic family refers to the time it takes for a signal to travel through a
logic gate and for the output to reflect the change in the input signal. Specifically, it's the
delay between a stable input change and when the output stabilizes to a new, valid logic
level. This delay is crucial for understanding circuit performance and timing behavior.
4. What do you mean by a memory? 2
A memory refers to a physical device that stores binary data, which can be accessed and
manipulated by a digital system. This data can be instructions for a computer program or
the data the program is actively using. Essentially, it's where a computer stores
information, either temporarily or permanently, for later use.
5. Why is ECL logic faster than TTL? 2
ECL (Emitter Coupled Logic) is faster than TTL (Transistor-Transistor Logic) primarily
because ECL operates in a non-saturated mode, preventing transistors from entering the
saturation region, which reduces switching time. TTL, on the other hand, saturates its
transistors, leading to a storage delay that slows down switching.
6. Compare static RAM and dynamic RAM. 2
Static RAM (SRAM) and Dynamic RAM (DRAM) are two primary types of computer
memory, but they differ significantly in speed, cost, and how they store data. SRAM is
faster, more expensive, and typically used for CPU caches, while DRAM is slower but
cheaper and forms the main system memory in computers.
7. Illustrate the use of logic families in digital circuits. 2
Logic families are sets of digital circuits designed with specific characteristics like voltage
levels, switching speed, and power consumption. They are crucial for implementing logic
gates and building digital systems. Examples include TTL, CMOS, and ECL, each with trade-
offs between speed, power, and other parameters.
8. Elaborate the term Fan-in in digital circuits. 2
In digital circuits, fan-in refers to the number of inputs a logic gate can accept. It essentially
defines how many signals can be fed into a single gate. For example, a logic gate with two
inputs has a fan-in of two.
9. Which logic family consumes the least power? 2
The CMOS (Complementary Metal-Oxide-Semiconductor) logic family consumes the least
power. CMOS is known for its low power consumption due to its design, which utilizes
complementary transistors that are either fully on or off, minimizing static power
dissipation.
10. Define Power Dissipation. 2
Power dissipation in logic families refers to the amount of power consumed by a logic gate
or a digital circuit during its operation. It's a crucial factor in digital design, as it affects
battery life, heat generation, and overall system performance. Power dissipation is
typically measured in milliwatts (mW).
11. Write Difference between RAM and ROM. 2
RAM and ROM are both types of computer memory, but they differ in their volatility and
purpose. RAM (Random Access Memory) is volatile, meaning it loses its data when power
is turned off, and is used for actively running programs and data. ROM (Read-Only
Memory) is non-volatile, retaining its data even without power, and stores essential
startup instructions for the computer.
12. Define PROM. 2
PROM is the programmable Read Only Memory. It consists of Fixed AND array and
Programmable OR array.
13. Define Noise Immunity. 2
Noise immunity in digital electronics refers to a circuit's ability to tolerate unwanted
electrical signals (noise) without causing errors or malfunctions. It's a crucial characteristic
for reliable digital system operation, as noise can stem from various sources like power
fluctuations, electromagnetic interference, or crosstalk. High noise immunity ensures the
circuit functions correctly even in noisy environments.
14. Draw and explain the CMOS inverter. 2

15. Draw the circuit diagram of Two Input NOR gate. 2

16. Name any four logic families. 2
TTL(Transistor-TransistorLogic)
CMOS (Complementary Metal-Oxide-Semiconductor)
ECL (Emitter-Coupled Logic)
RTL (Resistor-TransistorLogic)
17. For a memory size of 2048 X 16 bits, how many binary cells are required? 2
Total Binary Cells= Number of words × Bits per word
Total Binary Cells=2048 × 16= 32,768
 Section-B
Ques. Long Answer Type Questions Marks
No.
1. Discuss different types of RAM memory cell. 7
There are two main types of RAM memory cells: Static RAM (SRAM) and
Dynamic RAM (DRAM). SRAM uses transistors to store data, while DRAM uses
a combination of transistors and capacitors. SRAM is faster and more
expensive, while DRAM is slower and more cost-effective.
Static RAM (SRAM):
Structure:
SRAM cells are built using multiple transistors (typically four to six) to
create a bistable circuit, which can maintain its state (either 0 or 1) as
long as power is supplied.
Functionality:
Once data is written into an SRAM cell, it remains stored until
overwritten or the power is turned off. This eliminates the need
for constant refreshing.
Advantages:
Fast access times, low power consumption (compared to DRAM
for similar density), and stable data storage.
Disadvantages:
Higher cost per bit, lower density compared to DRAM, and
larger cell size.
Typical Applications:
Cache memory (L1, L2, L3) in CPUs, high-speed buffers, and
other performance-critical applications.
Dynamic RAM (DRAM):
Structure:
DRAM cells consist of a single transistor and a capacitor. The
capacitor stores a charge to represent a data bit (0 or 1).
Functionality:
Due to charge leakage from the capacitor, DRAM cells require
periodic refreshing (rewriting the data) to maintain the stored
information.
Advantages:
Lower cost per bit, higher density, and smaller cell size.
Disadvantages:
Slower access times due to the refresh requirement, higher
power consumption compared to SRAM for similar density.
Typical Applications:
Main system memory (RAM) in computers and other devices.
In essence:
SRAM is like a fast, expensive, and reliable storage that doesn't
 need constant attention.
DRAM is like a more affordable, higher-capacity storage that
requires regular maintenance (refreshing) to keep working.

2. Explain the working and structure of EEPROM cell. 7

EEPROM (Electrically Erasable Programmable Read-Only Memory) cells store
data by trapping or not trapping electrons on a floating gate within a transistor
structure. This charged/uncharged state represents a binary digit (0 or
1). EEPROMs are non-volatile, meaning they retain data even when power is off,
and can be erased and reprogrammed electrically, unlike EPROMs which require
UV light.
Structure:
Floating-gate transistor:
The core of an EEPROM cell is a MOSFET (Metal-Oxide-
Semiconductor Field-Effect Transistor) with a floating gate.
Floating gate:
This is a conductive layer, typically polysilicon, completely
surrounded by an insulating oxide layer (SiO2). It is not directly
connected to any circuit and can hold a charge.
Control gate:
a. Above the floating gate is a control gate, which is used to
control the flow of current through the transistor.
b. Tunnel oxide:
c. This thin layer of oxide between the floating gate and the
substrate allows electrons to tunnel through it under certain
voltage conditions.
Working:
Programming (Writing):
a. To store a '1', a high voltage is applied to the control gate and
the source and drain are grounded.
b. This creates a strong electric field, causing electrons to tunnel
through the tunnel oxide and accumulate on the floating gate.
c. The trapped electrons create a charge that impedes the flow of
current when a read voltage is applied to the control gate.
Erasing:
a. To erase the stored data (i.e., remove the charge from the
floating gate), a different voltage configuration is applied.
 b. The source and drain are grounded, and a high voltage is applied
to the drain, causing electrons to tunnel off the floating gate
and into the drain.
c. This leaves the floating gate uncharged, and the transistor
behaves normally when a read voltage is applied.
Reading:
a. A read voltage is applied to the control gate.
b. If the floating gate has a charge (programmed state), it impedes
the flow of current through the transistor, indicating a '1'.
c. If the floating gate is uncharged (erased state), current flows
normally, indicating a '0'.
Key differences from EPROM:
a. Erasure method: EEPROMs are erased electrically, while
EPROMs require UV light exposure.
b. Programming: EEPROMs can be programmed and erased in-
circuit, while EPROMs typically require an external
programmer.
c. Erase/Write cycles: EEPROMs have a limited number of
erase/write cycles, but modern ones can reach a million or
more.

3. Describe the difference between PAL & PLA using neat diagram and suitable 7
examples.

Programmable Array Logic Programmable Logic Array

(PAL) (PLA)

The full form of PAL is a The full form of the PLA is a

programmable array logic programmable logic array

The construction of PLA can

The construction of PAL can be done using the
be done using the programmable collection of
programmable collection of AND & fixed collection of
AND & OR gates OR gates.

The availability of PAL is The availability of PLA is

more. less.

The flexibility of PAL

programming is more. The flexibility of PLA is less.

The cost of a PAL is low. The cost of PLA is high.

The number of functions

The number of functions implemented in PLA is
implemented in PAL is large. limited.
 The speed of PAL is high. The speed of PLA is low.

Example of PAL

Implement the following Boolean expression with the help of programmable

array logic (PAL)
X =AB + AC’
Y= AB’ + BC’
The above given two Boolean functions are in the form of SOP (sum of
products). The product terms present in the Boolean expressions are X & Y, and
one product term that is AC’ is common in every equation. So, the total required
logic gates for generating the above two equations is AND gates-4 OR
programmable gates-2. The equivalent PAL logic diagram is shown below.

PAL Logic Circuit

The AND gates which are programmable have the right of entry for normal as
well as complemented variable inputs. In the above logic diagram, the available
inputs for each AND gate are A, A’, B, B’, C, C’. So, in order to generate a single
product term with every AND gate, the program is required.
All the product terms are obtainable at the inputs of an each OR gate. Here, the
programmable connections on the logic gate can be denoted with the symbol
‘X’.

Here, the OR gate inputs are fixed. Thus, the required product terms are
associated with each OR gate inputs. As a result, these gates will generate
particular Boolean equations. The ‘.’ The symbol represents permanent
connections.
Design of Programmable Logic Array (PLA)

The definition of term PLA presents the Boolean function in the form of a sum of
product (SOP). The designing of this programmable logic array can be done using
the logic gates like AND, OR, and NOT by fabricating on the chip, that makes
every input as well as its compliment obtainable toward every AND gate.
An every AND gate’s output is connected to the every OR gate. Finally, the
output of the OR gate generates the output of the chip. Thus, this is how an
appropriate association is finished to use the expressions of the sum of the
product. In the programmable logic array, the connections of logic gates like
AND & OR are programmable. PLA is expensive and difficult to compare with
PAL. The PAL uses two dissimilar developed methods can be used for a
programmable logic array for enhancing the effortlessness of programming. In
this kind of method, every connection can be done using a fuse on each
intersection point wherever the unnecessary connections can be detached by
the fuse blowing. The final technique engages the making of connection while
the process of the fabrication using the suitable cover offered for the precise
interconnection model.

Example of PLA

Implement the following Boolean expression with the help of programmable

logic array (PLA)

X = AB + AC’
Y = AB’ +BC + AC’
The above given two Boolean functions are in the form of SOP (sum of
products). The product terms present in the Boolean expressions are X & Y, and
one product term that is AC’ is common in every equation. So, the total required
logic gates for generating the above two equations is AND gates-4, OR
programmable OR gates-2. The equivalent PLA logic diagram is shown below.

PLA Logic Circuit

The AND gates which are programmable have the right of entry for normal as
well as complemented variable inputs. In the above logic diagram, the available
inputs for each AND gate are A, A’, B, B’, C, C’. So, in order to generate a single
product term with every AND gate, the program is required.
 All the product terms are obtainable at the inputs of each OR gate. Here, the
programmable connections on the logic gate can be denoted with the symbol
‘X’.

4. Design 8Kx8 RAM memory system, using 1Kx8 memory ICs 7

To design an 8K × 8 RAM memory system using 1K × 8 memory ICs, you
need to:
• Understand that "8K × 8" means:
o 8K (8192) locations
o Each location stores 8 bits (1 byte)
• The given memory ICs are 1K × 8, meaning:
o Each IC has 1K (1024) locations
o Each location stores 8 bits
✅ Step 1: Calculate Number of ICs Needed
Total memory required=8K×8Each IC provides=1K×8\text{Total memory
required} = 8K \times 8 \\ \text{Each IC provides} = 1K \times
8Total memory required=8K×8Each IC provides=1K×8
8K1K=8 ICs required\frac{8K}{1K} = \mathbf{8} \text{ ICs required}1K8K
=8 ICs required
So, we need 8 memory ICs of 1K×8 to make 8K×8 RAM.
✅ Step 2: Address Lines Calculation
Each 1K IC requires:
log 2(1024)=10 address lines\log_2(1024) = 10 \text{ address lines}log2
(1024)=10 address lines
To address 8K (8192) memory locations:
log 2(8192)=13 address lines\log_2(8192) = \mathbf{13 \text{ address
lines}}log2(8192)=13 address lines
So, we need 13 address lines for the 8K × 8 system.
✅ Step 3: Memory Organization
We’ll use:
• 8 blocks of 1K × 8 (each block covers 1K locations)
• Each block is selected using 3 high-order address lines (A12–A10) via
a 3-to-8 decoder
• The 10 lower-order address lines (A9–A0) go to all ICs as internal
address lines
✅ Decoder:
Use a 3-to-8 line decoder:
• Input: A12, A11, A10
• Outputs: 8 select lines → Each output enables one 1K×8 IC
✅ Step 4: Control Signals
• OE (Output Enable) and CS (Chip Select) of each IC controlled via
decoder outputs.
• When a specific 3-bit combination appears on A12–A10, the decoder
activates one IC.
✅ Summary
• Total memory: 8K × 8
• ICs used: 8 × (1K × 8)
• Address lines: 13 total (A0–A12)
• Decoder: 3-to-8 to select among 8 memory ICs
• Parallel configuration: All ICs connected to the same data lines, only
 one active at a time

5. Why ECL is better? Implement NAND gate with DTL and TTL. 7

Since ECL is not operated in the saturation mode, it operates in the active mode
hence the speed of ECL is better than other logic family.

Diode Transistor Logic Circuit

Diode transistor logic circuit is shown below. This is a two-input diode
transistor logic NAND gate circuit. This circuit is designed with two
diodes & a transistor where two diodes are indicated with D1, and D2 &
the resistor is indicated with R1 which forms the input side of the logic
circuit. The Q1 transistor CE configuration & R2 resistor form the output
side. The ‘C1’ capacitor in this circuit is used to give an overdrive current
throughout the switching time and this decreases the switching time to
some level.

Diode Transistor Logic Working

Whenever both the inputs of the circuits A & B are LOW, then both D1 &
D2 diodes will become forward biased, thus these diodes will conduct
within the forward direction. Thus the current supply because of the
voltage supply (+VCC = 5V) will supply to the GND throughout the R1
resistor & the two diodes. The voltage supply gets reduced within the R1
resistor & it will not be enough to turn ON the Q1 transistor, thus the Q1
transistor will be in the cut-off mode. So, the o/p at the ‘Y’ terminal will
be Logic 1 or HIGH value.

When any one of the inputs is LOW, then the corresponding diode will
be forward-biased so, a similar operation will happen. As any one of
these diodes is forward biased, then current will be supplied to the
ground throughout the forward-biased diode, thus the ‘Q1’ transistor
will be within cut-off mode, so the output at the ‘Y’ terminal will be high
or logic 1.

Whenever both the A & B inputs are HIGH then both the diodes will be
reverse biased, thus both the diodes will not conduct. So in this
condition, the voltage from the +VCC supply will be sufficient to drive
the Q1 transistor into conduction mode.

Therefore the transistor conducts throughout emitter & collector

terminals. The whole voltage gets reduced within the ‘R2’ resistor & the
output at the ‘Y’ terminal will have LOW o/p and is considered as low or
logic 0.

TTL NAND Gate

Case:- 1 If all inputs are at logic zero or any input is at logic zero

Transistor Q1 will become on and the maximum current will

flow through the emitter of the transistor Q1 which will reduce the
current at Base of Q2 i.e. a minute current will flow through the Q2
forced the transistor Q2 to remain off. Since Transistor Q2 and Q3 is
connected as emitter follower hence transistor Q3 will also be off (as
minute current will also flow through the base of Q3 which is not able to
turn on the Q3). Due to aforesaid condition a sufficient voltage is
 available at B-E junction of Q4 to turn on the Q4 and Diode D1 and the
output will be connected to +Vcc.

Case:- 2 If all inputs are at logic 1

It will make the transistor to operate in the reverse active mode

and the maximum current will flow through the collector of Q1 which in
turn base current of Q2 and Q3 will also increase which will make the Q2
and Q3 to turn on and the transistor Q4 and diode D1 to turn off hence
the output will be connected to Ground .

6. Define noise margin, Fan-in, Fan-out as characteristics of logic families. 7

Implement NAND gate with CMOS.
Noise margin, Fan-in, and Fan-out are key characteristics of logic families that
define their performance and limitations. Noise margin refers to the immunity
of a gate to voltage fluctuations or noise. Fan-in is the number of inputs a logic
gate can accept. Fan-out is the number of logic gate inputs that a logic gate
output can drive reliably.
Noise Margin:
Definition:
Noise margin is the ability of a logic gate to tolerate voltage fluctuations
(noise) on its input without causing a change in its output state. In
simpler terms, it's the "safety zone" for the voltage levels of logic high
and logic low signals.
Importance:
A higher noise margin means the circuit is more robust against noise and
less prone to errors.
Types:
• High-level noise margin (NMH): The difference between the
minimum output high voltage (VOH) and the minimum input
high voltage (VIH).
• Low-level noise margin (NML): The difference between the
maximum output low voltage (VOL) and the maximum input low
voltage (VIL).
Calculation:
NMH = VOH - VIH and NML = VIL - VOL.
Fan-in:
Definition: Fan-in is the maximum number of inputs that a logic gate can
accept. It essentially dictates how many signals can be fed into the logic
gate's inputs.
Importance: Fan-in determines the complexity of logic functions that
can be implemented using a single gate.
Example: A 3-input AND gate has a fan-in of 3.
Fan-out:
Definition:
Fan-out is the maximum number of logic gate inputs that a single logic
gate output can drive without causing a degradation in its performance
(e.g., voltage levels, speed).
 Importance:
Fan-out limits the number of gates that can be connected to a single
output, impacting the complexity of the overall circuit.
Example:
If a gate has a fan-out of 10, it means it can reliably drive up to 10 other
gate inputs.
TWO Input CMOS NAND Gate

7. Design a BCD to Excess-3 code converter and implement it using a suitable 7

PLA.
8. Draw a neat diagram of TTL NAND gate and explain its operation. 7

Case:- 1 If all inputs are at logic zero or any input is at logic zero
 Transistor Q1 will become on and the maximum current will
flow through the emitter of the transistor Q1 which will reduce the
current at Base of Q2 i.e. a minute current will flow through the Q2
forced the transistor Q2 to remain off. Since Transistor Q2 and Q3 is
connected as emitter follower hence transistor Q3 will also be off (as
minute current will also flow through the base of Q3 which is not able to
turn on the Q3). Due to aforesaid condition a sufficient voltage is
available at B-E junction of Q4 to turn on the Q4 and Diode D1 and the
output will be connected to +Vcc.
Case:- 2 If all inputs are at logic 1
It will make the transistor to operate in the reverse active mode
and the maximum current will flow through the collector of Q1 which in
turn base current of Q2 and Q3 will also increase which will make the Q2
and Q3 to turn on and the transistor Q4 and diode D1 to turn off hence
the output will be connected to Ground .

9. Define the TTL (Transistor-Transistor-Logic) logic Family used for digital 7

circuits.
Transistor-Transistor Logic (TTL) is a digital logic family that uses bipolar
junction transistors (BJTs) to implement logic gates and other digital
circuits. It's characterized by its speed and relatively high power
consumption compared to other logic families like CMOS. TTL is
commonly used in various digital applications, including computers,
consumer electronics, and industrial control systems.
Characteristics of TTL:
Bipolar Transistors:
TTL utilizes NPN bipolar junction transistors (BJTs) as the
fundamental building blocks for logic gates and other circuit
components.
Logic Gates:
TTL logic gates, like NAND, NOR, AND, OR, and XOR, are
implemented using combinations of BJTs, diodes, and resistors.
Multiple Emitter Transistors:
Some TTL gates, like the NAND gate, utilize transistors with
multiple emitters to perform the logic function.
Output Configurations:
TTL circuits often feature different output configurations, such
as totem-pole, open-collector, and tri-state, to provide flexibility
in circuit design and interfacing.
Subfamilies:
TTL has various subfamilies, including standard TTL, low-power
TTL, Schottky TTL, and advanced Schottky TTL, each offering
different speed and power consumption characteristics.
Logic Levels:
TTL typically operates with voltage levels of 0V for a low logic
level and +5V for a high logic level.
Advantages of TTL:
 Speed:
TTL offers relatively fast switching speeds, making it suitable for
many digital applications.
Robustness:
TTL circuits are generally more robust and less susceptible to
noise and interference compared to some other logic families.
Availability:
TTL integrated circuits (ICs) are widely available and have been
used extensively in various electronic systems.
Disadvantages of TTL:
Power Consumption:
TTL generally consumes more power than CMOS logic families,
especially at higher frequencies.
Voltage Levels:
TTL operates with a relatively high voltage level (5V), which may
not be compatible with other logic families that use lower
voltage levels.

10. Define the SRAM cell with working and circuit diagram along with applications. 7
6-T Static RAM cell Read Operation

• Assume that node 1 has logic 0v

• So M1 and M6 are ON while M5 and M2 are OFF. Because of this,
Node1 = 0V and V2 = VDD.
• Data lines are pre-changed from 0 to VDD and
the word line is activated.
• So M3 and M4 are switched ON.
• Since the drain and source for M4 are at the same potential, no current f
lows in this area.
• However, the drain and source at M3 in LHS have a high differential pot
 ential, therefore M3 experiences non-zero current flow.
• Path: M3, M1, and GND
• The
voltage at BL starts to decline, which causes the capacitor to discharge a
nd raise V1.
• Since V1 is increasing from 0V and it may turn on M2 if M1 size is small,
So for reading operation, M1 should be greater than M3
6-T SRAM cell Write Operation

Consider that Node 1 stores Assume 1.

• So M2 and M5 are ON while M1 and M6 are OFF.
• Prior to the ON state of M2 and M4, V1 = VDD and V2 = 0V.
• As Wordline goes high, M3 and M4 are turned ON.
• Since Node2 < VT1, Node2 cannot be used to turn ON M1. We need to
turn ON M1 so that path is created from Node1 to GND and the voltage
at Node1 will decrease to zero since the path is pulled down to GND.
• Therefore we turn OFF M2. Node1 < VT2 to turn OFF M2. When Node1
= Vin; M3 goes in the linear region and M5 in the saturation region.
• For a successful Write operation, we should have M4> M6.

11. Elaborate the PLA (Programmable Logic Array) along with working and
applications.
The combinational circuit do not use all the minterms every time.
Occasionally, they have don’t care conditions. Don’t care condition
when implemented with a ROM becomes an address input that will
never occur. The result is that not all the bit patterns available in the
ROM are used, which may be considered a waste of available
equipment. For cases where the number of don’t care conditions is
excessive, it is more economical to use a second type of LSI component
called a Programmable Logic Array (PLA).
 A Programmable Logic Array is similar to a ROM in concept; however it
does not provide full decoding of the variables and does not generates
all the minterms as in the ROM. The PLA replaces decoder by group of
AND gates, each of which can be programmed to generate a product
term of the input variables. In PLA, both AND and OR gates have fuses at
the inputs, therefore in Programmable Logic Array both AND and OR
gates are programmable. Fig. 3.88 shows the Block Diagram of PLA. It
consists of n inputs, output buffer with m outputs, m product terms, m
sum terms, input and output buffers. The product terms constitute a
group of m AND gates and the sum terms constitute a group of m OR
gates, called OR matrix. Fuses are inserted between all n inputs and
their complement values to each of the AND gates. Fuses are also
provided between the outputs of the AND gates and the inputs of the
OR gates. The third set of fuses in the output inverters allows the output
function to be generated either in the AND-OR form or in the AND-OR-
INVERT form. When inverter is bypassed by link we get AND-OR
implementation.

12. Describe the operation of ECL in detail. 7

Emitter-coupled logic is the fastest of all digital logic families. It was
invented by Hannon S. Yourke in the year 1956 at IBM. It is also called as
current mode logic. The design of ECL circuit consists of transistors and
resistors.
By preventing the transistor from entering into saturation, the high-speed
operation is achieved in ECL logic family. Very small voltage swing is
necessary to switch between the two different voltage levels. This cannot be
achieved in transistor-transistor logic, as the transistors enter into
saturation mode, while in operation.
Emitter-coupled logic family offers an incredible propagation delay of 1ns.
The delay is more reduced in the latest ECL families.
In this section, you will learn about the operation of basic emitter-coupled
logic implemented for inverter circuits and OR/NOR gate.
Two input ECL OR/NOR gate
The following circuit is the Emitter-coupled logic circuit of the 2-input
OR/NOR gate. It is the slight modification of the inverter circuit given above.
In this, an additional transistor is used at the input side.
The operation is simple as explained above. If the input at both the
transistors Q1 and Q2 are LOW, it will make VOUT1 to HIGH value. It
corresponds to the NOR gate output. At the same time, transistor Q3 is
turned ON, which will make the VOUT2 to be LOW. It corresponds to
the OR gate output.
Similarly, if both the input of transistors Q1 and Q2 are HIGH, it will turn on
both the transistors. It will drive the output at terminal VOUT1 to be LOW. The
 transistor Q3 is turned OFF during this operation. It will drive the output at
terminal VOUT2 to be HIGH.

Advantages
• High-speed operation is possible and so the fastest logic family.
• Since transistors are not allowed to enter into saturation, which reduces
the storage delay.
• Fan-out capability is high.

13. Discuss the type of primary memory in detail. Also implement the boolean 7
function F(a,b,c,d) = ∑m(4,7,10,11,14,15) using PROM.

Primary Memory, also known as main memory, is the memory that the CPU
can access directly. It is volatile (except for ROM) and is essential for storing
instructions and data temporarily during program execution.
SRAM (Static RAM) uses flip-flops to store each bit. Faster, more expensive,
doesn't need refreshing.
DRAM (Dynamic RAM) stores data in capacitors. Needs constant refreshing.
Slower and cheaper than SRAM.
 ROM (Read-Only Memory):Non-volatile — retains data even when power
is off,

14. Differentiate the three PLDs. Implement the circuit with PLA for the following 7
Boolean functions F (a,b,c)=∑m(0,7), G (a,b,c,d)= ∑m (4,5,12,13,14,15), and
H(a,,b,c) =∑m(2,4,5).
15. Give the classification of logic families. Write short note on fan in, Fan out, noise 7
margin. Also draw the NAND gates using CMOS.
Fan Out: Refers to the number of inputs that is driven by the output of another logic
gates. For example, the following circuit has an EX-OR gate, which drives 4 NOT gates. So
fan- out of EX-OR gate is 4.

Fan In: Fan in is the number of inputs available in a gate. For the example given in the
figure below, the EX-OR gate has three inputs. So fan-in for the given EX-OR gate is 3.

Noise Margin: Noise is an unwanted signal that is superimposed on the normal

operating signal. Noise may be due to various factors like operating environment,
radiations, stray electrical and magnetic fields.