SRG ENGINEERING COLLEGE

ANNIYAPURAM(PO), NAMAKKAL(DT)-637017

DEPARTMENT OF BIOMEDICAL ENGINEERING

Second Year (IV – SEMESTER)

Lab Manual

BM3412- ANALOG AND DIGITAL

INTEGRATED CIRCUITS LABORATORY

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 BM3412 ANALOG AND DIGITAL INTEGRATED
CIRCUITS LABORATORY

LIST OF EXPERIMENTS:

DESIGN AND TESTING OF THE FOLLOWING CIRCUITS

1. Inverting, Non-inverting Amplifier, and comparator

2. Integrator and Differentiator.
3. Design and analysis of active filters using Op-amp
4. Schmitt trigger using Operational amplifier
5. Instrumentation amplifier using Operational amplifier
6. RC and LC oscillators
7. Multivibrators using IC555 Timer.
8. Study of logic gates, Half adder and Full adder
9. Encoder and BCD to 7 segment decoder
10. Multiplexer and demultiplexer using digital ICs
11. Universal shift register using flip flops
12. Design of mod-N counter
13. Simulation and analysis of circuits using software.

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Ex. No:1(a) INVERTING, NON-INVERTING Date:
AMPLIFIER
AIM:
To design, construct and test inverting, non-inverting and differential amplifier using IC 741.
APPARATUS REQUIRED:
S.No. Name of the Apparatus Range/Value Qty
1. Bread Board - 1
2. RPS (0-30) V 2
3. Dual Power Supply ±15 V 1
4. Resistor 1k Ω,10k Ω 2,2
5. IC 741 Op-Amp - 1
6. Connecting Wires - Few
7. Function Generator (0-3) MHz 1
8. CRO (0-30) MHz 1
9. Voltmeter or Multi-meter (0-30) V 1
DESIGN:

INVERTING AMPLIFIER: To design an amplifier for the gain of -10. Gain =

Rf/R1.As the Gain is given negative, the circuit is inverting the amplifier. Gain
Av = Rf/R1 = 10 => Rf= 10 R1. Let R1= 1k, Rf = 10 * R1 = 10 * 1k = 10k.
NON-INVERTING AMPLIFIER: To design an amplifier for the gain of 11. Gain
= 1+ Rf/R1.As the Gain is given positive, the circuit is noa n-inverting amplifier.
Gain Av = 1+Rf/R1 = 11 => Rf = 10 R1. Let R1= 1k, Rf = 10 * R1 = 10 * 1k = 10k.

THEORY:
INVERTING AMPLIFIER: A typical inverting amplifier with input resistor R 1and a feedback
resistor Rf is shown in the figure. Since the op-amp is assumed to be an ideal one the input bias current
is zero and hence the non-inverting input terminal is at ground potential. The voltage at node „A‟ is
Zero, as the non inverting input terminal is grounded. The nodal equation by KCL at node „A‟ is
given by Vi/R1 + Vo/Rf =0 or V0 = -Rf (Vi/R1).
NON-INVERTING AMPLIFIER: A typical non-inverting amplifier with input resistor R 1 and a
feedback resistor Rf is shown in the figure. The input voltage is given to the positive terminal. The
output voltage is given by V0= (1+Rf /R1) Vi

CIRCUIT DIAGRAM:
INVERTING AMPLIFIER TABULATION:

Wave- Time Period Voltage Practical

form in ms in Volts Gain
Input
(Vin)
Output
(Vo)

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 PIN DIAGRAM

NON INVERTING AMPLIFIER

Wave- Time Voltage Practical
form in ms in Volts Gain
Input
(Vin)
Output
(Vo)

PROCEDURE:
(i) Connect the inverting amplifier circuit as per the circuit diagram.
(ii) For various input voltage measure and record the output voltage.
(iii) Repeat the same for non- inverting and differential amplifier.

MODEL GRAPH:

INVERTING AMPLIFIER NON-INVERTING AMPLIFIER

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SPECIFICATION FOR IC 741

+Vcc = +15V, - Vcc = -15V

Ambient Temparature : 250 C
Input offset voltage : 6 mV(Max)
Input offset current :
200nA(Max) Input bias current
: 500nA(Max)
Input resistance : 2M
Output resistance : 75
Total Power dissipation :
85mW.

RESULT:
The design and testing of the inverting, non-inverting amplifier is done and the input and output
waveforms were drawn.
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Ex. No:1(b) COMPARATOR Date:

AIM:
To obtain the output of voltage comparator
APPARATUS REQUIRED:
S.No. Name of the Apparatus Range/Value Qty
1. Bread Board - 1
2. RPS (0-30) V 2
3. Dual Power Supply ±15 V 1
4. Resistor 1k Ω 2
5. IC 741 Op-Amp - 1
6. Connecting Wires - Few
7. Function Generator (0-3) MHz 1
8. CRO (0-30) MHz 1
9. Voltmeter or Multi-meter (0-30) V 1

THEORY:
Voltage Comparator: A comparator is a circuit which compares a signal voltage applied at one input of an op-
amp with output  Vsat = (Vcc). If the signal is applied to the inverting terminal of the op-amp it is called
inverting comparator and if the signal is applied to non-inverting terminal of the op-amp it is called non-
inverting comparator. In an inverting comparator if input signal is less than reference voltage, output will be
+Vsat. When input signal voltage is greater than reference voltage output will be –Vsat. The vice-versa takes
place in non-inverting comparator.
PROCEDURE:
1) Voltage comparator:
1. Connect the circuit as shown in the figure.
2. Connect an alternating waveform to the non-inverting input of the opamp.
3. Connect a reference voltage source to inverting input of the op-amp.
4. Plot the input and output waveforms

PIN DIAGRAM

CIRCUIT DIAGRAM:

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Voltage Comparator:

TABULAR COLUMN:

SI. NO INPUT OUTPUT

VOLTAGE (V) TIME (ms) VOLTAGE (V) TIME (ms)

RESULT:
Thus the output of voltage comparator was obtained and the graphs have been drawn.

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Ex. No:2 INTEGRATOR AND DIFFERENTIATOR Date:
AIM:
To design and test the following Op-Amp Circuits: a. Integrator b. Differentiator
APPARATUS REQUIRED:
S.No. Name of the Apparatus Range/Value Qty
1. Bread Board - 1
2. IC Power Supply ±15 V 1
3. Resistor 10 k Ω, 100 k Ω,1.5 k Ω,15k Ω 2, 1,1,1
4. IC 741 Op-Amp - 1
5. CRO 20 MHz. 1
6. Signal Generator 0-1 MHz. 1
7. Capacitor 0.1µF,0.01 µF 1(each)
8. Connecting Wires - Few
THEORY:
a. INTEGRATOR:
The circuit performs the mathematical operation of integration, that is, the output waveform is the
integral of the input waveform. The output voltage V o(t) = - (1/RfCf) Vi(t) dt , Where Vi is the input
voltage , Rf is the feedback resistance & Cf is the feedback capacitence.
b. DIFFERENTIATOR:
The circuit performs the mathematical operation of differentiation, that is, the output waveform is the
derivative of the input waveform. The output voltage Vo(t) = - RC (dvi / dt) Where Vi is the input
voltage
, Rf is the feedback resistance & Cf is the feedback capacitence

DESIGN:
a. Integrator: Design of Integrator with lower frequency limit of fmin = 160Hz.
1
f 
min
2Rf C f
Rf = 10R1
Let R1=1.5KΩ, then Rf =
The range of Cf value from 0.001µF to 10µF is preferable. The capacitor has to very low leakage
C 
f 
1 2Rf f min

b. Differentiator: Design of opamp differentiator that will differentiate an input signal

with fa =100Hz.The time period T of the input signal must be larger than or equal to R fC1.
1
Highest frequency of the input signal = fa 
2Rf C1
Select C1 ( 1F). Let C1  0.1F
1
f a  100 
2Rf C1
1
R 
 1
f
2 100  0.1106  
f ;R 
b 1 10 f a 1KHz 
2
RC 1 2 1000  0.1106
1 1

R1 C1 = Rf Cf; C 1.59 103  0.1106

 
f
15.9 103

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PROCEDURE:
1. Connections are given as per the circuit diagram for integrator.
2. The square wave of 2Vp-p is given as input to the inverting terminal of the IC.

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3. The output waveform is observed in the CRO.
4. Plot the input and output waveforms.
5. Repeat the same for differentiator

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 Waveform

CIRCUIT DIAGRAM TABULATION:

a. INTEGRATOR :
Amplitude Time period
(Volts) (ms)

INPUT

OUTPUT

b. DIFFERENTIATOR:

Waveform Amplitude Time period

(volts) (ms)

INPUT

OUTPUT

MODEL GRAPH:
a) Integrator: b) Differentiator:

RESULT:
Thus the operation of Integrator and Differentiator was studied and the output was verified with the theoretical
calculation.

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Ex. No:3 INSTRUMENTATION AMPLIFIER Date:
AIM:
To design and test the operation of the Instrumentation Amplifier.
APPARATUS REQUIRED:
S.No. Name of the Apparatus Range/Value Qty
1. Bread Board - 1
2. Decade Resistance Box 1 Ω to 1 M Ω 1
3. Dual Power Supply ±15 V 1
4. Resistor 1 k Ω,2.2 k Ω 7,1
5. IC 741 Op-Amp - 1
6. Multimeter 3½ Digits 1
7 RPS (0-30) V 1
8. Connecting Wires - Few
THEORY:
An instrumentation amplifier is an amplifier with high input impedance, very low offset
and drifts voltage. This configuration is better than inverting or non-inverting amplifier because it has
minimum non-linearity, stable voltage g,ain and high common mode rejection ratio (CMRR > 100
dB.). This type of amplifier is used in thermocouples, strain gauges and biological probes.
Output voltage V0 = (V2 – V1) [1 + 2 R1 / R2]
CIRCUIT DIAGRAM:

PROCEDURE:
(i) Connections are given as per the circuit Diagram.
(ii) For various input voltage V1 & V2, measure and record the output voltage.

TABULAR COLUMN:
Input Vo in volts
Voltages
V1 V2
volts volts Theoretical Practical

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RESULT:
Thus the Instrumentation amplifier was constructed & Verified

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Ex. No:4(a) SECOND ORDER ACTIVE FILTERS Date:
AIM:
To design, construct and plot the frequency response of second order low pass and high pass filter
having the fc of 1 kHz.
APPARATUS REQUIRED:
S.No. Name of the Apparatus Range/Value Qty
1. Bread Board - 1
2. IC Power Supply ±15 V 1
10 k Ω,5.86 k Ω 1
3. Resistor
1.6 k Ω 2
4. IC 741 Op-Amp - 1
5. CRO 20 MHz. 1
6. Function Generator 0-3MHz. 1
7. Capacitor 0.1µF 2
8. Connecting Wires - Few
THEORY:
An improved filter response can be obtained by using a second order active filter. A second order
filter consist of two RC pairs has a roll-off rate of –40db/decade. The transfer function of a Low pass
filter A0 h2
is H (s)  . For n=2, the damping factor α = 1.414, the pass band gain
S 2   
2
h h
A0 = 3 – α = 1.586. Cutoff frequency of the filter = 1/ 2π RC= h. HPF is the complement of the Low
pass filter and can be obtained simply by interchanging R and C in the low pass configuration
DESIGN:
fc = 1KHz, Assume C = 0.1µF, R= 1/2πfcC=
The gain for the second order filter is known as 1.5816.
Let Ri = 10KΩ, Gain =Ao = 1.5816 => 1+ Rf / Ri = 1.586 => Rf = 0.586 Ri =
CIRCUIT DIAGRAM:
Low Pass Filter

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PROCEDURE:
1. Connect the Low pass filter circuit as shown in the circuit diagram.
2. Give an input signal Vi of 2V(p-p) and measure the output voltage for different frequency from the
CRO.
3. Plot the frequency response 20 log Vo/Vi versus input frequency and find 3db frequency.
4. Determine the cut-off frequency from the plot.
5. Repeat the above for HPF.
TABULATION:
Low Pass Filter INPUT VOLTAGE: Vi = volts
Frequency Hz Output voltage Vo volts Gain in db 20 logVo/Vi

High Pass Filter:

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High Pass Filter: INPUT VOLTAGE: Vi = volts
Frequency Hz Output voltage Vo volts Gain in db 20 logVo/Vi

MODEL GRAPH:
Low Pass Filter: High Pass Filter:

RESULT:
Thus the Second order low pass filter and High pass filter was designed and frequency response plot was
drawn.

LPF: i. Theoretical = ii. Practical =

HPF: i. Theoretical = ii. Practical =

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Ex. No:4 (b) BAND PASS FILTER Date:
AIM:
To design, construct, test and to plot the frequency response of wide band pass filter.

APPARATUS REQUIRED:
S.No. Name of the Apparatus Range/Value Qty
1. Bread Board - 1
2. IC Power Supply ±15 V 1

3. Resistor 10 k Ω, 39.8 k Ω, 7.9 k Ω 4, 1

4. IC 741 Op-Amp - 1
5. CRO 20 MHz. 1
6. Signal Generator 0-3 MHz. 1
7. Capacitor 0.01µF 2
8. Connecting Wires - Few
THEORY:
A wide band pass filter can be formed by cascading a HPF and LPF section. If the HPF and
LPF are of the first order, then the band pass filter (BPF) will have a roll off rate of -20 dB/decade. A
wide band pass filter formed by cascading I order HPF and I order LPF is shown in the circuit
diagram.
DESIGN:
fh = 2KHz; fl = 400Hz; pass band gain A0= 4.
LPF and HPF sections may be designed to have a gain of 2.
As the opamp is used in non-inverting configuration Ao = 1+ (Rf/Ri) = 2=> Rf/Ri = 1=> Rf =
Ri. Let Ri =10 kΩ, Rf = .
fh = 1/(2πR2C2) = 2KHz. Let C2= 0.01µF, R2 = 1/(2πX2X103X0.01X10-6) =
fl = 1/(2πR1C1) = 400Hz. Let C1= 0.01µF, R1 = 1/(2πX400X0.01X10-6) =
CIRCUIT DIAGRAM:

PROCEDURE:
1. Connect the Band pass filter circuit as shown in the circuit diagram.
2. Give an input signal Vi of 1V (p-p) and measure the output voltage for different frequency.
3. Plot the frequency response 20 log Vo/Vi versus input frequency and find 3db frequency.
4. Determine the cut-off frequency fh and fl .
MODEL GRAPH:

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 TABULATION: INPUT VOLTAGE: Vi = volts
Frequency ( Hz ) Output voltage Vo (volts) Gain in db 20 logVo/Vi

RESULT:
Thus the Second order Band pass filter was designed and frequency response plot was drawn

Lower cutoff frequency: i. Theoretical = ii. Practical =

Upper cutoff frequency: i. Theoretical = ii. Practical=

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19
Ex. No:5 SCHMITT TRIGGER (REGENERATIVE Date:
COMPARATOR)
AIM:
To design a Schmitt trigger circuit for generating a square wave output.

APPARATUS REQUIRED:
S.No. Name of the Apparatus Range/Value Qty
1. Bread Board - 1
2. IC Power Supply ±15 V 1
3. Resistor 1 k Ω, 27 k Ω 2, 1
4. IC 741 Op-Amp - 1
5. CRO 20 MHz. 1
6. Function Generator 0-3 MHz. 1
7. Connecting Wires - Few

THEORY:
Schmitt trigger circuit is an inverting comparator with positive feed back. The input voltage
is applied to the (-) terminal and feed back voltage to the (+) terminal. The input voltage Vi triggers
the output every time it exceeds certain voltage levels called upper threshold and lower threshold
voltage. This circuit converts an irregular shaped wave form to a square wave or pulse. The upper and
lower threshold is VUT = Vsat [R2/(R1+R2)], VLT = - Vsat [R2/(R1+R2)] respectively.

DESIGN:
VUT = + 0.5V; VLT = - 0.5V
For 741, with supply voltages ±15V, the saturation voltage ±V sat = ±15V
0.5 = 15 [R2/ (R1+R2)]. R1=27 R2. Let R2 = 1 kΩ therefore R1 =

CIRCUIT DIAGRAM: TABULATION:

Waveform Amplitude Time
(Volts) period
(ms)
INPUT

OUTPUT

PROCEDURE:
 Connect the circuit as shown in circuit diagram.
 Adjust the signal generator so that Vi =2V p-p sine wave at
1kHz.Observe and plot the input and output wave forms

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 MODEL GRAPH:

RESULT:
A Schmitt trigger designed and constructed and the square wave output is obtained.
Upper threshold voltage =
Lower threshold voltage

= Square output:
Amplitude =
Time period =

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Ex. No:6(a) RC PHASE SHIFT OSCILLATOR Date:
AIM:
To design, construct and test a RC phase shift oscillator for a frequency of 100Hz.

APPARATUS REQUIRED:
S.No. Name of the Apparatus Range/Value Qty
1. Bread Board - 1
2. IC Power Supply ±15 V 1
3. Resistor 1885 k Ω (1MΩ), 65 k Ω, 6.5 k Ω 1,1,3
4. IC 741 Op-Amp - 1
5. CRO 20 MHz. 1
6. Capacitor 0.1µF, 0.01µF 3, 1
7. Connecting Wires - Few

THEORY:
Oscillator is a feed back circuit where a fraction of output voltage of an amplifier is fed back
to the input in the same phase. RC phase shift oscillators are sine wave oscillators which are used in
the audio frequency range. The amplification is done by the op-amp and as it is used in the inverting
mode is gives a phase shift of 180 .The feedback RC network produces an additional phase shift of
180.Each RC network gives 60 phase shift.
The frequency of oscillation is given by = 1/6(2RC)

DESIGN:
fo = 100Hz; Assume C = 0.1 µF => R = 1/6(2foC) = 1/6(2X100X0.1X10-6) =
To prevent overloading of the amplifier by RC network, R1 ≤ 10R
Let R1 = 10R =
Rf = 29 R1 =

CIRCUIT DIAGRAM:

PROCEDURE:
1. The connection is made as per the circuit diagram.
2. Observe the output waveform V0 and calculate the frequency of oscillation.
3. Plot the waveform.

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 TABULATION:
OUTPUT VOLTAGE (V) TIME PERIOD(ms) FREQUENCY OF
OSCILLATION (KHZ)

MODEL GRAPH:

T= One cycle time, F=Frequency of wave in Hz=1/T

RESULT:
Thus a RC phase shift oscillator is designed to oscillate at 500Hz and the frequency of the
output waveform is =

i. Theoretical = ii. Practical =

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Ex. No:6(b) WEIN BRIDGE OSCILLATOR Date:
AIM:
To design the wein‟s bridge oscillator using OP-AMP IC for f0 = 1000Hz
APPARATUS REQUIRED:
S.No. Name of the Apparatus Range/Value Qty
1. Bread Board - 1
2. IC Power Supply ±15 V 1
3. Resistor 100 k Ω POT, 3 k Ω, 30 k Ω 1,2,1
4. IC 741 Op-Amp - 1
5. CRO 20 MHz. 1
6. Capacitor - DCB 0.05 µF 2
THEORY:
The Wein bridge oscillator is the most commonly used audio frequency oscillator because of its simplicity
and stability. The bridge has a series RC network in one arm and a parallel RC network in the
adjoining arm. In the remaining two arms of the bridge, resistors R1 and Rf are connected. The phase
angle criterion for oscillation is that the total phase shift around the circuit must be 0. This condition
occurs only when the bridge is balanced. The frequency of oscillation f0 is exactly the resonant
frequency of the balanced Wein bridge and is given by, Frequency = f0 = 1/ (2πRC).
DESIGN:
f0=1KHz; f0 = 1/(2πRC)=> R = 1/(2πf0C), Choose C=0.05F R=
1/(2πX1X103X0.05X10-6) => R =
Take R1=10R= Rf
= 2R1 =
CIRCUIT DIAGRAM:

PROCEDURE:
1. Construct the circuit with the values obtained in the design.
2. Observe the output waveform on an Oscilloscope. Adjust Rf to obtain a sine wave output.
3. Measure the frequency of oscillator and voltage amplitude. Plot the output.

TABULATION:
OUTPUT VOLTAGE (V) TIME PERIOD (ms) Frequency of Oscillation (KHz)

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 MODEL GRAPH:

RESULT:
Thus the Wien Bridge oscillator circuit is designed output waveform is obtained.

Theoretical frequency :

Practical frequency

:
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Ex. No:7(a) DESIGN OF ASTABLE MULTIVIBRATOR Date:
USING IC 555 TIMER
AIM:
To design and test an astable multivibrator for generating symmetrical and unsymmetrical
square wave form for the given frequency and duty cycle.
APPARATUS REQUIRED:
S. No. Name of the Apparatus Range/Value Qty
1. Bread Board - 1
2. Resistor 3.6 k Ω, 7.2 k Ω 1, 2
3. IC 555 - 1
4. CRO 20 MHz. 1
5. Capacitor 0.1µF, 0.01µF 1, 1
6. RPS (0-30) V/ 5V 1
7. Diode 1
8. Connecting Wires - Few
THEORY:
The 555 timer is connected as an astable multivibrator as shown in figure. In this mode of
operation the timing capacitor charges up towards Vcc (assuming Vo is high initially) through (Ra +
Rb) until the voltage across the capacitor reaches the threshold level (2/3) V cc. At this point the
internal upper comparator switches state causing the internal flip-flop output to go high. This turns on
the discharge transistor and the timing capacitor C then discharges through Rb and the discharging
transistor. The discharging continues until the capacitor voltage drops to (1/3) Vcc at which point the
internal lower comparator switches states causing the internal flip-flop output to go low, turning off
the discharge transistor. At this point the capacitor starts to charge again, thus completing the cycle.
DESIGN:
i. For Unsymmetrical waveform:
f =1/T=1.44/(Ra+2Rb)C;
DutyCycle = D = tlow/ ( tlow + t high ) => D= R b/ (Ra +2Rb) ;
Where thigh = 0.693(Ra + R b)C; tlow = 0.69;
Specifications: frequency = 1kHz; Duty cycle = 25%
Design: tlow = 0.25ms = 0.693R b C;
Let C= 0.1µF => R b = 0.25/(0.693X0.1X10-6) =
thigh = 0.693(Ra + R b)C = 0.75 ms => Ra =
ii. For Symmetrical Wave form :
thigh = 0.693 Ra C; tlow = 0.693 R bC
f = 1/T = 1.44 /(Ra + Rb)C => D= Rb /(Ra + Rb);
Specifications: frequency = 1 kHz; Duty cycle = 50% .
Design: tlow = 0.5 ms = 0.693 R bC;
Let C= 0.1 µF; R b =
thigh = 0.693 Ra C = 0.5 ms ; Ra =

26
 CIRCUIT DIAGRAM: Unsymmetrical: Symmetrical:

PIN DIAGRAM FOR IC555

1 8

2 IC555 7

3 6

4 5

1 = Ground, 2 = Trigger, 3 = output, 4 = Reset, 5 = Control voltage,

6 = Threshold, 7 = Discharge, 8 = +Vcc

27
PROCEDURE:
1. Connect the circuit as given using component values as obtained in designed part (i)
2. Observe and sketch the capacitor voltage waveform and output waveform.
3. Measure the frequency and duty cycle of the output waveform.
4. Connect the circuit using component values as obtained from designed part (ii).
5. Repeat step 2 and 3

TABULATION:
Symmetrical: Duty Cycle = 50 %
Output Capacitor
tlow (ms) t high (ms) Frequency (Hz)
Voltage (V) Voltage (V)
Theoretical Practical Theoretical Practical Theoretical Practical

Unsymmetrical: Duty Cycle = 25%

tlow (ms) Output Capacitor
t high (ms) Frequency (Hz)
Voltage (V) Voltage (V)
Theoretical Practical Theoretical Practical Theoretical Practical

MODEL GRAPH:

RESULT:
Thus IC555 timer was operated in astable mode to generate square wave.
Theoretical Duty cycle : 25% 50%
Practical Duty cycle :

28
Ex. No:7(b) MONOSTABLE MULTIVIBRATOR USING Date:
IC 555 TIMER
AIM:
To design, construct and test a monostable multivibrator using IC - 555 timer.
APPARATUS REQUIRED:
S. No. Name of the Apparatus Range/Value Qty
1. Bread Board - 1
2. Resistor 1.8 k Ω 1
3. IC 555 - 1
4. CRO 20 MHz. 1
5. Function Generator 0-3 MHz. 1
6. Capacitor 0.1µF, 0.01µF 1, 1
7. RPS (0-30) V/ 5V 1
8. Connecting Wires - Few
THEORY:
Mono-stable multivibrator has only one stable state and one quasi-stable state. Transition
isobtained from the stable to quasi-stable by triggering. The transition time due to external triggering is
very short, whereas the time for the circuit to remain quasi-stable state is very large. The circuit returns to
stable state from its quasi-stable state by itself, without requiring any external triggering signal. Because,
after triggering, the circuit returns from quasi-stable state by itself after a certain time delay, therefore the
circuit is also called a one shot multivibrator or univibrator.
The mono-stable multivibrator is a regenerative device, which is used to generate rectangular
output, pulse of predetermined width. The device can make a fast transition in time T after the application
of input trigger and as such can be used as a delay circuit. The circuit is also referred to as gating circuit,
because it generates rectangular wave form, which can be used to gate other circuits. The Pulse width is T
= 1.1 RC, where R is the resistor and C is the capacitor.
DESIGN:
T=1.1 RC;
Let T = 200 µsec; C= 0.1µF => R =
CIRCUIT DIAGRAM:

PROCEDURE:
1. Connect the circuit as shown in circuit diagram.
2. Apply negative trigger to pin 2.
3. Observe and sketch the output wave form at pin 3.
4. Observe the output pulse width for different values of C and tabulate.

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 TABULATION:
R (k Ω) C (F ) Pulse width Pulse width
T (Practical) (ms) T (Theoretical) (ms)

MODEL GRAPH:

RESULT:
Thus IC555 timer was operated in Mono stable mode to generate square waveform.

Theoretical pulse duration =

Practical pulse duration =

30
DIGITAL

31
 EXPERIMENT NO.08
STUDY OF LOGIC GATES

AIM:
To study about logic gates and verify their truth tables.

APPARATUS REQUIRED:
SL No. COMPONENT SPECIFICATION QTY
1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. NAND GATE 2 I/P IC 7400 1
5. NOR GATE IC 7402 1
6. X-OR GATE IC 7486 1
7. NAND GATE 3 I/P IC 7410 1
8. IC TRAINER KIT - 1
9. PATCH CORD - 14
THEORY:

Circuit that takes the logical decision and the process are called logic gates. Each gate hasone or
more input and only one output.
OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as universal gates. Basic
gates form these gates.

AND GATE:
The AND gate performs a logical multiplication commonly known as AND function. Theoutput is
high when both the inputs are high. The output is low level when any one of the inputs is low.

OR GATE:
The OR gate performs a logical addition commonly known as OR function. The output is high
when any one of the inputs is high. The output is low level when both the inputs are low.

32
 NOT GATE:
The NOT gate is called an inverter. The output is high when the input is low. The outputis low
when the input is high.

NAND GATE:
The NAND gate is a contraction of AND-NOT. The output is high when both inputs arelow and
any one of the input is low .The output is low level when both inputs are high.

NOR GATE:
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low.The
output is low when one or both inputs are high.

X- OR GATE:
The output is high when any one of the inputs is high. The output is low when both theinputs
are low and both the inputs are high.

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

AND GATE:

SYMBOL: PIN DIAGRAM:

33
 OR GATE:

NOT GATE:

SYMBOL: PIN DIAGRAM:

34
X-OR GATE :

SYMBOL : PIN DIAGRAM :

2- INPUT NAND GATE:

SYMBOL: PIN DIAGRAM:

3- INPUT NAND GATE :

35
NOR GATE:

36
Result:
Thus, the logic gates were implemented and its truth tables were verified.

37
EXPERIMENT NO. 09

DESIGN OF HALFADDER AND FULL ADDER

AIM:
To design and construct half adder, full adder, half subtractor and full subtractor
circuits and verify the truth table using logic gates.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. AND GATE IC 7408 1
2. X-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
4. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 23

THEORY:

HALF ADDER:

A half adder has two inputs for the two bits to be added and two outputs one from the
sum ‘ S’ and other from the carry ‘ c’ into the higher adder position. Above circuit is
called as a carry signal from the addition of the less significant bits sum from the X-OR
Gate the carry out from the AND gate.
FULL ADDER:

A full adder is a combinational circuit that forms the arithmetic sum of input; it consists

of three inputs and two outputs. A full adder is useful to add three bits at a time but a half

adder cannot do so. In full adder sum output will be taken from X-OR Gate, carry output

will be taken from OR Gate.

LOGIC DIAGRAM:

HALF ADDER

38
TRUTH TABLE:

A B CARRY SUM

0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

39
 K-Map for SUM: K-Map for CARRY:

SUM = A’B + AB’ CARRY = AB

LOGIC DIAGRAM:

FULL ADDER
FULL ADDER USING TWO HALF ADDER

TRUTH TABLE:

A B C CARRY SUM

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

40
 K-Map for SUM:

SUM = A’B’C + A’BC’ + ABC’ + ABC

K-Map for CARRY:

CARRY = AB + BC + AC

PROCEEDURE:
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table

Result:

Thus, half adder and full adder were implemented and its truth tables were verified.

41
 EXPERIMENT NO. 10
DESIGN AND IMPLEMENTATION OF ENCODER AND DECODER

AIM:
To design and implement encoder and decoder using logic gates and study of IC
7445 and IC 74147.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. 3 I/P NAND GATE IC 7410 2
2. OR GATE IC 7432 3
3. NOT GATE IC 7404 1
2. IC TRAINER KIT - 1
3. PATCH CORDS - 27

THEORY:

ENCODER:
An encoder is a digital circuit that perform inverse operation of a decoder. An
encoder has 2n input lines and n output lines. In encoder the output lines generates the
binary code corresponding to the input value. In octal to binary encoder it has eight
inputs, one for each octal digit and three output that generate the corresponding binary
code. In encoder it is assumed that only one input has a value of one at any given time
otherwise the circuit is meaningless. It has an ambiguila that when all inputs are zero the
outputs are zero. The zero outputs can also be generated when D0 = 1.
DECODER:
A decoder is a multiple input multiple output logic circuit which converts coded input
into coded output where input and output codes are different. The input code generally
has fewer bits than the output code. Each input code word produces a different output
code word i.e there is one to one mapping can be expressed in truth table. In the
block

42
diagram of decoder circuit the encoded information is present as n input producing 2n
possible outputs. 2n output values are from 0 through out 2n – 1.

PIN DIAGRAM FOR IC

7445: BCD TO

DECIMAL DECODER:

43
PIN DIAGRAM FOR IC 74147:

LOGIC DIAGRAM FOR ENCODER:

44
TRUTH TABLE:

INPUT OUTPUT
Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C
1 0 0 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 1 1
0 0 0 1 0 0 0 1 0 0
0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 1 1 1 1

LOGIC DIAGRAM FOR DECODER:

45
 TRUTH TABLE:

INPUT OUTPUT
E A B D0 D1 D2 D3
1 0 0 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

Result:

Thus, encoder and decoder were implemented and its truth tables were verified.

46
 EXPERIMENT NO. 11

DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND

DEMULTIPLEXER

AIM:
To design and implement multiplexer and demultiplexer using logic gates and
study of IC 74150 and IC 74154.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. 3 I/P AND GATE IC 7411 2
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
2. IC TRAINER KIT - 1
3. PATCH CORDS - 32

THEORY:
MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a
smaller number of channels or lines. A digital multiplexer is a combinational circuit that
selects binary information from one of many input lines and directs it to a single output
line. The selection of a particular input line is controlled by a set of selection lines.
Normally there are 2n input line and n selection lines whose bit combination determine
which input is selected.
DEMULTIPLEXER:
The function of Demultiplexer is in contrast to multiplexer function. It takes
information from one line and distributes it to a given number of output lines. For this
reason, the demultiplexer is also known as a data distributor. Decoder can also be used as
demultiplexer.
In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates.
The data select lines enable only one gate at a time and the data on the data input line will
pass through the selected gate to the associated data output line.

BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

47
FUNCTION TABLE:

S1 S0 INPUTS Y
0 0 D0 → D0 S1’ S0’
0 1 D1 → D1 S1’ S0
1 0 D2 → D2 S1 S0’
1 1 D3 → D3 S1 S0

Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0

CIRCUIT DIAGRAM FOR MULTIPLEXER:

48
TRUTH TABLE:

S1 S0 Y = OUTPUT
0 0 D0
0 1 D1
1 0 D2
1 1 D3

BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

49
FUNCTION TABLE:

S1 S0 INPUT
0 0 X → D0 = X S1’ S0’
0 1 X → D1 = X S1’ S0
1 0 X → D2 = X S1 S0’
1 1 X → D3 = X S1 S0

Y = X S1’ S0’ + X S1’ S0 + X S1 S0’ + X S1 S0

LOGIC DIAGRAM FOR DEMULTIPLEXER:

50
TRUTH TABLE:

INPUT OUTPUT
S1 S0 I/P D0 D1 D2 D3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1

51
PIN DIAGRAM FOR IC 74150:

PIN DIAGRAM FOR IC 74154:

PROCEDURE:

52
 (i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

Result:

Thus, multiplexer and demultiplexer were implemented and its truth tables were
verified.

53
 EXPERIMENT NO. 12
DESIGN AND IMPLEMENTATION OF 3 BIT SYNCHRONOUS UP/DOWN
COUNTER

AIM:
To design and implement 3 bit synchronous up/down counter.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. JK FLIP FLOP IC 7476 2
2. 3 I/P AND GATE IC 7411 1
3. OR GATE IC 7432 1
4. XOR GATE IC 7486 1
5. NOT GATE IC 7404 1
6. IC TRAINER KIT - 1
7. PATCH CORDS - 35

THEORY:

A counter is a register capable of counting number of clock pulse arriving at its

clock input. Counter represents the number of clock pulses arrived. An up/down counter
is one that is capable of progressing in increasing order or decreasing order through a
certain sequence. An up/down counter is also called bidirectional counter. Usually
up/down operation of the counter is controlled by up/down signal. When this signal is
high counter goes through up sequence and when up/down signal is low counter follows
reverse sequence.

54
 K MAP

STATE DIAGRAM:

55
 CHARACTERISTICS TABLE:

Q Qt+ J K
1
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

LOGIC DIAGRAM:

56
 TRUTH TABLE:
Input Present State Next State A B C
Up/Down QA QB QA+1 Q B+1 J K JB K JC K
A A B C
QC QC+1
0 0 0 0 1 1 1 1 X 1 X 1 X
0 1 1 1 1 1 0 X 0 X 0 X 1
0 1 1 0 1 0 1 X 0 X 1 1 X
0 1 0 1 1 0 0 X 0 0 X X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
0 0 1 0 0 0 1 0 X X 1 1 X
0 0 0 1 0 0 0 0 X 0 X X 1
1 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
1 0 1 1 1 0 0 1 X X 1 X 1
1 1 0 0 1 0 1 X 0 0 X 1 X
1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 0 0 X 1 X 1 X 1

PROCEDURE:
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

Result:
Thus, 3 bit synchronous up/down counter were implemented and its truth tables
were verified.

57
 EXPREMENT:13

DESIGN AND IMPLEMENTATION OF SHIFT REGISTER

AIM:
To design and implement
(i) Serial in serial out
(ii) Serial in parallel out
(iii) Parallel in serial out
(iv) Parallel in parallel out

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. D FLIP FLOP IC 7474 2
2. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 35

THEORY:

A register is capable of shifting its binary information in one or both directions is

known as shift register. The logical configuration of shift register consist of a D-Flip flop
cascaded with output of one flip flop connected to input of next flip flop. All flip flops
receive common clock pulses which causes the shift in the output of the flip flop. The
simplest possible shift register is one that uses only flip flop. The output of a given flip
flop is connected to the input of next flip flop of the register. Each clock pulse shifts the
content of register one bit position to right.

58
 PIN DIAGRAM:

LOGIC DIAGRAM:

SERIAL IN SERIAL OUT:

59
 TRUTH TABLE:

Serial in Serial out

CLK

1 1 0
2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1

LOGIC DIAGRAM:
SERIAL IN PARALLEL OUT:

TRUTH TABLE:

OUTPUT
CLK DATA
Q QB Q Q
A C D
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1

60
 LOGIC DIAGRAM:
PARALLEL IN SERIAL OUT:

TRUTH TABLE:

CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1

LOGIC DIAGRAM:
PARALLEL IN PARALLEL OUT:

TRUTH TABLE:

61
 DATA INPUT OUTPUT
CLK D DB D D Q Q Q Q
A C D A B C D
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

Result:

Thus, the shift register was implemented and its truth tables were verified.

62
63
 SIMULATION EXPERIMENTS USING PSPICE
INTRODUCTION:
PSpice is the acronym for personal SPICE, which is acronym for simulation program with
integrated circuit emphasis. It is a type of program for simulating analog and digital circuits.
The type of simulation performed by PSpice depends on the source specifications and control
statements. The types of analysis usually executed in the PSpice program are as follows:
1. DC Analysis:- it is used for circuits with time – invariant sources (e.g., steady state dc
sources). It calculates all nodal voltages and branch currents over a range of values. The types of analysis
and their corresponding. (dot) commands are described below:
2. Transient Analysis:- It is used for circuits with time variant sources (e.g., ac
sources/switched dc sources). It calculates all nodes voltages and branch currents over a time interval and
their instantaneous values are the outputs. The corresponding. (dot) commands are as follows:
3. AC Analysis:- It is used for small signal analysis of circuits with sources of varying
frequencies. It also calculates all nodal voltages and branch currents (over a range of frequencies) and
their magnitudes and phase angles.

In PSpice, the circuit is first described to a computer by using a file called circuit file. It contains
the circuit details, viz., the information about source and commands for what to do and what to display as
output. The PSpice accepts circuit file as an input and after executing commands, creates and outputs file
to store results. However, the circuit to be analyzed is specified in terms of element names, element
values different sources (voltage or current) and different parameters.

PSpice calculates all nodal voltages and branch currents over a range of time interval by giving
the output of their instantaneous values. It can also perform other operations as will be evident later. For
circuits with variable frequency sources, AC analysis is used. Each circuit element is connected between
two nodes. All nodes must be connected to at least two elements and therefore appear twice at least.

OrCAD PSpice simulates analog-only circuits. After the preparation of a design for simulation,
OrCAD Capture generates a circuit file set. The circuit file set, containing the circuit netlist and analysis
commands, is read by PSpice for simulation.

PSpice formulates these into meaningful graphical plots, which can be marked for display
directly from schematic page using markers.

OrCAD® offers a total solution for core design tasks, schematic- and VHDL-based design entry;
FPGA and CPLD design synthesis; digital, analog, and mixed-signal simulation; and printed circuit board
layout.

64
Ex.No: 14 (a) SECOND ORDER ACTIVE FILTERS Date:

AIM: To simulate a second order Low pass filter & high pass filter using Pspice and to obtain their
frequency response.

SOFTWARE REQUIRED:
PC with Pspice software.
CIRCUIT DIAGRAM: Low Pass Filter

High Pass Filter:

PROCEDURE:
1. Open e-Sim.
2. Go to file option in the main menu and select new project.
3. Go to place part and select the components and place in the schematic window.
4. Add wires to all the components and specify the values of the components.
5. Go to Pspice in the main menu and check for errors in the netlist and set up the simulation profile by
adding required traces.
6. Observe the output waveform

65
RESULT:
Thus the low pass and high pass – second order filter circuit is simulated and the required frequency response
graphs are plotted.

66
 Ex.No:14 (b) ACTIVE BAND PASS FILTER Date:

AIM: To design and simulate a band pass filter using Pspice and to obtain the frequency response.

SOFTWARE REQUIRED:
System with Pspice software.

CIRCUIT DIAGRAM:

PROCEDURE:
1. Open e-Sim.
2. Go to file option in the main menu and select new project.
3. Go to place part and select the components and place in the schematic window.
4. Add wires to all the components and specify the values of the components.
5. Go to Pspice in the main menu and check for errors in the netlist and set up the simulation profile by
adding required traces.
6. Observe the output waveform

RESULT:
Thus the Active Band pass secondorder filter circuit is simulated and the required frequency response graphs
are plotted.

67
Ex. No: 14(a) ASTABLE MULTIVIBRATOR Date:
(USING OP-AMP AND IC 555 TIMER)
AIM: To simulate an astable multivibrator using Pspice.

APPARATUS REQUIRED:
System with Pspice software.

PROCEDURE:
Follow the same procedure as in the first simulation experiment.

CIRCUIT DIAGRAM: Using Op-Amp

Using 555 Timer

RESULT:
Thus the astable multivibrator circuit using 555 timer is simulated and the required waveforms are obtained.

68
Ex. No: 14(b) MONOSTABLE MULTIVIBRATOR Date:
AIM: To simulate monostable multivibrator using Pspice and to observe the waveforms.

SOFTWARE REQUIRED:
Sytsem with Pspice software.

CIRCUIT DIAGRAM:

CIRCUIT DIAGRAM USING 555 TIMER

PROCEDURE:
Follow the same procedure as in the first simulation experiment.

RESULT:
Thus the monostable multivibrator circuit using 555 timer is simulated and the required waveforms are obtained.

69
70
71
 SAMPLE VIVA-VOCE QUESTIONS AND ANSWERS
1. Define operational amplifier
Ans: Op-amp is an operational amplifier capable of performing mathematical operations such as addition,
subtraction, multiplication, logarithm, anti-logarithm, integration, differentiation etc and amplification. It
is a multi stage differential amplifier which is in wide variety of applications.
2. What is the difference between ordinary amplifier and operational amplifier?
Ans: An ordinary amplifier can only amplify the given input signal. But, an operational amplifier can
perform many mathematical operations with enormous gain.
3. What are the different types of op-amp configurations available?
Ans: Op-amp configurations are broadly subdivided into two types. They are open-loop and Closed-loop
configurations. Open loop configurations are of three types. They are Inverting, Non-inverting and
differential configuration. Closed-loop configurations are of three types. They are Inverting, Non-
inverting, buffer amplifier and differential configuration. The differential configuration of closed-loop op-
amp is further subdivided into two types. They are configuration with one op-amp and configuration with
two op- amps.
4. Which is the basic building block of operational amplifier?
Ans: The basic building block of op-amp is differential amplifier. A differential amplifier amplifies the
difference between two input signals.
5. Mention some of the applications of op-amp.
Ans: Op-amps are mainly used in analog system design. They are used for wide variety of applications
such as mathematical operations, data acquisition systems, process control, programmable gain
amplifiers, automotive instrumentation and control, communication ICs, radio/audio/video ICs, analog
computers, A/D converters etc.
6. Can an op-amp be used for both AC and DC Applications?
Ans: Yes. Op-amps can be used for both AC and DC applications. This is one of the important features of
an op-amp. They have the ability to process both AC and DC input signals.
7. Why negative feedback is preferred in op-amp?
Ans: In most of the op-amp application, negative feedback is preferred to decrease the overall voltage
gain. Open-loop gain is huge and this is minimized by using two resistors. Input resistor and feedback
resistor is used to control the gain and thus suitable for many practical applications.
8. List out the ideal characteristics of op-amp.
Ans: The ideal characteristics of op-amp are
i) Open-loop gain must be infinite. AoL = ∞
ii) The input impedance must be infinite. Ri = ∞
iii) The output impedance must be zero. Ro = 0
iv) Common Mode Rejection Ratio must be infinite. CMRR = ∞
v) Slew rate must be infinite. dvo/dt = ∞
vi) It must not provide output when there is no input. Vo = 0; when Vi = 0.
vii) Differential mode gain must be infinite. Ad = ∞
viii) Common mode gain must be zero. Ac = 0
9. Define slew rate. What causes it? Mention the effects and methods of minimizing Slew rate.
Ans: It is the rate at which the output voltage changes with respect to time. It tells how fast an output of
op- amp can change. Example: For a general purpose op-amp 741, the maximum slew rate is 0.5V/μs.
This means, the output voltage can change a maximum of 0.5V in 1 μs. Slew rate is a major limiting
factor for op-amps operating at high frequency.
Slew rate can also be given as the maximum current flowing through a compensating capacitor. S.R =
I/C. Op-amp with slew rate greater than 100V/μs are termed as “High Speed Op-amps”. For special
applications such as video systems, op-amps with slew rate of 1000V/μs are available.
CAUSES OF SLEW RATE:
72
The worst case, or slowest slew rate, occurs at unity gain. Therefore, slew rate is usually specified at unity
gain. Slew rate depends on many factors: the amplifier gain, Compensating capacitors, the current
flowing through the compensating capacitor and even whether the output voltage is going positive or
negative.
If Vi is a sine wave, with a peak amplitude of Vp, the maximum rate of change of Vi depends on both its
frequency f and peak amplitude. It is given by 2πfVp. If this change is larger than op-amps slew rate, the
output Vo will be distorted.
If a step input is given, it is observed that above certain step amplitude the output slope saturates at a constant
value called slew rate (SR). When the frequency of a train of square wave given to a voltage follower is
constantly increased, the shape of the output will be a triangular wave instead of square.
Methods of Minimizing Slew Rate
The minimization methods can be summarized with the use of following expression. SR =
2πIf / gm
By increasing the frequency f.
By reducing the input stage transconductance gm.
By increasing the current I flowing through the capacitor.
Or by reducing the value of compensation capacitor Cc (which increases the frequency)
10. What is the maximum voltage that can be given at the inputs?
Ans: The inputs must be given in such a way that the output should be less than Vsat.
11. Why op-amps cannot be used in open-loop configuration?
Ans: Op-amp in open loop configuration has enormous gain. For example the op-amp 741 has a typical gain
of 200,000 (106 dB) & op-amp OP-77 has a typical gain of 12 million (141.6 dB). This huge gain is not
necessary for most of the application of op-amp. Since op-amp output will saturate at ±Vsat (positive and
negative saturation) which is approximately equal to ±V (Supply voltage)
12. Can a op-amp be operated using single power supply?
Ans: No. All the general purpose op-amp must be operated with two power supplies. Since, the differential
amplifier has two supply : +Vcc and – Vee, the op-amp which is a multi stage differential amplifier stage
must also have two supply voltages. However, op-amps with single supply voltage are also used for very
few applications.
13. Define offset voltage and state its significance.
Ans: When an op-amp has no inputs given, there is a possibility of getting output because of small voltage at
input terminals. This very small voltage difference between the two terminals of op-amp resultsdue to the
slight mismatch between the characteristics of two transistors present in the starting stage of op-amp. If a
small voltage appears across the input terminals of op-amp, then because of the huge gain of op-amp, the
amplified output will result even when there is no input. So a voltage must be applied by the user to
cancel out the effects. The voltage that must be applied to nullify the output voltage is called as offset
voltage.
14. List the important features of op-amp 741.
Ans: Features of op-amp 741
1. No frequency compensation required.
2. Short circuit protection
3. Offset voltage null capability
4. Large common mode and differential voltage ranges
5. Low power consumption
6. No latch-up
15. How to construct a adder circuit using op-amp?
Ans: A two input summing amplifier may be constructed using the inverting mode. The adder can be obtained
by using either non-inverting mode or differential amplifier. Here the inverting mode is used. So the
inputs are applied through resistors to the inverting terminal and non-inverting terminal is grounded. This
is called “virtual ground”, i.e. the voltage at that terminal is zero. The gain of this summing amplifier is 1,
any scale factor can be used for the inputs by selecting proper external resistors.
73
16. List all Specifications of op-amp 741
Ans:
1. Voltage gain A = α typically 2,00,000
2. I/P resistance RL = α Ω, practically 2MΩ
3. O/P resistance R =0, practically 75Ω
4. Bandwidth = α Hz. It can be operated at any frequency
5. Common mode rejection ratio = α
(Ability of op amp to reject noise
voltage)
6. Slew rate + α V/μsec
(Rate of change of O/P voltage)
7. When V1 = V2, VD=0
8. Input offset voltage (Rs ≤ 10KΩ) max 6 mv
9. Input offset current = max 200nA
10. Input bias current : 500nA
11. Input capacitance : typical value 1.4pF
12. Offset voltage adjustment range : ± 15mV
13. Input voltage range : ± 13V
14. Supply voltage rejection ratio : 150 μV/V
15. Output voltage swing: + 13V and – 13V for RL > 2KΩ
16. Output short-circuit current: 25mA
17. supply current: 28mA
18. Power consumption: 85mW
19. Transient response: rise time= 0.3 μs
17. What is the maximum voltage that can be given at the inputs?
Ans: The inputs must be given in such a way that the output should be less than Vsat.
18. How to construct a Subtractor?
Ans: A basic differential amplifier can be used as a subtractor. Input signals can be scaled to the desired
values by selecting appropriate values for the resistors. When this is done, the circuit is referred to as
scaling amplifier. However in this circuit all external resistors are equal in value. So the gain of amplifier
is equal to one. The output voltage Vo is equal to the voltage applied to the non-inverting terminal minus
the voltage applied to the inverting terminal; hence the circuit is called a subtractor.
19. Why op-amp integrator is called as precision Integrator?
Ans: The op-amp integrator has a high degree of accuracy. And it can
precisely implement the output voltage expression. Because of this, op-amp integrator
is often called as precision integrator.
20. Mention some of the applications of integrator.
Ans: Op-amp integrator finds wide application in function generators
(Triangle and sawtooth wave generators), active filters (State variable & biquad
filters, Switched Capacitor filters), Analog to Digital Converters (Dual-slope
converters, Quantized feedback converters) and Analog controllers (PID Controllers).
21. What are the problems faced by basic ideal integrator and how can
we overcome ?
Ans: The input offset voltage Vio and the part of input current charging thefeedback capacitor Cf produces the
error voltage at the output of the ideal integrator. Therefore, in practical integrator, to reduce the error voltage at
the output, a resistor Rf is connected in parallel to Cf. This Rf, limits the low-frequency gain and hence
minimizes the variations in the output voltage. Both stability and the roll-off problemsin basic ideal integrator
canbe corrected by additional resistor Rf.
22. What is other name given to practical integrator?
Ans: The method of preventing saturation in integrator is to place a parallel resistance Rf with Cf. The resulting
circuit is called as lossy integrator (Practical Integrator) which can still provide integration function. But, only
over a limited frequency range. In most applications, integrators are placed in a control loop to avoid saturation
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and there is no need for Rf in such applications.
23. What is meant by negative resistance?
Ans: Negative resistance indicates the release of power. Negative resistance
can be used to neutralize unwanted ordinary resistance, as in the design of current sources or to control the pole
location, as in the design of active filters and oscillators.
Integrator is otherwise called as fixed frequency, variable gain LPF. True or False?
Ans: True.
24. Give the meaning and use of Virtual ground.
Ans: If the difference input voltage is ideally zero, and non-inverting terminal
is grounded with a input signal applied to the non-inverting terminal via R1, then voltage at the inverting terminal
is approximately equal to voltage at the non-inverting terminal. This is known as virtual ground (A terminal that
is not connected to physical ground but, assumed to be.) It is much used in closed-loop analysis of inverting
amplifier.
25. How integrator is useful in constructing Servo Amplifer?
Ans: A Servo Amplifier is constructed when an integrator is followed by an inverting amplifier. Servo amplifiers
are used where the output is a delayed response to the input. Example: Radar (or) Position of a xy table in a
manufacturing process.
26. How to convert an op-amp integrator to op-amp differentiator?
Ans: To convert a op-amp integrator to differentiator, just replace the feedback capacitor Cf as feedback resistor
Rf. And replace the input resistor R1 as input capacitor C1 of an integrator.
27. How ideal differentiator suffers from instability? How can we overcome them?
Ans: The ideal or basic differentiator‟s circuit gain (Rf/R1) increases with increase in frequency at a rate of
+20dB/decade. This makes the circuit unstable. Also, the impedance Xc1 decreases with increase in frequency,
which makes the circuit very susceptible to high frequency noise. When amplified, this noise can
completely override the differentiated output signal. Both stability and high frequency noise can be corrected by
addition of two components R1 and Cf. This circuit is called as practical differentiator.
28. What is the condition to be followed for proper differentiation?
Ans: The input signal will be differentiated properly if the time period T of the input signal is larger than equal to
RfC1. That is T ≥ RfC1.
29. How high frequency noise affects the performance of an differentiator?
Ans: Due to poor Stability (i.e) Circuit tends to oscillate and gain of the circuit increases with an increase in
frequency. So high frequency noise is amplified and is dominant at the output.
30. Determine the output of differentiator for the following input waves.
Ans: The inputs and respective output waveform of differentiator are as follows, Sine Wave Negative Cosine
Wave, Sine Wave, Square Wave, Spike Wave, Sawtooth Wave, Square Wave
31. Give some important applications of differentiator.
Ans: Differentiator is most commonly used in wave shaping circuits to detect high frequency components in an
input signal and also as a rate-of-change detector in FM modulators.
32. What is Unity Gain Frequency?
Ans: Unity-gain frequency of op-amp differentiator is the frequency at which the gain is unity (0 dB).
33. What is UGB?
Ans: Unity Gain Bandwidth (UGB) is the bandwidth of op-amp when the voltage gain is 1. It is also called as
Closed-loop bandwidth, Gain-Bandwidth Product or Small signal bandwidth.
34. What are the important requirements of an instrumentation Amplifier?
Ans: The requirements of an instrumentation amplifier are low noise, low thermal and time drifts, high input
impedance, accurate closed-loop gain, high CMRR and high Slew Rate.
35. List the characteristics of a basic three op-amp instrumentation amplifier.
Ans: For 3 op-amp instrumentation amplifier, the characteristics are
The voltage gain, from differential input to single ended output is set by only one resistor.
The input resistance of both inputs are very high and does not change as the gain is varied.
Vo does not depend on the voltage common to both inputs (Common- mode rejection) but, only on their
difference.
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36. Mention some of the applications of an instrumentation amplifier.
Ans: Instrumentation Amplifier is used in data acquisition unit, sensing, measurement & Control of physical
parameters such as temperature, used as signal conditioning circuit, Light-intensity meter, Measurement of flow
and thermal conductivity, Analog-weight scale, Active guard drive, digitally programmable gain and output
Offsetting.
37. What are the Different configurations of instrumentation amplifier? What are the merits and demerits?
Ans: There were four configurations. They are
Triple op-amp IAs
Dual op-amp IAs
Monolithic IAs
Flying-Capacitor IAs Triple op-amp IA :
Offers high impedance because of buffer stage and too many components used. Dual op-amp IA:
Offers less Complexity in circuit (with fewer resistors & op-amps) with Significant boost in performance. But it
treats the input asymmetrically with Some delay.
Monolithic IA :
Better optimization of CMRR, gain linearity and noise reduction. Flying-Capacitor IA :
Excellent CMRR, as common mode signals are completely ignored.
How many stages does a three op-amp instrumentation amplifier contain? And what are they? Ans: A common
op- amp instrumentation amplifier uses 3 op-amps and seven resistors which is splitted into two stages. i) Buffer
stage (High impedance) Differential
input- differential output stage. ii) Difference amplifier stage.
38. What is the disadvantage of a instrumentation amplifier?
Ans: The requirement for instrumentation amplifier is too strict to follow for
general purpose applications. When the requirements are not too strict, then a general purpose op-amp can be
used in differential mode. Such amplifiers are called as differential instrumentation amplifier.
39. What is the use of op-amp buffer?
Ans: Op-amp buffer or voltage follower is a unity gain, high input impedance
and very low output impedance circuit used to provide isolation between two stages of an system.
40. What is meant by passive and active filters?
Ans: Passive filters: Uses Resistors, Capacitors and inductors as elements.
Active Filters: Uses Transistors or op-amps in addition to Resistors and Capacitors.
41. Why active filters are not suitable for high frequency applications?
Ans: Above MHZ range the op-amp open-loop gain rolls-off with increase in frequency.
42. List some of the applications of filters.
Ans: Filters are an integral part of electronic networks and are used in application from audio circuits to Digital
Signal Processing (DSP) Systems such as speech, audio, Video, Image processing etc.,
43. How Active filters are superior than passive filters?
Ans: Advantage of active filters over passive filters
Gain and frequency adjustment flexibility.
No loading problem.
Low Cost.
44. How Filters are classified and what are they?
Ans: Based on passband, stopband and cutoff frequency, filters are classified into Lowpass, Highpass, Bandpass,
Bandstop and Allpass filters.
45. What are poles and zeros?
Ans: Zeros are numerator and poles are denominator polynomials of the transfer function of a filter. Poles and
Zeros determine the characteristics of a filter.
46. Does a filter affect both amplitude and phase of the input signal?
Ans: Yes.
47. What is the use of bode plot?
Ans: The Bode Plots are plots of decibels and degrees versus decades (or Octaves). The purpose of bode plot is to

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represent both logarithmic and semi-logarithmic scales.
48. In what basis the order of the filter is decided?
Ans: Based on the parameter „n‟, the order of the filter is decided. n=1; First order, n=2; Second order and so on.
The parameter „n‟ decides the accuracy of the filter primarily at the stopband (Rolloff). Higher the value of n,
better the filter will be and complex the design will be.
49. Define Bandwidth of a filter.
Ans: Bandwidth of a filter is defined as higher cutoff frequency minus lower cutoff frequency. Or in other words
it is the difference between Upper cutoff frequency and Lower cutoff frequency. Bandwidth is expressed in HZ.
B.W = fH – fL HZ
50. What do you understand from the frequency response of filter?
Ans: There were three cases that should be noted in any filter except allpass filter. The three cases for LPF filter
for example is given as
Case i: If the input frequency fin is less than the higher cutoff frequency fH, then magnitude of the gain is
maximum and it is given as passband gain of the filter AF. Case ii If the input frequency fin is equal to the cutoff
frequency, then the gain magnitude will be 70.7% of the maximum gain
Case iii: If the input frequency fin is greater than the higher cutoff frequency fH, then magnitude of the gain is
maximum and it is given as passband gain of the filter AF.
51. How filters are classified according to their band characteristics?
Ans: Filters are classified according to their passband and stopband characteristics. Butterworth Flat passband and
flat stopband (Flat-Flat filter) Chebyshev Ripple passbad and flat stop band Ripple passband and Ripple Stopband
52. How to convert a BPF to BSF?
Ans: Swap HPF-LPF series connection of BPF to LPF-HPF series connection to achieve Bandstop filter (BSF)
which is also called as BEF(Band Elimination Filter) or Notch Filter.
53. What is the function of a all pass filter?
Ans: This filter passes all frequencies well but it provides phase shift between input and Output voltage which is a
function of frequency.
54. List the applications of BPF.
Ans: It acts as frequency selector, stereo-equalizer octave filter, communication transmitter and receiver circuits,
radio, TV broadcast receivers, telephone, radar, space satellites and bio-medical equipment.
55. Write the way of constructing a I order Butterworth BPF.
Ans: I order Butterworth BPF can be constructed using I order Butterworth HPF followed by I order Butterworth
LPF.
56. Why inductors cannot be used with active filters?
Ans: Because, inductors are bulky due to windings and cannot be fabricated inside an IC.
57. What is the condition for stability of a network?
Ans: All the poles in unit circle must fall on the left half of the S-plane during mapping for Passive network
(Filter) The location of the poles determines the stability conditions for active network. All the roots must have
negative real parts for a active network (Filter). Also there are no changes in the signs of the first column of the
routh array.
58. Define multivibrator.
Ans: A multivibrator is an oscillatory circuit capable of generating waveforms without any Specific input signal.
The circuit only has supply voltage connections, from which the two amplifiers saturates one another to generate
vibrations.
59. State the relationship between Astable multivibrator and a comparator.
Ans: Astable multivibrator is almost a comparator except the trigger or threshold voltage will be generated on
its own.
60. What is the major difference between astable and monostable multivibrator?
Ans: In astable multivibrator there is no stable state and no triggering input. But, monostable multivibrator has
one stable state and works based on the triggering pulse
input.
61. Which Determines the switching time of a multivibrator?
Ans: The threshold value determines the switching time of a multivibrator. When ever a capacitor voltage
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exceeds │VT│, the output state changes.
62. List some applications of multivibrator.
Ans: Multivibrators are mostly used for timing applications. Astable multivibrator is primarily used as square
wave generator in a function generator. Monostable
Multivibrator is used for timed control applications with the help of triggering input.
63. Say how to form a triangular wave generator using multivibrator?
Ans: To construct a triangular wave generator, a Astable multivibrator should be followed by an integrator.
Square wave is generated first and then converted to triangular with the help of integrator.
64. Define stable state.
Ans: The time over which a multivibrator output voltage stays constantly is called as stable state. A quasi-stable
in the other hand depends on the triggering input to regain the output state.
Give the relationship between tp and T of a monostable multivibrator. Ans: The Triggering pulse width „tp‟ must
be much smaller than the ON time „T‟ of Stable State.
65. What is a Schmitt trigger?
Ans: Schmitt trigger is the inverting comparator with positive feedback. The
other names given for Schmitt trigger circuit is regenerative comparator and squaring circuit. It is mainly used in
converting any irregular shaped waveform into square wave or pulse. So it is used in wave shaping circuit.
66. Write the truth table of a comparator.
Ans: Truth table of a Comparator When V+ > V- +Vsat
When V+ < V- - Vsat
When V+ = V- High Impedance State
67. What is Comparator chatter? And how can we eliminate it?
Ans: For slowly varying signals, comparators tend to produce multiple output transitions, or bounces, as input
crosses the threshold region. This is referred to as comparator chatter. This phenomenon is eliminated with the
help of Hysteresis. In hysteresis the circuit snaps and activates the other threshold.
68. What happens when both threshold points in a Schmitt trigger is equal to zero?
Ans: When VUT = VLT = 0, the Schmitt trigger behaves as a zero crossing detector. There were two types of
Schmitt trigger. They are positive and negative Schmitt trigger.
69. Can a Schmitt trigger can be operated with single supply & single threshold voltage?
Ans: Schmitt trigger can also be operated with single power supply or with a single triggering input (Either
Positive or Negative)
70. According to oscillations how oscillators are classified?
Ans: Based on how oscillations are created, oscillations are classified as under damping, over damping and
constant amplitude oscillations.
71. How oscillations are created in RC phase shift and wien Bridge oscillator?
Ans: When the bridge is balanced and the overall phase attained is 0°, the
Wien bridge oscillator produces oscillations. RC phase shift oscillator produces 360° of phase shift in two
parts. Firstly, each and every RC pair in the feedback network produces 60° phase shift and a totally there
were three pairs, thus producing 180°
Phase shift and secondly, the feedback input is given to the inverting terminal of opamp to produce another
180° phase shift and a total phase shift of 360°.
72. What are the merits and demerits of different types of oscillator?
Ans: The major problem in Wien bridge oscillator is balancing the bridge
becomes very difficult when the component values drifts unfortunately due to external or internal conditions.
Poor stability and low frequency application is the demerits of RC phase shift Oscillator. Both RC phase shift
and Wien bridge oscillator have a advantage that its operating frequency can be easily varied by just replacing
the values of either R or C to a new value. Crystal oscillator has excellent stability and poor deviation.
73. Why Timer IC is numbered as 555?
Ans: The timer IC is called as 555, because the internal architecture consists of three 5KΩ resistors.
74. What are the different operating modes of 555 Timer?

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Ans: There were two operating modes of 555 Timer. It operates in Astable and Monostable mode.
75. What are the different types of packages available for 555 Timer IC?
Ans: The packages used for 555 Timer are 8-pin mini Dual-Inline-Package (DIP) and 8-pin Metal Can.
76. List some applications of 555 timers in both Astable mode and Monostable Mode.
Ans: In Astable mode of operation, some of the applications of 555 Timer were: Tone- burst oscillator, Voltage
controlled frequency shifter, square wave generator etc., In Monostable or one-shot mode, some ofthe
applications of 555 timer were: Water-level fill control, Touch switch, Frequency divider, missing pulse
detector and many more.
77. What is a PLL?
A PLL is a Phase Locked Loop Circuit used to track any changes in the input frequency.
78. What are the operating modes of an PLL?
A PLL functions in any in any one of the mode described here.
Free Running mode
Capture mode Lock
mode and
Tracking mode/range
79. What are the basic building blocks of a PLL IC?
The basic building blocks of PLL IC are 1) Phase comparator 2) Low Pass Filter and 3) Error Amplifier.
80. What is meant by free running mode of a PLL?
A PLL is said to be in this mode when there is no input frequency given to phase comparator for comparison.
When no input is given, PLL runs freely without any locking or tracking and so it is called as free running
mode of PLL.
81. Name some of the applications of PLL IC 565.
PLL ICs are mostly used in frequency application circuits such as Frequency synthesizer, frequency multiplier,
frequency divider, phase comparator, FM demodulator, PM demodulator, Phase magnitude comparator, etc.,
82. Why PLL Circuit is mostly preferred in Frequency Applications?
It is preferred in most of the frequency applications because the frequency content of a signal is indirectly
proportional to Phase of the same signal. As we compare the phase of the two signals, we indirectly compare
the frequency of the same signal. This is due to the fact that direct phase is nothing but indirect frequency and
direct frequency is nothing but indirect phase.
83. What happens when the two input signals given to PLL is having same frequency or same phase?
When both the inputs are same, the PLL will start functioning in the Lock mode and if once lock has been
occurred, the PLL will start tracking the Phase or frequency changes in the input signal.
84. What is VCO?
VCO is the integral part of PLL. A VCO is the Voltage Controlled Oscillator. As the name implies itgenerates
oscillations according to the input voltage. This VCO is placed in the feedback path of a PLL. The output of
the VCO is changing according to the Error output voltage from the error amplifier placed finally in the
forward path.
85. Mention Some Important DAC characteristics.
Ans: Resolution, Full-scale output Voltage, Offset error, Gain error, Monotonocity and Relative accuracy.
86. What are the different types of D/A Converter techniques available?
Ans: The different types of DAC techniques are Binary
weighted DAC
R-2R Ladder network Inverted
R-2R ladder network Current
Driven DAC
87. Define resolution of a DAC.
Ans: The resolution is nothing but the number of distinct analog outputs that can be produced by DAC. It is given
as Resolution = 2n Where „n‟ is the number of digital inputs. Example: For 3 inputs DAC there are 8 distinct
outputs.

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