Stony Brook University Department of Electrical and Computer Engineering

ESE 324 Electronics Laboratory C Spring 2012

Lab 2: XOR Based Phase Detector Design

Objectives 1) Design a simple XOR based phase detector. 2) Understand the fundamental design constraints of a phase detector such as maximum operating speed, and dead zone. 3) Design two different implementations of a phase detector. 4) Understand the differences between a transmission gate based phase detector and static CMOS based phase detector. Background Phase detector is a circuit that produces an output signal whose average value is linearly proportional to the phase difference between the two inputs. Referring to the following figure, the slope of the line is referred to as the gain of the phase detector. The output is voltage and input is a phase difference so the gain is measured in V/rad.

A phase detector is a highly important circuit block for a variety of applications including motor control and telecommunication systems. A simple phase detector can be implemented as an XOR gate. As shown in the figure below, the width of the output pulse varies as the phase difference between the inputs varies. The average DC value of the output signal is proportional to the phase difference of the input signals.

Two important design specifications of a phase detector are maximum operating frequency and dead zone. The first parameter refers to the highest frequency of the input signals for which the phase detector can reliably produce the output. The second specification refers to the minimum phase difference that the phase detector can reliably detect. The condition to determine the maximum operating frequency may vary based on the application. In this experiment, we will assume the following condition: Condition to determine the maximum operating frequency: Phase detector is considered to reliably detect the phase if the output reaches to at least 70% of the Vdd (in our case this is equal to 3.5 volts) when the input signal is at half the bit period. This condition is described in the figure below. Assume the other input of the phase detector is connected to VDD, so the phase detector functions as an inverter.

Both design specifications (operating frequency and dead zone) are highly dependent on the propagation delay of the XOR gate. To measure the propagation delay, we will assume 50% of the transition as the threshold. The measurement of the propagation delay is illustrated in the figure below:

Preliminary Lab Read the laboratory document carefully before coming to the lab. Understand the requirements of each step. It will save you time if you setup the first schematic before coming to the lab. Parts: Two/three CD 4007s 100 pF capacitor 10 pF capacitor

Laboratory Experiment Part 1

Figure 1 1) Build an XOR based phase detector using transmission gates, as shown in Figure 1. You will use four NMOS and four PMOS transistors. To build this circuit, you will need two CD 4007s. Remember to connect pin 14 to VDD and pin 7 to VSS for both ICs. Note that VDD = 5V and VSS = 0 V. Obtain the truth table of the XOR gate by filling the table below and verify that the gate functions correctly. If the circuit does not initially work as expected, debug your circuit by probing different nodes and find the node that has an unexpected voltage.

A VSS VDD VSS VDD

B VSS VSS VDD VDD

Vout

Part 2 In this part, you will measure several different propagation delays in your phase detector. Start with both inputs set to VSS. The output should also be at VSS. Then, provide a 1 kHz square wave to input A from 0 to 5 volts, as shown below:

1) Record the output waveform. Then, measure low-to-high propagation delay (tLH)A of the output when the input A changes from VSS to VDD. Also, measure the high-to-low propagation delay (tHL)A of the output when the input A changes from VDD to VSS. 2) In the second step, set input A to zero and provide a 1 kHz square wave from 0 to 5 volts to input B. Then, measure low-to-high propagation delay (tLH)B of the output when the input B changes from VSS to VDD. Also measure the high-to-low propagation delay (tHL)B of the output when the input B changes from VDD to VSS. Remember to measure the propagation delay between the two points that correspond to 50% transition of the signal (check background section). Insert the values into the table below. 3) By looking at the schematic and considering the voltage transitions, describe why the delays are different. Explain why (tLH)B is relatively higher than (tLH)A. Delay (tLH)A (tHL)A (tLH)B (tHL)B Part 3 1) Connect input A to VDD. Provide a square wave (from 0 to 5 volts) to input B with four different frequencies as follows: f1 = 50 kHz, f2 = 500 kHz, f3 = 800 kHz, f4 = 3 MHz.

Record output waveform for each frequency and measure the current drawn from the primary power supply for each frequency. Fill in the table below and plot a graph showing the relationship between frequency versus current. Signal frequency at input B 50 kHz 500 kHz 800 kHz 3 MHz Total current drawn from VDD

Remember that when one of the inputs is connected to VDD, the phase difference between the two signals is equal to the inverse of the second input. Comment on the behavior of the output signal as the frequency is increased. 2) Typically, every phase detector has a highest operating frequency beyond which the phase detector fails to reliably detect the phase. The condition to determine the maximum operating frequency may vary depending upon the application. Considering the condition described in the background section, determine the maximum operating frequency for two cases (remember that the input A is connected to VDD): Case 1: Duty cycle of the square wave at input B is 50% Case 2: Duty cycle of the square wave at input B is 80% For both cases, record your output waveform. Determine the maximum frequency and fill in the table below. Note that you can adjust the duty cycle of the signal by using function generator. Explain why the maximum frequency is reduced when the duty cycle increases. Duty cycle of the square wave at input B 50% 80% Part 4 1) In this part, change the load capacitor from 100 pF to 10 pF and fill in the tables below by repeating the same steps as above Maximum frequency

Delay (tLH)A (tHL)A (tLH)B (tHL)B

Signal frequency at input B 50 kHz 500 kHz 800 kHz 3 Mhz

Total current drawn from VDD

Duty cycle of the square wave at input B 50% 80%

Maximum frequency

2) Explain how the capacitor affects the delay, maximum operating speed, and overall current drawn from the power supply. Part 5

Figure 2 In this part, you will design another XOR based phase detector. However, instead of using transmission gates, you will adopt a static CMOS implementation. Build the circuit shown in Figure 2 using CD4007 ICs. 1) Obtain the truth table of the XOR gate by filling the table below and verify that the gate functions correctly. If the circuit does not initially work as expected, debug your circuit by probing different nodes and find the node that has an unexpected voltage.

A VSS VDD VSS VDD

B VSS VSS VDD VDD

Vout

Following the similar steps as you did for the transmission gate based XOR, fill in the tables below. 2) Measure different propagation delays Delay (tLH)A (tHL)A (tLH)B (tHL)B 3) Vary the frequency and record output waveform for each frequency. Measure the current drawn from the primary power supply for each frequency. Plot a graph showing the relationship between frequency versus current. Signal frequency at input B 50 kHz 500 kHz 800 kHz 3 MHz Total current drawn from VDD

4) Determine the maximum operating frequency at two different duty cycles. Record the output waveform for both values. Remember the condition described in the background section. Duty cycle of the square wave at input B 50% 80% Part 6: 1) Change the output capacitor from 100 pF to 10 pF and repeat the same steps and fill in tables below: Delay (tLH)A (tHL)A (tLH)B Maximum frequency

(tHL)B

Signal frequency at input B 50 kHz 500 kHz 800 kHz 3 MHz

Total current drawn from Vdd

Duty cycle of the square wave at input B 50% 80%

Maximum frequency

1) Explain how the capacitor affects the delay, maximum operating speed, and overall current drawn from the power supply when XOR is implemented utilizing CMOS static logic.

Part 7 Looking at all of your results, compare the overall performance of transmission gate based phase detector with static CMOS based phase detector. Compare the number of transistors, speed, and power consumption.