AKKAPALLI SARITHA LinkedIn: www.linkedin.
com/in/saritha-akkapalli-5486011a4
Name AKKAPALLI SARITHA
Designation Design Verification Engineer
Email Id [email protected]
Mobile No +91-8790064729
Highest B.Tech in Electronics and Communication Engineering
Education
Key Skill Set
Digital Design
HDL : Verilog, System Verilog, UVM
Scripting Language : TCSH, TCL, Perl, Gvim, Linux
Tools : Synopsys VCS tool, Cadence, Xilinx IDE, MATLAB.
Platforms : Windows, Linux.
Programming Language : C, C++
Protocols : AMBA AXI,AHB,APB, ADC,CAN,I2C,SPI,UART
Pre-layout GLS
Academic Profile:
Degree School/College/Institute Board/University Div/Marks Year of
passing
B. Tech (ECE) Trinity college of engineering JNTUH 8.01(CGPA) 2020
and technology, Karimnagar.
10+2 Trinity Junior college, Board of Intermediate 95% 2016
Karimnagar Education
10th Valmiki Vidyalayam, Board of Secondary 9.8(CGPA) 2014
Karimnagar Education
Experience Summary:
Capgemini Engineering, Hyderabad, India.
Role/Designation: DV Engineer
Duration : 24 March 2022 to present
Sumedha IT, Hyderabad, India.
Role/Designation : DV Trainee
Duration : 9/2021 to 2/2022.
Profile Summary:
• 3 Years of experience in Design Verification.
• Worked on Subsystem and ChipTop level verification for a SOC project.
• Worked on Subsystem and ChipTop level pre-layout GLS for a SOC project.
• Extensive Skills in Verilog, System Verilog, and Verification Methodologies like UVM.
• Having a good working knowledge of CAN, ADC, I2C, UART, and GPSB Protocols. and
basic knowledge of ARM AMBA Protocols – APB, AHB, AXI.
• Worked on AXI VIP integration at SOC level
• Worked on coverage-based constraint random verification and Assertion-based verification.
• Worked on Functional, Code, and Toggle coverage.
• Very good knowledge of debugging issues at block level.
• Strong in digital design fundamentals.
Achievements & Awards:
• Got recognition and received a WOW AWARD for contributions and good technical work
in the Telechips AXON SOC project
• Presented project in national level conference (Nagpur).
• Won first prize in PPT presentation on BRAIN COMPUTER INTERFACE.
• Got Merit certificate on workshop in multisim and PCB at JNTUH Kondagattu, Jagityal.
• Presented a paper on BRAIN PORT VISION DEVICE in a national-level conference on
emerging trends in technology.
• Received training certificate in the language C++.
• Participated in a workshop on ORACLE JAVA PROGRAMMING.
• Participated in the district-level NATIONAL CHILDREN’S SCIENCE CONGRESS.
• Received merit participation certificate in INDO GLOBAL EDUCATION EXPO and SUMMIT.
Strengths:
#Techinical expertise #problem-solving skills #Analytical thinking
#Team collaboration #Attention to detail #Time Management
Project Details:
Project 1: Telechips ADM3 SoC Dev(AXON)
Location: Capgemini, Hyderabad
Client: Telechips
Duration: 04/2022 - 07/2024
Role/Title Verification of IOSS
Contribution: Responsibilities
• Coded all the test cases of register reset and read/write
operation verification of each IP(ADC, CAN, I2C, UART,
GPSB) for their first instances.
• Coded a test case to verify the functionality of all the register
bits of “IO_SS_CFG” block.
• Coded test cases for interrupt generation of CAN, ADC, I2C,
UART, GPSB and verified point-to-point connectivity.
• Coded testcases for GPSB and ADC fault generation and
verified point-to-point Connectivity
• Coded testcases for verifying the data path of ADC, CAN
and I2C .
• Porting and implementing the IO Subsystem testcases in the
Chip Top level to verify Top-level pins of I2C, UART,
CAN, GPSB, ADC.
• debugging the RTL issue, in case of test failure.
• Completing the Code Coverage of IO Subsystem.
• Creating the Testbench for Pre-Layout GLS of HSIO and
Chip Top.
Tools & Language used: Synopsys VCS, Verdi, C, C++, Verilog, System Verilog
Operating Sysytem Linux
Project 2: BRECK FCV
Location: Capgemini, Hyderabad
Client: AMD
Duration : 08/2024 -- present
Role/Title: Verification of Top level
Responsibilities
Contribution: • My primary responsibility involved AXI VIP integration at
the SOC level.
• Coded CDO(configuration data objects) based test cases at
the SOC level.
Synopsys VCS, Verdi, C, System Verilog, UVM
Tools & Language used:
Linux
Operating Sysytem:
INTERNSHIP :
DV Trainee
Sumedha IT
09/2021 – 02/2022, HYDERABAD.
Tools: Synopsys VCS tool
PROJECT 1:
AHB2APB Bridge IP Core Verification using UVM
Description: The AHB to APB bridge is an AHB slave that works as an interface between the high-
speed AHB and the low-performance APB buses.
PROJECT 2:
Design and verification of 8-bit Address Decoder
Description: The address Decoder design receives a packet as an input which has the address of 8-
bit. So if the given packet has a valid address then its corresponding output will toggle 3 times and
if the decoder receives a packet with an invalid address then the output pin error_address pin will
be asserted.
PROJECT 3:
FIFO design using SystemVerilog verification
Personal Information
DOB: 29 Aug 1999 Marital Status: Unmarried Citizenship: Indian
Declaration
I hereby declare that the above-mentioned information is correct to the best of my knowledge and
Belief.
A.Saritha.
