Breakdown voltage capability of vertical 4H–SiC power

devices
Philippe Godignon, Jérôme Biscarrat, Miya Tranchesset, Romain Lavieville,
Pierre Brosselard, Josep Montserrat

To cite this version:

Philippe Godignon, Jérôme Biscarrat, Miya Tranchesset, Romain Lavieville, Pierre Brosselard, et al..
Breakdown voltage capability of vertical 4H–SiC power devices. Materials Science in Semiconductor
Processing, 2024, 178, pp.108347. �10.1016/j.mssp.2024.108347�. �cea-04742479�

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 Materials Science in Semiconductor Processing 178 (2024) 108347

Contents lists available at ScienceDirect

Materials Science in Semiconductor Processing

journal homepage: www.elsevier.com/locate/mssp

Breakdown voltage capability of vertical 4H–SiC power devices

Philippe Godignon a, *, Jérôme Biscarrat a, Miya Tranchesset a, Romain Lavieville a,
Dominique Tournier b, Pierre Brosselard b, Josep Montserrat c
a
Université Grenoble Alpes, CEA LETI, Grenoble, France
b
Univ Lyon, INSA Lyon, Univ. Claude Bernard Lyon 1, Ecole Centrale Lyon, CNRS, Ampère, F-69621, France
c
IMB-CNM-CSIC, Campus UAB, 08193 Bellaterra, Barcelona, Spain

A R T I C L E I N F O A B S T R A C T

Keywords: Power semiconductor devices are constructed to endure high voltages (>30 V) and manage high current density.
Silicon carbide Edge termination is a specific feature that must be integrated into the device architecture to achieve high voltage
Power devices capability in vertical power components. It is necessary to design these edge terminations while taking into
Edge termination
account the device’s architecture and technology. Termination efficiency is the main factor, but its area is also of
JTE
great significance. Many edge termination designs with efficiency close to 100 % have been reported and are
Avalanche capability
UIS currently used in commercial devices. However, having a near-100 % static breakdown voltage is not the only
requirement in modern power devices. Today, most power applications rely on the avalanche capability as a key
parameter. Avalanche capability is defined by the device ability to enter in non-destructive avalanche mode,
where the component can temporarily sustain a high voltage and a high current in blocking mode. The
Unclamped Inductive Switching (UIS) test can be used to measure the avalanche mode, and it can be customized
to define a safe operating area for a full avalanche mode (SOA). The safe operation of both single pulse and
repetitive pulsed avalanche limits can be characterized. Such operation mode is now controlled in both Silicon
and Silicon Carbide based power devices. However, the development of novel wide and ultra-wide band gap
semiconductors in regards to avalanche capability and SOA still require a lot of work.

1. Introduction current flow [2]. A schematic illustration of these architectures is rep­

resented in Fig. 1. In lateral devices, the current flows laterally between
Electrification is one of the most important strategies for driving the two electrodes located on the surface of the semiconductor, like many
transition from fossil fuel to renewable energy. Power electronics form a other semiconductor devices such as CMOS circuits. The vertical ar­
crucial part of this transition [1]. In fact, power devices [2] are chitecture results in current flowing from the top to the bottom of the
semiconductor-based architectures able to manage high voltage and/or semiconductor die, between two electrodes on either side. In both ar­
high current for conditioning electrical energy. They are used in almost chitecture configurations, the component’s maximum voltage capability
all the electronic systems and applications, usually to control the energy requires the addition of specific features to the device structure. In a
supply to the electronic systems or to electrical loads (motors, actuators vertical device, this feature is called edge termination and is located at
…). Power electronics use these devices in different family of circuits the periphery (see Fig. 2.) of the active area driving the current [4].
such as rectifiers, converters or breakers. Typically, the semiconductor Power devices are often qualified using their on-resistance (Ron) and
power devices can suffer from electrical parasitic’s such as overvoltage breakdown voltage (BV). In the scientific literature, breakdown voltage
or surge energy generated by the load or the power circuit. Conse­ is often identified by a sharp increase of the reverse current in the I–V
quently, the design of such components must be robust and take into curve, which, in some cases, may result in misleading results analysis.
account safety margins defined in the so-called Safe Operating Areas The two main ways to define the BV parameter in current commercial
(SOA) [2,3]. device data sheets are: 1) reaching the avalanche mode breakdown
Two primary architectures are used for power semiconductor de­ voltage, 2) reaching a given leakage current density level, typically 1
vices: lateral and vertical, depending on the direction of dominant mA/cm2. Nonetheless, as we will discuss in this paper, power system

* Corresponding author.
E-mail address: [email protected] (P. Godignon).

https://doi.org/10.1016/j.mssp.2024.108347
Received 17 November 2023; Received in revised form 14 March 2024; Accepted 15 March 2024
Available online 18 April 2024
1369-8001/© 2024 The Authors. Published by Elsevier Ltd. This is an open access article under the CC BY license (http://creativecommons.org/licenses/by/4.0/).
P. Godignon et al. Materials Science in Semiconductor Processing 178 (2024) 108347

developers prefer power components showing an avalanche breakdown Silicon, both electrons and holes impact ionization coefficients decrease
capability. with temperature, resulting in an increase of the avalanche voltage
Today’s power semiconductor devices are mostly Silicon based but when temperature increases. In SiC, impact ionization rates are lower
Silicon Carbide (SiC) emerged as the most viable candidate material for than in Si. Niwa [10] reported that the hole impact ionization coefficient
next-generation efficient solutions, notably thanks to its wider bandgap for 4H–SiC decreases at higher temperatures while the electron impact
and critical electric field and good thermal conductivity [5]. As their Si ionization increases slightly. Even though electrons in 4H–SiC have a
counterparts, SiC vertical power devices need a properly designed edge positive temperature coefficient, properly designed devices still see an
termination. However, the high voltage edge termination design and increase in avalanche voltage as temperature increases, provided that
optimization of SiC devices is partially different from Si ones due to carrier removal is effective enough. Ideally, avalanche should take place
several specificities [5]. The higher critical electric field in SiC compared in a plane parallel pn junction to favor generated carriers extraction.
to Si makes the management of the electric field distribution different, As SiC doping decreases, the critical electric field that activates
particularly at the interfaces with dielectrics. The use of field plates for avalanche phenomena decreases [11,12]. This could be seen as a
edge termination is limited by this [6]. In terms of technology, SiC has drawback for high voltage devices where low doped thick epilayers are
significantly lower dopant diffusion coefficients than Si. Producing deep used, and lower critical field means lower avalanche voltage. However,
and laterally graded junctions [7], which are useful for building efficient it is equally important to consider that the device’s interface dielectrics
terminations in Si, is not as straightforward to do in SiC. Beside, deep SiC and passivation layers will be submitted to lower electric field stress, and
etching is slower than Si, which limits trench-based termination. The may consequently be more reliable on the long term. Table II lists the
charge trapping at the SiC/SiO2 interface is much higher, which neces­ drift layer parameters (epi doping and thickness) for the primary power
sitates special care in the termination design to prevent surface charges application voltage classes, as well as the critical electrical field
from affecting it. Consequently, the design of high voltage terminations extracted from Ref. [11].
in SiC becomes more complex due to these aspects. The higher doping level of SiC epilayer of SiC devices compared to Si
The present trends in periphery protection for high voltage vertical at same voltage range makes SiC more robust to specific degradation
4H–SiC devices are discussed in this paper. After some general consid­ mechanisms such as dynamic avalanche, second breakdown, and cosmic
erations about 4H–SiC parameters related to breakdown phenomenon, rays impact.
we will have a look to the currently used solutions and to the recently
proposed improvements, especially regarding the reduction of the edge 3. High efficiency edge terminations
termination area consumption. Then, we will look at a crucial require­
ment in high-power systems applications, which is the power device’s The purpose of edge terminations is to maximize the static break­
ability to withstand an avalanche. down voltage and, if possible, to facilitate a non-destructive avalanche
phenomenon in the power device [13]. The key parameter of an edge
2. Voltage breakdown in 4H–SiC devices termination is its efficiency, which is the ratio between the termination
breakdown voltage versus the maximum breakdown voltage of a 1D
Power semiconductor devices have the ability to block high voltage plane parallel junction made on the same drift layer configuration
to protect the load from its power supply. High voltage vertical archi­ (epilayer doping and thickness). The latter is the maximum voltage we
tecture requires a critical active layer called the drift region to allow for can applied between the top and bottom electrodes before activating an
the spread of equipotential lines when the structure is in blocking mode. avalanche phenomena in the semiconductor at the pn junction level.
In the semiconductor device, the applied voltage can be increased for a Therefore, designers aim to construct edge terminations with the utmost
given drift layer until it reaches a maximum value, which is known as efficiency, as close as possible to 100 %.
the breakdown voltage. Table I provides a list of possible breakdown The edge termination of most recent vertical power devices in Si or
modes, with some of them being destructive and others being reversible SiC is achieved by using selective P doped wells obtained through ion
[8] (see Table 2). implantation. Usually, these edge terminations are built either with P
Avalanche is usually the preferred breakdown type in blocking mode rings with high doping (>1E19 cm− 3) or/and with Junction Termina­
since it is usually reversible and non-destructive below a given thermally tion Extension (JTE) with moderate doping (few 1e17 cm− 3) [14–17].
dissipated energy limit, which depends on the device design [8,9]. There are numerous and diverse combinations of both structures that
Avalanche mode occurs when there is an impact ionization and multi­ have been reported and are currently employed in commercial SiC di­
plication phenomena caused by a high electric field inside the semi­ odes and transistors. Fig. 1 displays a non-complete list of suggested
conductor, which results in the generation of carriers. Under high architectures [14–32]. Pure P+ rings edge termination (Fig. 3a) is ad­
electric fields, charge carriers that are accelerated transfer energy vantageous because nearly all power devices have implanted P+ profiles
through impact ionization, creating more electron-hole pairs that lead to in their active cell process flow. This simplifies the fabrication process
the multiplication of charges, which results in a rapid increase in cur­ and reduces costs by eliminating the need for extra photolithography or
rent. The avalanche phenomenon and its associated multiplicative factor p-type implantation steps to implement the termination. However, this
are influenced by the electrons and holes impact ionization coefficients ring termination requires meticulous control of the photolithography
[2,9]. The electric field is the primary factor that influences these co­ dimensions, particularly regarding the first ring position, and typically
efficients. As the electric field increases, the coefficients increase. In takes up a large area (>20 rings). The JTE structure (Fig. 3b)

Fig. 1. Power MOSFET lateral (left) and vertical (right) architecture schematic.

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P. Godignon et al. Materials Science in Semiconductor Processing 178 (2024) 108347

necessitates an additional mask level and implantation step, but when Table 1
combined with internal or external rings, it leads to optimal efficiency Typical breakdown phenomena observed in power semiconductor devices [8].
and a shorter termination length. In power MOSFETs, a deep P-body is Breakdown Breakdown Specificities
implanted to form the channel area. One may consider to use this phenomena type
implant to form an edge termination. However, up to now, tentative to Avalanche in a pn reversible Limited by maximum critical avalanche
use this P-body layer as JTE failed [26] due to a higher p-doping than the junction energy
optimal one. Therefore, it is necessary to perform a specific Al implan­ Avalanche reversible Limited by (minority) carriers extraction
tation step or multiple mask levels etching of the P-body (Fig. 3i) as elsewhere efficiency
Punch-through reversible Limited by carriers extraction efficiency
required. A gradual lateral doping along the x-axis is highly beneficial and dissipated power. Depends on doping
for efficient termination in the JTE design. In silicon, it can be done by and junctions barrier potentials
opening variable width implantation windows and playing with the Parasitic BJT turn- destructive Depends on junctions built-in potential
lateral diffusion of the dopants during thermal treatment [6,33]. In SiC, on (latch-up) (related to the band gap of the
semiconductor)
dopants do not diffuse at reasonable temperatures (<1800 ◦ C). An
Carriers trapping reversible Depends on traps density and detrapping
alternative technique to obtain lateral doping variation of the JTE is to rate of deep traps levels
combine the single implantation step with multiple etching steps as Percolation Time Depends on switching frequency
proposed in Ref. [28] and shown in Fig. 3f. breakdown dependent
It is now possible to design edge terminations with maximum effi­
ciency and safety using 4H–SiC using TCAD modeling and standard
efficiency. In a current 10 kV device, the edge termination takes up
processing tools. Besides the correct design of the JTE and rings geom­
roughly 45 % of the die area. If there was no termination required, the
etry, there are other factors that need to be considered. The first one is
die could have twice the current capability value. Fortunately, for a 1.2
the high density of interface traps typically obtain on a SiC/SiO2 inter­
kV component, a total edge termination length of 50 μm–100 μm has
face. The breakdown voltage can fluctuate depending on these charges.
shown to be sufficient.
Interface charges may help increase the apparent static breakdown
In the edge termination structures listed above (Fig. 3), some of them
voltage, but they can also cause voltage instability during switching,
can help to reduce the total die area. For instance, the termination of
which could result in a potential change in the dynamic avalanche
Fig. 3e [27] is claimed to reduce the termination length by 30 %
voltage. All Fig. 3’s edge terminations are sensitive to surface charges
compared to the termination of Fig. 3d. Regardless, it is important to
with a more or less degree of sensibility. The efficiency of single JTE
consider other relevant parameters when reducing the termination
relies on whether or not there are positive or negative charges in the
width. A critical parameter is the presence and position of the channel
dielectric, while JTE with inner and outer guard rings only exhibit
stopper. This feature can be found at the ends of the die (as depicted in
degradation when positive charges are present. On the contrary, guard
Fig. 5a). It consists of a highly doped thin ring with the same doping type
rings are more sensitive to negative charges. This behavior is illustrated
as the drift region. A floating metal layer can be also deposited on top of
in Fig. 4 for 3.3 kV PiN diodes. Two edge terminations (b and d in Fig. 3)
the ring. As a result, the channel stopper is self-biased at the same
have been modelled with Sentaurus TCAD tool, calculating the break­
voltage as the electrode on the backside (drain, cathode, collector). It
down voltage versus the p-doping of the JTE for different dielectric
helps to have a uniform distribution of the electric field at the die top
interface charge concentrations. The experimental results are also
surface, prevents from a parasitic inversion channel and acts as a
mentioned. For both termination types, experiment fits only with a zero
parasitic charge collector eventually generated at the SiC/dielectric
or a negative charge at the interface, which corresponds to the best
interface. However, to prevent surface arcing (Fig. 5b), it is necessary to
combination for this termination type. According to theory, the termi­
maintain a specific distance between the end of the active area metal
nation shown in Fig. 3d is the most effective for high voltage power
(anode, source, emitter) and the channel stopper. Excessive contraction
devices (>1200 V), but it is quite area-consuming.
of the termination length can lead to instabilities in the dielectric
strength caused by charges or humidity effects in the passivation top
4. Optimization of edge termination area
layer.
The edge terminations depicted in Fig. 3 are the most frequently
Edge terminations with near 100 % efficiency are now regularly
employed in modern commercial devices, and they can either be planar
obtained. The current optimization step involves reducing the termi­
or combined with a MESA etch. In this sense, the management of the
nation area. Edge termination does not contribute to device current
electric field in the periphery is done laterally along the axe parallel to
conduction, but it may take up a significant amount of semiconductor
the surface. Reducing the edge termination area can be achieved by
die space. Since the development trend is to increase the device current
using the vertical axis to partially or fully withstand the electric field in
capability versus the semiconductor area, or equivalently to reduce the
the periphery. This approach allows for significantly reducing the size of
specific on-resistance per die, the termination area dead zone (in terms
the edge termination. It is possible to utilize buried rings as described in
of current capability) plays a major role in the SiC die output current
Ref. [34] or deep implantation for JTE rings [35], but the

Fig. 2. Schematic of a high voltage termination concept in a vertical power diode architecture.

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P. Godignon et al. Materials Science in Semiconductor Processing 178 (2024) 108347

Table 2
Drift region’s parameters used for standard power application voltage classes and corresponding critical electric field value.
Voltage class 650V 1.2 kV 1.7 kV 2.3 kV 3.3 kV 6.5 kV 10 KV 15 kV

Epilayer thickness doping 5 μm 2 × 9 μm 1 × 14 μm 6 × 18 μm 5 × 30 μm 3 × 55 μm 1 × 90 μm 7 × 130 μm 4 ×

(cm¡3) 1016 1016 1015 1015 1015 1015 1014 1014
Critical electric field (MV/cm) 2.71 2.5 2.44 2.33 2.21 2 1.94 1.85

Fig. 3. Schematics and corresponding literature references of the main planar edge terminations used in SiC power devices.

implementation is quite complex with SiC technology. Most approaches environmental pollution issue has to motivate the studies of eco-friendly
involve etching a trench over the entire thickness of the drift layer and SiC dry etching processes using low GWP etch chemistry or, at least, to
filling it with a dielectric like SiO2, polyimide or BCB [36–39]. However, limit the use of deep trench-based termination. On the other hand,
since a high electric field is usually present at the end of the active area sidewall implantation (Fig. 6b) is performed using a high ion beam angle
p/n junction on the trench top side, additional features are required to and several steps are required to implant the different orientations of the
properly block the high voltage. By using a field plate with an optimized trench sidewall, making the process costly and time consuming.
shape [40,41], the equipotential crowding can be reduced (Fig. 6a). Therefore, it may be possible to incorporate a partial trench etching
Another efficient approach is to implant a p-type layer on the trench at a technologically realistic depth with P+ rings implanted at the bot­
sidewalls, as proposed in Refs. [42,43] (Fig. 6b). By utilizing this 3D tom of the trench, as described in Refs. [45,46]. In this case, the trench
termination configuration, the electric field at the SiC top surface can be does not need to reach the N+ buffer below the drift region. By utilizing
reduced, which prevents issues with top side passivation arcing under conventional ion implant and SiC etching processes, devices with higher
humidity effect. However, these termination architectures are limited by voltage ranges can be made.
several process limitations. Among them, SiC dry etching is much slower
than Si technology, and it generates a high number of surface defects and 5. Avalanche mode
roughness, both on the trench bottom and sidewalls. In SiC, trenches
that are deeper than 10 μm pose a challenge. As a result, these trench To take full advantage of SiC’s superior electro-thermal properties,
edge terminations are challenging to use for voltage ranges greater than most SiC power devices are with a vertically based architecture (JBS and
1.2 kV. Furthermore, the standard conventional SiC dry-etching process PiN, MOSFETs, JFETs). A power device that qualifies for a breakdown
utilizes fluorine-based chemistry, particularly the use of sulfur hexa­ voltage class (650 V, 1200 V, 1700 V, etc.) has an actual breakdown
fluoride (SF6). According to studies, this gas has a high global warming voltage higher than that voltage class value. If the device breaks down in
potential (GWP) of around 23,500 kg of CO2 equivalent per kg over a a destructive manner, a significant derating margin must be imple­
100-year time horizon [44]. The increasing attention to the mented, such as 50 % for 650 V GaN HEMT. Independently of the

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P. Godignon et al. Materials Science in Semiconductor Processing 178 (2024) 108347

Fig. 3. (continued).

Fig. 4. Simulation and experimental measurement of PiN diodes with (a) a single JTE and (b) a hybrid ring assisted JTE (d) in Fig. 1) edge termination. 4 interface
charges density have been used (− 2e12, -1e12, 0 and +1e12 cm− 2).

derating, the power device operation will be safer if it is capable to enter edge termination or active area. When the avalanche mode is reached,
in a non-destructive and repetitive avalanche breakdown mode, and to the voltage at the device electrodes is clamped and does not increase
sustain this avalanche state during a given time duration or number of anymore (at low power). The device will then take care of dissipating the
cycles. Avalanche robustness is highly desired for power devices in surge energy generated by the power circuit. Depending on the device
power electronics applications to protect against overvoltage and surge design, a given maximum energy rate will be dissipated before the de­
energy. By clamping the voltage peak, devices can conduct high vice enters in thermal breakdown.
avalanche current, which dissipates the excessive energy generated in Measurement of avalanche behavior directly on-wafer would be a
the circuit. better method to receive faster feedback on a device’s design and
The breakdown of power PiN diodes and MOSFET transistors occurs technology regarding its avalanche capability. By doing so, the die’s real
due to an avalanche process that takes place in the p/n junctions of the behavior can be studied without the packaging effect, which may affect

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P. Godignon et al. Materials Science in Semiconductor Processing 178 (2024) 108347

Fig. 5. (a) Schematic representation of the device edge termination and its channel stopper, (b) top image of a power diode suffering from a surface electrical arcing
between the main electrode and the channel stopper.

Fig. 6. (a) Trench termination with optimized with field plate (from Ref. [42]) (b) Trench termination with lateral side implantation.

its avalanche performance. For this purpose, we intended to measure the

avalanche behavior using static I–V measurement, as well as with re­
petitive avalanche mode biasing limiting the dissipated power and
temperature raise.

5.1. Static avalanche mode

In static on-wafer I–V measurements of PiN diodes and MOSFETs, the

breakdown mode can be detected by a sudden change in the leakage
current slope under high voltage biasing. According to Table I, some
breakdown modes are destructive. In this case, when performing I–V
measurements again, the I–V curves behave completely differently,
usually with a much higher leakage current starting at a low bias voltage
(short-circuit mode breakdown). However, other breakdown modes
than avalanche are reversible (such as junction punch-through). To
segregate avalanche mode from other non-destructive breakdown, on-
wafer temperature dependent I–V measurements can be used. As
stated above, increasing the operation temperature should result in a
slight increase in the measured avalanche voltage. Due to the temper­
ature’s behavior of the impact ionization coefficient in SiC mentioned Fig. 7. Reverse i-V characteristics of SiC PiN and Schottky diodes measured at
earlier, the increase of the avalanche voltage with temperature is rela­ different measurement temperatures. Schottky diodes exhibit soft breakdown
tively low, around 0.38 V/K in our 1.2 kV diodes case. Power semi­ while PiN enter in avalanche mode.
conductors like PiN and MOSFETs tend to exhibit this behavior easily,
but it still depends on the edge termination efficiency. heating and prevent from thermal breakdown. In this way, the
However, other devices such as Schottky power diodes and JBS di­ avalanche mode is kept repetitive for a long time. By using a repetitive
odes may have a different I–V characteristic behavior [2,5]. In these avalanche mode biasing with limited power dissipation, it is possible to
components, a high leakage tunneling current due to thermionic field investigate secondary effects that affect the device’s long-term reli­
emission (TFE) conduction related to the Schottky contact is appearing ability. For example, there may be drifts caused by hot carrier injection
in the I–V measurement (see Fig. 7). The presence of high leakage cur­ and charge trapping.
rents may mask the activation of the avalanche mode or reach the The results presented in Fig. 7 corresponds to 2 wafers with 1.2 kV
measurement system (SMU) current limits before the avalanche is Schottky and JBS diodes processed at CNM-CSIC Barcelona. Both wafers
reached. had a drift region of 12 μm and 7e15 cm− 3 doped. The Schottky metal,
Besides, in the event of an avalanche, we can limit the current Ti, and W, and P+ doping profile were the primary elements that
flowing in the device by setting a current compliance to control its self-

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P. Godignon et al. Materials Science in Semiconductor Processing 178 (2024) 108347

differentiated these two wafer processes. The extracted barrier height Table 3
was 1.04eV and 1.14eV for Ti and W, respectively. Different active area Main termination designs tested up to avalanche mode in wafer with W as
parameters and edge terminations were designed on the same wafer. We Schottky metal.
also implemented PiN bipolar diodes using the JBS P+ implantation JTE Internal Internal Distance Total Breakdown
profile for the anode formation. length rings rings to channel termination voltage (V)
The distance between JBS P+wells is one of the designed parameters (μm) number distances stopper length(μm)
and width (μm) (μm)
that was analyzed (see Fig. 8a). This parameter has a significant impact
(μm)
on the leakage current value at which avalanche mode is activated. We
35 2 rings/3 4.5/5 60 95 2050
can see in Fig. 8b that the avalanche voltage is the same for three of the
μm
Wp/Wn designs (Schottky ratios of 0,63, 1, and 1.33) and for the 50 3 rings/3 4.5/5/5.5 60 110 2080
reference PiN, despite the avalanche mode appears at different reverse μm
current levels. Both PiN and JBS experience a small increase in their BV 75 3 rings/3 4.5/5/5.5 60 135 2075
when temperature rises. μm
100 3 rings/3 4.5/5/5.5 60 160 2080
The next step was to compare the impact of the termination design μm
on the avalanche voltage. For this purpose, we selected the design with a 150 3 rings/3 4.5/5/5.5 120 270 2070
Schottky ratio of 1 (Wp 2μm/Wn 2 μm) for the wafer with W as Schottky μm
metal. These devices allow us to observe the repeated avalanche mode 150 0 0 120 270 2065
mentioned earlier. Table III summarizes the design parameters for ter­
minations. The total termination length up to the channel stopper is also
overvoltage event characteristics, the avalanche mode activates and
given. All devices show a similar avalanche voltage around BV = 2080V,
induces high energy and current flow inside the device, which can lead
corresponding to the PiN diode one. It seems to confirm that the impact
to its thermal runaway. Internal and package thermal limitations
ionization and avalanche take place in the active area of the JBS for this
determine the device’s ability to sustain a maximum current and voltage
particular design. We can see that a termination with a JTE of 35 μm
combination for a certain duration. The single pulse avalanche energy
length is sufficient to support the 2050V avalanche voltage.
parameter has been established to quantify the component electro-
We are unable to determine if the avalanche occurred in the active
thermal limits during avalanche mode [47]. A dynamic characteriza­
area or the edge termination area based solely on these electrical mea­
tion method has been developed in Si technology to evaluate the single
surements. Fig. 9a displays a diagram of the different locations (A, B, C)
pulse avalanche capability limit and related avalanche energy parame­
where avalanche phenomena can occur. The JBS with a 0.63 Schottky/
ters of power devices. This methodology, named Unclamped Inductive
PiN ratio was pushed to destruction through an increase in power during
Switching (UIS) [48,49], has been adapted to 4H–SiC power diodes and
avalanche mode. The active area (location A in Fig. 9a) at the center of
transistors and is now regularly reported for new SiC device generations.
the diode is where destruction occurs, as shown in Fig. 9b. The thermal
The procedure for measuring UIS involves releasing energy that was
breakdown is likely caused by a heat transfer from the SiC near surface
previously stored in an inductor in the device under test (DUT). The
area to the top metal layers (W and Al). An excessive temperature is
electrodes of the device under test (DUT) experience an overvoltage due
produced that is higher than the metals’ fusion point. The location of the
to the energy stored in the inductance. An example of an electrical cir­
avalanche process can be determined after using TCAD modeling or
cuit we use for UIS testing on a diode (D1) is shown in Fig. 10. Linear
failure morphological analysis.
charging of the inductance occurs during the conduction phase of
transistor M1 (phase 1) in Fig. 10. When M1 is turn-off, an overvoltage
5.2. Dynamic breakdown voltage and maximum avalanche energy appear at the M1 and DUT electrodes while the current start to decrease
(phase (2) in Fig. 10). Note that a similar circuit configuration would be
The previous static avalanche evaluation method is not completely used to test the UIS capability of the transistor M1, removing the diode
trustworthy to determine the avalanche behavior in a real application D1.
when the device is operating in hard-switching mode. Parasitic imped­ The UIS test can be utilized for three different purposes. The primary
ances of the power circuit and inductive loads can initiate single pulse objective is to determine the device’s maximum avalanche energy, as
avalanche mode in a power device. Depending on the power circuit and

Fig. 8. JBS with different designs breakdown measurements (a) JBS cell schematic (b) I–V reverse measurement (voltage applied on the cathode).

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P. Godignon et al. Materials Science in Semiconductor Processing 178 (2024) 108347

Fig. 9. a) Schematic representation of possible breakdown location in a JBS diode, b) pictures of two diodes after destructive thermal breakdown on different
locations: b) active area (location A) and c) die edge surface (location D).

Fig. 10. Example of Unclamped Inductive Switching (UIS) test circuit and corresponding voltage versus time signals.

done for Silicon. In this case, we need to reach the thermal breakdown of MOSFETs in dc–dc boost and flyback converters are often subjected to
the device. The second use is to measure the avalanche voltage of de­ repetitive avalanche shocks, which easily result in electrical degradation
vices exhibiting high leakage current levels in soft breakdown mode, and parameter drift. Then, such repetitive pulses measurement is also
such as Schottky and JBS diodes or similar devices. For this purpose, we relevant to fully characterize the MOSFET behavior.
will limit the discharged energy (or current peak) playing with the Fig. 11 displays UIS measurement waveforms for Caly Technologies’
inductance value and the gate pulse duration. By limiting the current 1.2 kV JBS diodes. In these reported measurements, different charging
level during avalanche operation, we can prevent excessive self-heating pulse durations (Tp) were employed to store energy in inductor L1. In
and thermal runaway to maintain a safe avalanche mode. A third use of Fig. 11a, we measured the voltage at the JBS electrodes when the control
the circuit is to test the repetitive avalanche mode capability, keeping switch M1 was turned off. We can infer a sharp increase of the voltage
the current peak below the thermal destruction value [50,51]. SiC VKA up to a plateau corresponding to the avalanche voltage of the JBS

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P. Godignon et al. Materials Science in Semiconductor Processing 178 (2024) 108347

Fig. 11. (a) Voltage peak versus inductance charging pulse length (b) Current peak in the Device Under Test during the avalanche mode for different charging
pulse length.

Fig. 12. Evolution of the a) avalanche energy capability b) avalanche current, versus the nominal current (meaning the die area) of several commercial SiC
power diodes.

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P. Godignon et al. Materials Science in Semiconductor Processing 178 (2024) 108347

diode. The plateau appears at 1670 V, which corresponds to the lower voltage bias than static avalanche mode. However, due to the
avalanche breakdown voltage at a junction temperature near room higher doping, lower carrier’s lifetimes and lower impact ionization
temperature operation. When the inductor charging pulse Tp is elevated, rates, it is considered that dynamic avalanche can hardly be seen for SiC
the current flowing through the diode in avalanche mode rises device ranges below 10 kV [56].
(explained in Fig. 11b). After a charging pulse duration Tp = 800 μs, the
corresponding energy released is enough to cause a thermal breakdown 6. Impact of cosmic rays
on our DUT. This destructive breakdown occurs after 5.2 μs in avalanche
mode. Failure is in short circuit. The maximum avalanche energy of a Cosmic rays are high radiation energy particles that can lead to
single pulse can be calculated using the voltage and current curves ob­ spontaneous failures in semiconductor devices biased in blocking mode
tained at Tp = 750 μs previously. For this purpose we used the meth­ or under high electric field. The impact of cosmic rays on power semi­
odology and equations reported in Ref. [52]. The extraction process conductor component for terrestrial applications have been shown first
resulted in a total energy of 180 mJ and an avalanche energy density of for Silicon devices [57]. The underlying mechanism for failure of power
6.16 J/cm2. device have been identified as massive charge multiplication triggered
In Fig. 11a, we can observe that in the avalanche mode, the voltage is by a nucleon-nucleus collision that creates an energetic recoil. Similarly
not fully clamped and slightly increases due to device internal self- to Si, in high electric field regions of SiC devices, the strong avalanche
heating. As the junction temperature increases, the avalanche voltage charge carrier multiplication is sufficient for causing single event
increases accordingly, resulting in the convex shape of the voltage curve. burnout [58]. In terrestrial applications, these particles are typically
The avalanche voltage is also affected by the length of the pulse. Oc­ neutrons and their flux exponentially increase with the altitude. In Si,
casionally, we can observe a discrepancy between the static avalanche mitigation is done through specific design allowing a reduction of the
voltage measured on-wafer and the dynamic avalanche voltage electric field peaks at the p/n junctions, or using a voltage range
measured with UIS, even when limiting the device self-heating. derating. In SiC, involved electric fields are usually 10 times higher.
Fig. 11b indicates that the avalanche current is 22 A while the However, this is mitigated by a thinner drift layer and a smaller die area
nominal current of the diode is 10 A. The value of this avalanche current for a given voltage capability and nominal current. It helps to reduce the
is dependent on the inductance value selected for the test. Changing the probability of a collision with a particle. Indeed, experimental results
inductance values can result in the generation of a complete safe oper­ show a higher robustness of SiC devices versus their Si counterparts [59,
ating area (SOA), as illustrated in Ref. [52]. For each inductance value, 60].
the supply voltage is increased up to the device thermal runaway. The Up to now, the impact of the termination design on device rugged­
corresponding avalanche current and energy can then be determined. It ness regarding Cosmic Rays has not been established. Again, the thinner
is possible to obtain inductance values that lead to a higher maximum and shorter SiC termination dimensions should favor a lower probability
avalanche current than the nominal DC current of the device. The ratio is of collision in the critical high field area. However, devices with similar
greatly influenced by the diode design (planar, trench, critical di­ electric field typically show similar failure rates. For a given technology
mensions), technology (Schottky metal), and the manufacturer’s defi­ or application, it is usually not possible to provide a single number of
nition of its device’s nominal current. In Fig. 12, we have drawn the cosmic radiation failure rate. The higher the device voltage rating, the
distribution of the avalanche energy and maximum avalanche current more susceptible it is to cosmic ray induced failures. Then, manufac­
versus nominal current for several commercial SiC diodes with different turers will recommend a voltage derating which will depends on the
voltage ranges. For a given device technology, avalanche energy in­ breakdown voltage range and mission profile [61].
creases almost linearly with the current, which is related to the die area.
Regarding current ratio, it is highly dependent on the technology and 7. Conclusions
the measurement parameters used (inductance value, charging time,
etc.). Solid-state SiC power devices with breakdown voltages of up to 15
With the introduction of SiC and other WBG devices in real power kV can be regularly demonstrated using the established design guide­
applications, and especially power systems with inductive loads (like lines and technology procedures for active and edge termination zones.
electric motors in electric vehicles), higher frequencies and high High breakdown effectiveness is the main reason for the widespread use
switching transitions (dV/dt) are used. Under these more rigorous of terminations that are based on guard rings or JTE with rings.
conditions, it is frequently observed that the device avalanche voltage Certainly, the majority of commercial SiC devices are designed to
during circuit operation is drifting. The BV drift may be greatly influ­ withstand avalanches. Single pulse avalanche current easily reaches the
enced by charge trapping near the avalanche location inside the semi­ nominal forward DC current ratings, while repetitive avalanche mode is
conductor. Another charge trapping effect could be caused by the also possible with very low performance’s drift. These avalanche modes
presence of deep-level point defects in the semiconductor [8,53]. capabilities are required in most modern power circuit applications
Adequate processing steps must be taken to minimize these deep levels, where inductive loads and parasitic interconnection inductances are
particularly during the ion implantation and activation steps of dopants. present. The measurement of avalanche capability directly on-wafer is
At device design level, we need to mitigate electric field peaks from not straightforward, as misunderstandings are possible when analyzing
charge trapping sensitive areas. a static I–V curve. Then, either temperature-dependent measurement on
Finally, the avalanche operation generates a bipolar conduction wafers or dynamic tests (UIS) on packaged devices are required. UIS test
mode, with the presence of the two types of carriers, electrons and holes. results may be influenced by the transient dV/dt rates applied to the
It is well known that bipolar current can cause stacking faults (SFs) to device under test. UIS test standards have been developed for Si devices,
propagate in SiC devices. The SFs impact the blocking characteristics with operation frequencies in the 10th of kHz range. However, new
and reverse leakage currents of power SiC devices, including Schottky power semiconductors such as SiC and GaN operate at higher fre­
and JBS diodes [54]. Then, it is possible that a repetitive avalanche quencies. Then, high frequency pulse tests may be necessary to emulate
mode in a unipolar device generates activation of stacking faults and the operating conditions of the novel power application.
corresponding electrical parameters degradation. This must also be GaN and novel UWBG materials (Ga2O3, Diamond) are particularly
taken into account in the final device’s ruggedness. affected by this. Although these materials have high BV, the absence of
On the other hand, Silicon bipolar devices also suffer from dynamic avalanche requires significant voltage degrading and prevents the de­
avalanche effect [55]. The avalanche mode occurs if the stored free vice from being applied in many inductive-load systems. Strong efforts
carriers do not recombined fast enough and lead to an increase of the done in GaN vertical devices start to give promising results. UWBG re­
electric field gradient in the structure, which may reach critical value at quires similar efforts to be performed. In addition to avalanche mode,

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P. Godignon et al. Materials Science in Semiconductor Processing 178 (2024) 108347

other capabilities like high peak surge current or short circuit capability [18] X. Deng, Y. Guo, T. Dai, C. Li, X. Chen, W. Chen, Y. Zhang, B. Zhang, A robust and
area-efficient guard ring edge termination technique for 4H-SiC power MOSFETs,
are also necessary in such new WGB devices to be competitive with Si
Mater. Sci. Semicond. Process. 68 (2017) 108–113.
and SiC. [19] X. Li, W. Yang, L. Li, X. Deng, B. Zhang, Three-section Adjusted field limited rings
applicable for SiC 2200V power MOSFETs, ECS Trans. 80 (7) (2017) 181–187.
[20] D.C. Sheridan, G. Niu, J.D. Cressler, Design of single and multiple zone junction
CRediT authorship contribution statement
termination extension structures for SiC power devices, Solid State Electron. 45 (9)
(Sep. 2001) 1659–1664.
Philippe Godignon: Writing - original draft, Validation, Conceptu­ [21] N. Niwa, J. Suda, T. Kimoto, 21.7 kV 4H-SiC PiN diode with a space-modulated
alization. Jérôme Biscarrat: Investigation, Formal analysis, Validation. junction termination extension,”, APEX 5 (6) (May 2012) 064001.
[22] R. Pérez, N. Mestres, S. Blanque, D. Tournier, X. Jordá, P. Godignon, R. Nipoti,
Miya Tranchesset: Investigation, Formal analysis, Data curation. A highly effective edge termination design for SiC planar high power devices,
Romain Lavieville: Supervision, Methodology, Conceptualization. Mater. Sci. 457–460 (2004) 1253–1257.
Dominique Tournier: Methodology, Formal analysis, Data curation, [23] K. Kinoshita, T. Hatakeyama, O. Takikawa, A. Yahata, T. Shinohe, Guard ring
assisted RESURF: a new termination structure providing stable and high
Conceptualization. Pierre Brosselard: Supervision, Conceptualization, breakdown voltage for SiC power devices, Proc. 14th Int. Symp. Power
Validation. Josep Montserrat: Investigation, Methodology, Data Semiconductor Devices Ics (ISPSD) (Jun. 2002) 253–256.
curation. [24] H. Niwa, G. Feng, J. Suda, T. Kimoto, Breakdown characteristics of 15-kV-Class 4H-
SiC PiN diodes with various junction termination structures, IEEE Trans. Electron.
Dev. 59 (10) (Oct. 2012) 2748–2752.
Declaration of competing interest [25] W. Sung, B.J. Baliga, A near ideal edge termination technique for 4500V 4H-SiC
devices: the hybrid junction termination extension, IEEE Electron. Device Lett. 37
(12) (December 2016).
The authors declare that they have no known competing financial [26] V. Soler, et al., Semicond. Sci. Technol. 32 (3) (2017) art nº035006.
interests or personal relationships that could have appeared to influence [27] A. Mihaila, et al., 28th Int. Symp. on Power Semiconductor Devices and ICs
the work reported in this paper. (ISPSD16), Prague, 2016, p. 223. June 12-16.
[28] T. Dai, L. Zhang, O. Vavasour, et al., 33th Int. Symp. On Power Semiconductor
Devices and ICs (ISPSD21), Nagoya (Japan), May , pp. 251–254.
Data availability [29] A. Mihaila, , et al.18th Int, Symp. on power semiconductor devices and ICs
(ISPSD06), Napoles (Italia) (2006) 161–164. June 5-9.
[30] C. Huang, H.C. Hsu, K.W. Chu, L.H. Lee, M.J. Tsai, K.Y. Lee, F. Zhao, Counter-
No data was used for the research described in the article. doped JTE, an edge termination for HV SiC devices with increased Tolerance to the
surface charge, IEEE Trans. Electron. Dev. 62 (2) (February 2015).
Acknowledgement [31] G. Pâques, Z. Scharnholz, N. Dheilly, D. Planson, R.W. De Doncker, High-voltage
4H-SiC thyristors with a graded etched junction termination extension, IEEE
Electron. Device Lett. 30 (10) (Oct. 2011) 1421–1423.
From CNM-CSIC side, this work has been partially supported by the [32] Q.J. Zhang, A. Agarwal, C. Capell, L. Cheng, M. O’Loughlin, A. Burk, J.W. Palmour,
research project OPTO-FET (PID2020-117201RB-C22) from the Spanish S. Rumyantsev, T. Saxena, M. Levinshtein, A. Ogunniyi, H. O′Brien, C.J. Scozzie, 12
kV, 1 cm2 SiC GTO thyristors with negative Bevel termination, Materials Science
Ministry of Science and Innovation, cofounded by FEDER. Forum Vols 717–720 (2012) 1151–1154.
[33] C. Ronsisvalle, V. Enea, Improvement of high-voltage junction termination
References extension (JTE) by an optimized profile of lateral doping (VLD), Microelectron.
Reliab. 50 (9–11) (Sep. 2010) 1773–1777.
[34] C.H. Cheng, C.F. Huang, K.Y. Lee, F. Zhao, A : Novel deep junction edge
[1] M. Rashid, Power electronics Handbook, in: Copyright ©, Elsevier, 2018.
termination for Superjunction MOSFETs, IEEE Electron. Device Lett. 39 (4) (April
[2] B. Baliga, Fundamentals of Power Semiconductor Devices, Springer, New York,
2018) 544–547.
USA, 2009.
[35] T. Masuda, T. Hatayama, S. Harada, Y. Saitou, Edge termination design with strong
[3] P. Wilson, The Circuit Designer’s Companion, fourth ed., Elsevier, July 2017.
process robustness for 1.2 kV-class 4H-SiC super junction V-groove MOSFETs, in:
[4] M.S. Adler, V.A.K. Temple, A.P. Ferro, R.C. Rustay, Theory and breakdown voltage
32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD),
for planar devices with a single field limiting ring, IEEE Transaction on Electron
Vienna, Austria, June 2020, pp. 166–169.
Devices 24 (2) (1977).
[36] M. Théolier M, H. Mahafoz-Kotb, K. Isoird, F. Morancho, S. Assié-Souleille,
[5] T. Kimoto, J.A. Cooper, Fundamentals of Silicon Carbide Technology: Growth,
N. Mauran, A new junction termination using a deep trench filled with
Characterization, Devices and Applications, John Wiley/Sons, Singapore, 2014,
BenzoCycloButene, IEEE Electron. Device Lett. 30 (6) (Jun. 2009) 687–689.
pp. 321–326, 423–432.
[37] K. Seto, R. Kamibaba, M. Tsukuda, I. Omura, Universal Trench edge termination
[6] M. Tarplee, V. Madangarli, Q. Zhang, Design rules for field plate edge termination
design, in: Proceedings of the 24th International Symposium on Power
in SiC Schottky diodes, IEEE Trans. Electron. Dev. 48 (12) (2002) 2659–2664.
Semiconductor Devices and ICs, Bruges, Belgium, 3-7 June 2012.
[7] R. Stengl, G. Ulrich, Variation of lateral doping—a new concept to avoid high
[38] T.H. Nguyen, M. Lazar, J.L. Augé, H. Morel, L.V. Phung, D. Planson, Vertical
voltage breakdown of planar junctions, International Electron Devices Meeting
termination filled with adequate dielectric for SiC devices in HVDC Applications,
(1985) 154–157.
Mater. Sci. Forum 858 (May 2016) 982–985.
[8] R. Zhang, Y. Zhang, Power device breakdown mechanism and characterization:
[39] H. Wang, J. Wang, L. Liu, N. Ren, J. Wu, C. Wang, S. Yang, K. Sheng, Design and
review and perspective, Jpn. J. Appl. Phys. 62 (2023) SC0806.
characterization of area-efficient Trench termination for 4H-SiC devices, IEEE
[9] M.E. Levinshtein, J. Kostamovaara, S. Vainshtein, Breakdown Phenomena in
Journal of Emerging and Selected Topics in Power Electronics 7 (3) (Sept. 2019)
Semiconductors and Semiconductor Devices, World Scientific Publishing, 2005.
1519–1526.
[10] H. Niwa, J. Suda, T. Kimoto, Impact ionization coefficients in 4H-SiC toward
[40] S. Hu, K. Sheng, A new edge termination technique for SiC power devices, Solid
Ultrahigh-voltage power devices, IEEE Trans. Electron. Dev. 62 (10) (2015).
State Electron. 48 (2004) 1861–1866.
[11] T. Kimoto, Updated trade-off relationship between specific on-resistance and
[41] W. Yang, H. Feng, X. Fang, Y. Onazawa, H. Tanaka, J. Sin, 28th Int. Symp. on Power
breakdown voltage in 4H-SiC{0001} unipolar devices, Jpn. J. Appl. Phys. 58
Semiconductor Devices and ICs (ISPSD2016), Prague, 2016, pp. 287–290. June 12-
(2019) 018002.
16.
[12] Kimoto T, Niwa H, Okuda T, Saito E, Zhao Y, Asada S, Suda J: Carrier lifetime and
[42] R. Kamibaba, K. Takahama, I. Omura, Design of Trench termination for high
breakdown phenomena in SiC power device material. J. Phys. Appl. Phys., 51 (36),
voltage devices, in: 22nd International Symposium on Power Semiconductor
363001..
Devices & IC’s (ISPSD 2010), Hiroshima, Japan, 2010, pp. 107–110. June 6-10.
[13] V.A.K. Temple, W. Tantraporn, Junction termination extension for near-ideal
[43] L. Liu, J. Wang, H. Wang, N. Ren, Q. Guo, K. Sheng, Sidewall-implanted Trench
breakdown voltage in pn junctions, IEEE Trans. Electron. Dev. 33 (10) (Oct 1986)
termination for 4H-SiC devices with high breakdown voltage and low leakage
1601–1608.
current, IEEE Electron. Device Lett. 43 (1) (January 2022).
[14] E. Stefanov, G. Charitat, L. Bailon, Design methodology and simulation tool for
[44] WMO Statement on the Status of the Global Climate in 2003, WMO-No. 966, WMO
floating ring termination technique, Solid State Electron. 42 (12) (1998)
publisher, Geneva, 2004.
2251–2257.
[45] Y.H. Kim, H.S. Lee, S.S. Kyung, Y.M. Kim, E.G. Kang, M.Y. Sung, A new edge
[15] D.C. Sheridan, G. Niu, J.N. Merret, J.D. Cressler, C. Ellis, C.C. Tin, Design and
termination technique to improve voltage blocking capability and reliability of
fabrication of planar guard ring termination for high-voltage SiC diodes, Solid State
field limiting ring for power devices, in: IEEE International Conference on
Electron. 44 (2000) 1367–1372.
Integrated Circuit Design and Technology and Tutorial, 2008, pp. 71–74.
[16] D.C. Sheridan, G. Niu, J.N. Merrett, J.D. Cressler, J.B. Dufrene, J.B. Casady,
[46] J. Jeong, J. Cha, G. Kim, S. Cho, H. Lee, Study of a SiC trench MOSFET edge-
I. Sankin, Comparison and optimization of edge termination techniques for SiC
termination structure with a bottom protection well for a high breakdown voltage,
power devices, in: Proceedings of the 13th International Symposium on Power
Appl. Sci. 10 (2020) 753.
Semiconductor Devices & ICs. ISPSD ’01 (Osaka), 2001, pp. 191–194.
[47] Application Note Toshiba Avalanche Energy (EAS) Calculation of Power MOSFET
[17] R. Pérez, D. Tournier, A. Pérez, P. Godignon, N. Mestres, J. Millán, Planar edge
©, Toshiba Electronic Devices & Storage Corporation, 2020-2021.
termination design and technology considerations for 1.7-kV 4H-SiC PiN diodes,
IEEE Trans. Electron. Dev. 52 (10) (October 2005) 2309.

11
P. Godignon et al. Materials Science in Semiconductor Processing 178 (2024) 108347

[48] JEDEC. STANDARD, Single pulse Unclamped inductive, Switching (UIS) Avalanche [55] J. Lutz, R. Baburske, Dynamic avalanche in bipolar power devices, Microelectron.
Test. Method. JESD24-5 (August 1990 (Reaffirmed: October 2002). Reliab. 52 (3) (2012) 475–481.
[49] Application Note RENESAS, Unclamped Inductive Switching (UIS) Test and Rating [56] J. Lutz, R. Baburske, Some aspects on ruggedness of SiC power devices,
Methodology, AN1968, Rev 0.00 (Nov 9, 2015). Microelectron. Reliab. 54 (Issue 1) (2014) 49–56.
[50] J. Wei, S. Liu, S. Li, J. Fang, T. Li, W. Sun, Comprehensive Investigations on [57] H. Kabza, H.-J. Schulze, Y. Gerstenmaier, P. Voss, J. Wilhelmi, W. Schmid,
degradations of dynamic characteristics for SiC power MOSFETs under repetitive F. Pfirsch, K. Platzoder, Cosmic radiation as a cause for power device failure and
avalanche shocks, IEEE Trans. Power Electron. 34 (3) (March 2019). possible countermeasures, in: Proceedings of the 6th International Symposium on
[51] X. Deng, W. Huang, X. Li, X. Li, C. Chen, Y. Wen, J. Ding, W. Chen, Y. Sun, Power Semiconductor Devices and ICs ISPSD, May 1994, pp. 9–12.
B. Zhang, Investigation of failure mechanisms of 1200 V rated trench SiC MOSFETs [58] Gerald Soelkner, Winfried Kaindl, Michael Treu, Dethard Peters: Reliability of SiC
under repetitive avalanche, Stress IEEE Transactions on Power Electronics 37 (9) power devices against cosmic radiation-induced failure, Mater. Sci. Forum, ISSN:
(September 2022). 1662-9752, Vols. 556–557, pp 851-856..
[52] Application Note AN-7514 “Single-pulse Unclamped inductive switching: A rating [59] C. Felgemacher, S. Vasconcelos Araujo, P. Zacharias, K. Nesemann, A. Gruber,
system”, 2002 Fairchild Semiconductor Corporation Rev. 1.0.3 • 10/8/10. Cosmic radiation ruggedness of Si and SiC power semiconductors, in: Proceedings
[53] J. Liu, M. Xiao, R. Zhang, S. Pidaparthi, C. Drowley, L. Baubutri, A. Edwards, of the 2016 28th International Symposium on Power Semiconductor Devices and
H. Cui, C. Coles, Y. Zhang, Trap-mediated avalanche in large-area 1.2 kV vertical ICs (ISPSD) June 12 – 16, Prague, Czech Republic, 2016.
GaN p-n diodes, IEEE Electron. Device Lett. 41 (9) (September 2020). [60] C. Martinella, et al., Impact of terrestrial neutrons on the reliability of SiC VD-
[54] M. Vivona, P. Fiorenza, V. Scuderi, F. La Via, F. Giannazzo, F. Roccaforte, Space MOSFET Technologies, IEEE Trans. Nucl. Sci. 68 (5) (MAY 2021).
charge limited current in 4H-SiC Schottky diodes in the presence of stacking faults, [61] How Infineon controls and assures the reliability of SiC based power
Appl. Phys. Lett. 123 (2023) 072101. semiconductors, Infineon white paper. www.infineon.com. August 2020.

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