Memory Management © Background © Swapping © Contiguous Memory Allocation © Paging © Structure of the Page Table ® Segmentation © Example: The Intel PentiumObjectives ® To provide a detailed description of various ways of organizing memory hardware ® To discuss various memory-management techniques, including paging and segmentation ® To provide a detailed description of the Intel Pentium, which supports both pure segmentation and segmentation with pagingground © Program must be brought (from disk) into memory and placed within a process for it to be Tun ® Main memory and registers are only storage CPU can access directly © Register access in one CPU clock (or less) ® Main memory can take many cycles ® Cache sits between main memory and CPU registers © Protection of memory required to ensure correct operationeand Limit © A pair of base and limit registers define the logical addr ‘operating system, 256000 process 300040 pf 300040 process base 420940 {120800 ] sae process limit 880000 1024000inding of Instructions and © Address binding of instructions and data to memory addresses can happen at three different stages ® Compile time: If memory location known a priori, absolute code can be generated; must recompile code if starting location changes ® Load time: Must generate relocatable code if memory location is not known at compile time © Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another. Need hardware support for address maps (e.g., base and limit registers)ieeeLogical vs. Physical Address Space © The concept of a logical address space that is bound to a separate physical address space is central to proper memory management ® Logical address - generated by the CPU; also referred to as virtual address ® Physical address — address seen by the memory unit © Logical and physical addresses are the same in compile- time and load-time address-binding schemes; logical (virtual) and physical addresses differ in execution-time address-binding schemeMemory-Management Unit (mu) © Hardware device that maps virtual to physical address © In MMU scheme, the value in the relocation register is added to every address generated by a user process at the time it is sent to memory © The user program deals with logical addresses; it never sees the real physical addressesDynamic Loading © Routine is not loaded until it is called © Better memory-space utilization; unused routine is never loaded © Useful when large amounts of code are needed to handle infrequently occurring cases ® No special support from the operating system is required implemented through program designDynamic Linking © Linking postponed until execution time © Small piece of code, stub, used to locate the appropriate memory-resident library routine © Stub replaces itself with the address of the routine, and executes the routine © Operating system needed to check if routine is in processes’ memory address. ® Dynamic linking is particularly useful for libraries © System also known as shared librariesSwapping A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution Backing store - fast disk large enough to accommodate copies of all memory images forall users; must provide direct access to these memory images Roll out, roll in - swapping variant used for prio lester pivority process 1s swapped out so higher-p1 execute --based scheduling algorithms; ‘ity process can be loaded and Major part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped Modified versions of swapping are found on many systems (i.e., UNIX, Linux, and Windows) System maintains a ready queue of ready-to-run processes which have memory images on dislContiguous Allocation © Main memory usually into two partitions: © Resident operating system, usually held in low memory with interrupt vector © User processes then held in high memory © Relocation registers used to protect user processes from each other, and from changing operating-system code and data © Base register contains value of smallest physical address © Limit register contains range of logical addresses — each logical address must be less than the limit register © MMU maps logical address dynamicallyrdware Support for Relocati trap: addressing errorontiguous Allocation © Multiple-partition allocation © Hole - block of available memory; holes of various size are scattered throughout memory © When a process arrives, it is allocated memory from a hole large enough to. accommodate it © Operating system maintains information about: a) allocated partitions _b) free partitions (hole) os os os os process 5 process 5 process 5 process § process 9 process 9 process |—> —7 process 10 process 2 process 2 process 2 process 2Problem How to satisfy a request of size n from a list of free holes © First-fit: Allocate the first hole that is big enough © Best-fit: Allocate the smallest hole that is big enough; must search entire list, unless ordered by size © Produces the smallest leftover hole © Worst-fit: Allocate the largest hole; must also search entire list O Produces the largest leftover hole First-fit and best-fit better than worst-fit in terms of speed and storage utilizationFragmentation ® External Fragmentation - total memory space exists to satisfy a request, but it is not contiguous © Internal Fragmentation — allocated memory may be slightly larger than requested memory; this size difference is memory internal to a partition, but not being used © Reduce external fragmentation by compaction © Shuffle memory contents to place all free memory together in one large block © Compaction is possible only if relocation is dynamic, and is done at execution time © 1/0 problem Latch job in memory while it is involved in I/O Do I/O only into OS buffersPaging © Logical address space of a process can be noncontiguous; process is allocated physical memory whenever the latter is available ® Divide physical memory into fixed-sized blocks called frames (size is power of 2, between 512 bytes and 8,192 bytes) ® Divide logical memory into blocks of same size called pages © Keep track of all free frames © To runa program of size m pages, need to find n free frames and Joad program © Set up a page table to translate logical to physical addresses © Internal fragmentationcPU il 11 ttt Le iy physical memory1| page o page 2 page 1 Yo 0 8 oN page 3 physical memoryphysical mernory 32-byte memory and 4-byte pagesFree Frames free-frame list free-frame list a 13 12 13 |page 1 14 14 [page o 15 15 re] | se] | 17 7 18 18 |page 2 ro] 19 20 20 [page 3 21 new-process page table 21 (a) Before allocation (by After allocationImplementation of Page Table © Page table is kept in main memory © Page-table base register (PTBR) points to the page table e eo length register (PRLR) indicates size of the page table © In this scheme eo data/instruction access requires two memory accesses. One for the page table and one for the data/instruction. © The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs) © Some TLBs store address-space identifiers (ASIDs) in each TLB entry — uniquely identifies each process to provide address-space protection for that processAssociative Memor Page # Frame ® Associative mé Address translation (p, d) ® If pis in associative register, get frame # out © Otherwise get frame # from page table in memoryPaging Hardware With TLB logical addressEffective Access Time © Associative Lookup = € time unit ® Assume memory cycle time is 1 microsecond ® Hit ratio — percentage of times that a page number is found in the associative registers; ratio related to number of associative registers © Hit ratio= a ® Effective Access Time (EAT) EAT = (1+ €) w+ (2+€)(1- @) =2+6-0Memory Protection © Memory protection implemented by associating protection bit with each frame © Valid-invalid bit attached to each entry in the page table: ® “valid” indicates that the associated page is in the process’ logical address space, and is thus a legal page ® “invalid” indicates that the page is not in the process’ logical address spaceShared Pages ® Shared code © One copy of read-only (reentrant) code shared among processes (i.e., text editors, compilers, window systems). © Shared code must appear in same location in the logical address space of all processes. ® Private code and data © Each process keeps a separate copy of the code and data © The pages for the private code and data can appear anywhere in the logical address spacecant | process P, ed 1 ed 2 eda data 3 process Py page tabte for P, page tabte for Py 3} eat edt z 4] ed2 oa2 a 5 ed3 2 i 6] eda data2 | page table for P, 7| daz process P, 8Structure of the Page Table © Hierarchical Paging © Hashed Page Tables © Inverted Page TablesHierarchical Page Tables © Break up the logical address space into multiple page tables © Asimple technique is a two-level page tableTwo-Level Paging Example © A logical address (on 32-bit machine with 1K page size) is divided into: © a page number consisting of 22 bits © a page offset consisting of 10 bits © Since the page table is paged, the page number is further divided into: © aiz-bit page number © auo-bit page offset © Thus, a logical address is as follows: page number page offset 12 10 10 where p, is an index into the outer page table, and p, is the displacement within the page of the outer page tableAddress-Translation Scheme logical address Pi [ped = - = | outer page table page of page tableThree-level Paging Scheme outerpage _ inner page offset Pi P | d 42 10 12 2nd outer page , outerpage innerpage offset Se See ee) 32 10 10 12Hashed Page Tables © Common in address spaces > 32 bits © The virtual page number is hashed into a page table © This page table contains a chain of elements hashing to the same location ® Virtual page numbers are compared in this chain searching for a match © Ifa match is found, the corresponding physical frame is extractedHashed Page Table physical logical address address P14 eda physical a [as pr eee reas hash tableInverted Page Table ® One entry for each real page of memory © Entry consists of the virtual address of the page stored in that real memory location, with information about the process that owns that page ® Decreases memory needed to store each page table, but increases time needed to search the table when a page reference occurs ® Use hash table to limit the search to one — or at most a few — page-table entriesphysical address page tableSegmentation © Memory-management scheme that supports user view of memory © A program isa collection of segments ® Asegment isa logical unit such as: main program procedure function. method object local variables, global variables common block stack symbol table arraysLogical View of Segmentation tlm) & user space physical memory spaceSegmentation Architecture © Logical address consists of a two tuple: , © Segment table - maps two-dimensional physical addresses; each table entry has: ® base - contains the starting physical address where the segments reside in memory © limit - specifies the length of the segment ® Segment-table base register (STBR) points to the segment table’s location in memory © Segment-table length register (STLR) indicates number of segments used by a program; segment number s is legal if s < STLRSegmentation Architecture (Cont.) © Protection © With each entry in segment table associate: © validation bit = 0 = illegal segment © read/write/execute privileges © Protection bits associated with segments; code sharing occurs at segment level © Since segments vary in length, memory allocation is a dynamic storage-allocation problem ® A segmentation example is shown in the following diagramtrap: addressing error physical memorysubroutine, ‘stack limit [base |] | 1000" 1400 1| ‘a0 | 6300 | 9200 2] 400 | 4300 | tone | S00 powers 3} segment table 4390 | 4700 logical actaress spaco jsoament 4| 700 6300 Esenenta e700 physical memoryExample: The Intel Pentium © Supports both segmentation and segmentation with paging © CPU generates logical address ® Given to segmentation unit © Which preduces linear addresses © Linear address given to paging unit ® Which generates physical address in main memory © Paging units form equivalent of MMUgical to Physical Addres: logical address physical address | page number page offset Pi P2 d 10 10 12Intel Pentium Segmentation logical address. |_ selector offset descriptor table segment descriptor 32-bit linear addressPentium Paging Architecture (logical address) Page directory , page table offset at 2e'24 144 oL cra register-Inear Address in Linux Broken into four parts: global directory middle directory page table offsetThree-level Paging in Linux (linear address) global directory | middle directory age table offset , global directory niidiie directory page frame. global directory entry middle case directory entry. registerThank You