SWITCHING THEORY AND LOGIC DESIGN QUESTION BANK

UNIT – I

Syllabus

REVIEW OF NUMBER SYSTEMS & CODES

Representation of numbers of different radix, conversation from one radix to another radix, r-1’s
compliments, and r’s compliments of signed members. Gray code, 4-bit codes; BCD, Excess-3,
2421, 84-2-1 code, etc. Error detection & correction codes: Parity checking, even parity, odd parity,
Hamming code.
BOOLEAN THEOREMS AND LOGIC OPERATIONS
Boolean theorems, principle of Complementation & Duality, De-morgan theorems. Logic
operations; Basic logic operations - NOT, OR, AND, Universal Logic operations, EX-OR, EX-
NOR operations. Standard SOP and POS Forms, NAND-NAND and NOR-NOR realizations,
Realization of three-level logic circuits.
Question Bank

PART – A

1. Write the importance of the radix or base in number systems.

2. Convert Decimal 153 to Octal.
3. What is a self-complement code and write an example for it?
4. What is the difference between BCD and Excess-3 codes?
5. What are the alphanumeric codes and write examples?
6. What is Consensus Theorem?
7. Write short notes on Error Detection and Correction codes.
8. What are the Complement and Duality Theorems?
9. What are the Basic gates and draw their symbols along with truth tables?
10. What are the Universal gates and draw their symbols along with truth tables?
 PART - B
1 a) Represent decimal number 8620 in (a) BCD (b) excess-3 code (c) 2421 code, and (d) binary
number. [5M, May-2025, Supple]
b) Represent the decimal number 6248 in excess‐3 code. [5M, Nov-2024, Reg]
2. a) Convert the decimal number 431 to binary in two ways: (a) convert directly to binary; (b)
Convert first to hexadecimal and then from hexadecimal to binary. Which method is faster?
[5M, Nov-2024, Reg]
b) Obtain the 1’s and 2’s complements of the following binary numbers:
(i) 00010000 (ii) 10101110 [5M, Nov-2024, Reg]
3. a) Convert the following (i) (123.589)10 = ( )8. (ii) (1011011111101.10101)2 = ( )16 [4M]
b) Represent +35 and -35 in Sign-magnitude, sign 1’s complement, and sign 2’s complement
representation. [4M]
c) Convert (525)10 into its Excess-3 code. [2M, July–2022, Supple]
4. a) Find the 9’s and the 10’s complement of the following decimal numbers:
i. 25 ii. 478 iii. 036 [5M, Nov-2024, Reg]
b) Represent the decimal number 6248 in excess‐3 code. [5M, Nov–2024, Reg]
5. a) Given the 8-bit data word 11000100, generate the 12-bit Hamming-code word.
[7M, May-2025, Supple]
b) State and prove De-morgan theorems. [3M, May-2025, Supple]
6. The binary numbers listed have a sign bit in the leftmost position and if negative numbers are
in 2’s complement form. Perform the arithmetic operations indicated and verify the answers.
(i) 101011 + 111000 (ii) 001110 + 110010
(iii) 111001 – 001010 (iv) 101011 – 100110 [14M, Jan-2023, Set-
1, Reg]
7. a) Convert the given expression in standard SOP form f (A, B, C) = AC+BA+BC. [7M]
b) Convert the given expression in standard POS form y=A.(A+B+C). [7M, Jan-2023, Set-2,Reg]
8. a) Represent the decimal numbers 0 to 7, -7 to -1 in signed magnitude, 1’s complement, and 2’s
complement forms using 4-bits. [7M]
b) Explain about weighted and non-weighted codes. [7M, Jan-2023, Set–3, Reg]
9. a) How do you convert a Gray number to binary? Generate a 4-bit Gray code directly using the
mirror image property. [7M, Jan–2023, Set–4, Reg]
b) What are the differences between canonical form and standard form? Explain [7M]
10. Convert the following expression into SOP and POS
(i) (AB+C) (B+C1D) (ii) x1 +(x+y1)(y+z1) [14M, Jan-2023, Set–4, Reg]
 UNIT – II

Syllabus

MINIMIZATION TECHNIQUES
Minimization and realization of switching functions using Boolean theorems, K-Map (up to
6 variables) and tabular method (Quine-McCluskey method) with only four variables and a single
function.
COMBINATIONAL LOGIC CIRCUITS DESIGN
Design of Half adder, full adder, half subtractor, full subtractor, applications of full adders; 4-bit
adder-subtractor circuit, BCD adder circuit, Excess 3 adder circuit and carry look-ahead adder
circuit, Design code converts using Karnaugh method and draw the complete circuit diagrams.
Question Bank

PART – A

1. Define Literal, Term, and Function.

2. How many minterms and maxterms can be formed by using n-variables?
3. Simplify the Boolean function: f = x + x1y?
4. What is the advantage of the tabular method?
5. Explain the term prime implicant.
6. Write the truth table of Half Adder.
7. Write the output functions of the Full Subtractor.
8. What is a Combinational Logic Circuit?
9. Draw the logic diagram of Full Adder using two Half Adders and an OR gate.
10. Reduce the following Boolean expressions to F = A1C1 + ABC + AC1?

PART- B
1. Obtain the simplified POS and SOP expression for the function using k-maps: F (A, B, C,
D) = Σm(1,3,5,8,9,13) + Σd(0,7,12,14) [8M, July–2023, Supple]
2. a) Simplify the following function using k-maps and implement the same using NAND gates.
F(A, B, C) = Σm(0,2,4,5,6,7) [7M, July-2023, Supple]
b) Briefly explain the tabulation procedure for the determination of prime implicants. [7M]
3. a) Simplify the Boolean function F(A, B, C, D) by first finding the essential prime implicants.
F(A, B, C, D) = ∑(0, 2, 3, 5, 7, 8, 9, 10, 11, 13, 15) [4M, May–2025, Supple]
b) Design Carry look-a-head adder circuit. [6M]
4. a) Explain the working of Full Adder circuit with truth table and logic diagram.
[5M, Nov-2024, Reg]
b) Simplify the following functions, and implement them with two-level NAND gate circuits:
F (A, B, C, D) = A’ + B + D’ + B’C [5M]
5. a) Simplify the following Boolean function using K-Map.
(a) F(x, y, z) = Σ(0, 1, 5, 7)
(b) A’B + BC’ + B’C’
(c) F(a, b, c, d) = Σ(0, 2, 4, 5, 6, 7, 8, 10, 13, 15) [6M, May-2025, Supple]
b) Design a code converter to convert BCD to Excess-3 Code. [4M]
6. a) Reduce the following function using K- map F = 3,4,5,6,7,12,13) + d(8,10,14,15) [7M]
b) Draw a logic diagram of the Ex-OR and EXNOR gate using the NAND gate and prove it using
a Boolean equation and truth table. [7M, Jan–2023, Set-3, Reg]
7. a) Write the differences between sequential and combinational circuits with an example.
[7M]
b) Simplify the following Boolean expressions, using four-variable K-maps:
F= A’B’C’D’ + ACD’ + B’CD’ + A’BCD + BC’D. [5M, Nov–2023, Reg]
8. a) Simplify the following Boolean expressions to a minimum number of literals:
F= xyz + x’y + xyz’ [5M, Nov-2024, Reg]
b) Draw logic diagrams of the circuits that implement the original and simplified expressions of
part (a). [5M]
9. a) Design a Binary to BCD code converter using K-map. [7M, Jan-2023, Set-4, Reg]
b) Convert the BCD to XS-3 and XS-3 to BCD by using a full adder [7M]
10. a) Express the following function as a sum of minterms and as a product of maxterms:
F (A, B, C, D) = B’D + A’D + BD [5M, Nov-2024, Reg]
b) Find the complement of F = wx + yz then show that FF’ = 0 and F + F’ = 1. [5M]
 UNIT – III

Syllabus

COMBINATIONAL LOGIC CIRCUITS DESIGN USING MSI & LSI

Design of Half adder, full adder, half subtractor, full subtractor, applications of full adders, 4-bit
binary subtractor, adder-subtractor circuit, BCD adder circuit, Excess 3 adder circuit, look-a-head
adder circuit, Design of decoder, demultiplexer, 7 segment decoder, higher order demultiplexing,
encoder, multiplexer, higher order multiplexing, realization of Boolean functions using decoders
and multiplexers, priority encoder, 4-bit digital comparator.
INTRODUCTION OF PLD’s
PLDs: PROM, PAL, PLA -Basics structures, realization of Boolean functions, Programming table.

Question Bank

PART – A

1. Explain the advantages of the Carry Look-Ahead adder circuit.

2. List the applications of full adders.
3. Define Multiplexer.
4. Define Encoders.
5. Write the basic difference between PROM, PLA, and PAL.
6. What is the difference between DEMUX and Decoder?
7. Draw the logic diagram of 8X1 MUX by using 2x1 MUXs.
8. Write the output functions of a 2-bit digital comparator.
9. How is Priority Encoder different from Encoder?
10. Write the applications of 7-segment displays.

PART - B

1. a) Draw and explain the operation of the 4-bit binary adder-subtractor circuit. [4M]
b) Design a combinational circuit that converts a 4-bit binary number to a 4-bit Gray code
number. Implement the circuit with Exclusive-OR gates. [10M, July-2023, Supple]
2. a) Realize full adder and full subtractor using 8:1 MUX. [8M]
 b) Explain the working of the Four-input priority encoder with the truth table and logic diagram.
[5M, Nov-2024, Reg]

3. a) Realize the following four Boolean functions using PAL. [10M]

F1(w,x,y,z) = 0,1,2,3,7,9,11
F2(w,x,y,z) = 0,1,2,3,10,12,14
F3(w,x,y,z) = 0,1,2,3,10,13,15
F4(w,x,y,z) = 4,5,6,7,9,15
b) Draw and explain the basic structure of PROM. [4M, July-2023, Supple]
4. Design and implement 4-bit Binary Adder/subtractor. [10M, July-2022, Supple]
5. a) Implement Full adder with a suitable decoder. [4M, May-2025, Supple]
b) A Combinational circuit is defined by the functions [6M]
F1(A, B, C) = ∑(3, 5, 6, 7) F2(A, B, C) = ∑(0, 2, 4, 7)
Implement the circuit with a PLA having three inputs, four product terms, and two outputs.
6. Design a combinational circuit using PROM that accepts 3-bit binary number and generates its
equivalent excess-3 code. [10M, July-2022, Supple]
7. Design a combinational circuit using PROM. The circuit accepts a 3-bit number and generates an
O/p binary number equal to square of the input number. [14M, Jan-2023, Set-1, Reg]
8. a) Implement the following Boolean functions using PLA.
A(x,y,z) = ∑(1,2,4,6), B(x,y,z) = ∑(0,1,6,7), and C(x,y,z) = ∑(2,6). [7M]
b) Design a combinational circuit using PROM that accepts a 3-bit binary number and generates
its equivalent excess -3 code. [7M, Jan-2023, Set-2, Reg]
9. a) Construct a 16x1 multiplexer with two 8x1 and one 2x1 multiplexers. Use block diagrams for
the three multiplexers. [5M, May-2025, Supple]
b) Design a Priority Encoder for the priority of inputs D0>D1>D2>D3 [5M]
10. a) Design a 1 to 8 Demultiplexer with a diagram and truth table. [7M]
b) Design a 4-bit digital comparator. [7M, Jan-2023, Set-3, Reg]
 UNIT – IV

Syllabus

SEQUENTIAL CIRCUITS I

Classification of sequential circuits (synchronous and asynchronous), operation of NAND & NOR
Latches and flip-flops; truth tables and excitation tables of RS flip-flop, JK flip-flop, T flip-flop, D
flip-flop with reset and clear terminals. Conversion from one flip-flop to another flip-flop. Design
of 5ripple counters, design of synchronous counters, Johnson counter, ring counter. Design of
registers - Buffer register, control buffer register, shift register, bi-directional shift register,
universal shift, register
Study the following relevant ICs and their relevant functions 7474,7475,7476,7490,7493,74121.

Question Bank
PART – A
1. What is a Sequential Logic Circuit?
2. What is the difference between a Flip-flop and a Latch?
3. Draw the logic diagram of the basic NAND Latch.
4. Write the applications of Flip-flops.
5. How many states are present in Ring and Johnson Ring Counters by using n-flipflops?
6. What is the basic difference between Synchronous and Asynchronous Counters?
7. What is the Race-around condition in JK Flip-flops?
8. What are the different triggering techniques used in Flip-flops?
9. How Race-around problem can be eliminated in JK flip-flops?
10. Which registers are called Ripple Counters?

PART-B
1. a) Draw the logic diagram of the Parallel-in, Serial-out shift register and explain its operation.
[6M]
b) Convert a D flip-flop to a T flip-flop with an example. [8M, July-2023, Supple]
2. a) Explain about Ring counter. [7M]
b) Explain the operation of the bi-directional shift register. [7M, July-2023, Supple]
3. a) Design 3 bit Johnson counter and neatly draw the timing waveforms. [6M, May-2025, Supple]
b) With a neat logic diagram explain the working of SR Flip Flop. [4M]

4. a) Design a 4-bit ripple counter and neatly draw the timing waveforms. [6M, May-2025, Supple]
b) Convert JK Flip Flop to D Flip Flop.
[4M]
5. a) What is a flip-flop? Design the basic flip-flop using NOR gates and explain. [7M]
b) What is an excitation table? Write the excitation tables for JK and T flip-flops.
[7M, Jan2023, Set-1, Reg]
6. a) Draw the diagram of the master-slave JK flip-flop. [7M]
b) Convert the JK flip-flop into a T flip-flop. [7M, Jan-2023, Set-2, Reg]
7. a) What do you mean by Characteristic Tables of flip-flop? Draw the Characteristic Tables of D
and S-R flip-flop. [5M, Nov-2024, Reg]
b) Draw the logic diagram of a four‐bit binary ripple countdown counter using flip‐flops that
trigger on the positive edge of the clock. [5M]
8. a) Draw the logic diagram of a JK flip-flop and using an excitation table explain its operation.
[7M]
b) Draw and explain the operation of the 4-bit ring counter. [7M, Jan-2023, Set-3, Reg]
9. a) What is the Race condition and explain the operation of the clocked RS flip-flop [7M]
b) Convert the JK Flip flop into RS flip-flop. [7M, Jan-2023, Set-4, Reg]
10. a) What is a counter? implement and explain the basic operation of 4-bit up counter [7M]
b) With neat diagram explain the operation of 3-bit universal shift register. [7M, Jan-2023, Set-
4, Reg]
 UNIT – V

Syllabus

SEQUENTIAL CIRCUITS II
Finite state machine; state diagrams, state tables, reduction of state tables. Analysis of clocked
sequential circuits Mealy to Moore conversion and vice-versa. Realization of sequence generator,
Design of Clocked Sequential Circuit to detect the given sequence (with overlapping or without
overlapping)

Question Bank
PART – A
1. What is a Finite State Machine?
2. What is Mealy Machine?
3. What is the Moore Machine?
4. Differentiate between Mealy and Moore machines.
5. What is the State Diagram of FSM?
6. What is the State Table of FSM?
PART-B

1. Design an FSM for a serial sequence detector with the pattern “1010” with overlapping and
with non-overlapping. [10M, July-2023, Supple]
2. A sequential circuit has one input and one output. The state diagram is shown below: Design
Mealy machine by using D flip-flops. [10M, July-2023, Supple]

3. a) Using JK flip‐flops, Design a counter with the following repeated binary sequence:
 0, 1, 2, 3, 4, 5, 6 [5M, Nov-2024, Reg]
b) Design a four‐bit binary synchronous counter with D flip‐flops. [5M]

4. a) A sequential circuit has one input and one output. The state diagram is shown below. Design
the sequential circuit with RS flip-flop. [10M]

b) Distinguish between Moore and Mealy Machines. [4M, July-2022, Supple]

5. a) A sequential circuit has one flip-flop Q, two inputs x and y, and one output S. It consists of a
full-adder circuit connected to a D flip-flop, as shown in Fig. below. Derive the state table and
state diagram of the sequential circuit. [5M, Nov-2024, Reg]

b) Design a finite state machine FSM for a serial two’s complement block and also draw the
logic diagram associated with it by using D flip-flop. [5M]
6. a) Write the difference between Mealy and Moore machines. [7M, Jan-2023, Set-1, Reg]
b) Convert the given Mealy machine to the Moore machine by using a transition diagram. [7M]

Input
State Output
a b
A B A 0
B B C 0
C B D 0
 D B A 1

7. a) Draw the circuit for Moore-type FSM. [7M]

b) Draw the state diagram of mod-8 Up - Down counter in the Moore model and obtain its state
table. [7M, Jan-2023, Set-2, Reg]
8. a) What is meant by state reduction? Explain what are the advantages of state reduction in
sequential circuits. [7M]
b) Draw a state diagram of a sequence detector that can detect 101. [7M, Jan-2023, Set-2, Reg]
9. a) Discuss the procedure of Mealy to Moore conversion. [7M]

b) Explain sequential circuits, state table, and state diagram. [7M, Jan-2023, Set-3, Reg]

10. For the state diagram shown below, write the state table, minimize the stat table and draw the
reduced state diagram. [10M, May-2025, Supple]

Prepared by Verified by Head of the Department