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Spartan and Spartan-XL FPGA Families Data Sheet

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DS060 (v1.8) June 26, 2008

Product Specification System level features - Available in both 5V and 3.3V versions - On-chip SelectRAM memory - Fully PCI compliant - Full readback capability for program verification and internal node observability - Dedicated high-speed carry logic - Internal 3-state bus capability - Eight global low-skew clock or signal networks - IEEE 1149.1-compatible Boundary Scan logic - Low cost plastic packages available in all densities - Footprint compatibility in common packages Fully supported by powerful Xilinx ISE Classics development system - Fully automatic mapping, placement and routing

Introduction
The Spartan and the Spartan-XL FPGA families are a high-volume production FPGA solution that delivers all the key requirements for ASIC replacement up to 40,000 gates. These requirements include high performance, on-chip RAM, core solutions and prices that, in high volume, approach and in many cases are equivalent to mask programmed ASIC devices. By streamlining the Spartan series feature set, leveraging advanced process technologies and focusing on total cost management, the Spartan series delivers the key features required by ASIC and other high-volume logic users while avoiding the initial cost, long development cycles and inherent risk of conventional ASICs. The Spartan and Spartan-XL families in the Spartan series have ten members, as shown in Table 1.

Additional Spartan-XL Family Features

Spartan/Spartan-XL FPGA Features

Note: The Spartan series devices described in this data sheet include the 5V Spartan family and the 3.3V Spartan-XL family. See the separate data sheets for more advanced members for the Spartan Series. First ASIC replacement FPGA for high-volume production with on-chip RAM Density up to 1862 logic cells or 40,000 system gates Streamlined feature set based on XC4000 architecture System performance beyond 80 MHz Broad set of AllianceCORE and LogiCORE predefined solutions available Unlimited reprogrammability Low cost Max System Gates 5,000 10,000 20,000 30,000 40,000

3.3V supply for low power with 5V tolerant I/Os Power down input Higher performance Faster carry logic More flexible high-speed clock network Latch capability in Configurable Logic Blocks Input fast capture latch Optional mux or 2-input function generator on outputs 12 mA or 24 mA output drive 5V and 3.3V PCI compliant Enhanced Boundary Scan Express Mode configuration

Table 1: Spartan and Spartan-XL Field Programmable Gate Arrays Logic Device XCS05 and XCS05XL XCS10 and XCS10XL XCS20 and XCS20XL XCS30 and XCS30XL XCS40 and XCS40XL Cells 238 466 950 1368 1862 Typical Gate Range (Logic and RAM)(1) 2,000-5,000 3,000-10,000 7,000-20,000 10,000-30,000 13,000-40,000 CLB Matrix 10 x 10 14 x 14 20 x 20 24 x 24 28 x 28 Total CLBs 100 196 400 576 784 Max. Total No. of Avail. Distributed Flip-flops User I/O RAM Bits 360 616 1,120 1,536 2,016 77 112 160 192 205(2) 3,200 6,272 12,800 18,432 25,088

Notes: 1. Max values of Typical Gate Range include 20-30% of CLBs used as RAM. 2. XCS40XL provided 224 max I/O in CS280 package discontinued by PDN2004-01.

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Spartan and Spartan-XL FPGA Families Data Sheet

General Overview
Spartan series FPGAs are implemented with a regular, flexible, programmable architecture of Configurable Logic Blocks (CLBs), interconnected by a powerful hierarchy of versatile routing resources (routing channels), and surrounded by a perimeter of programmable Input/Output Blocks (IOBs), as seen in Figure 1. They have generous routing resources to accommodate the most complex interconnect patterns. The devices are customized by loading configuration data into internal static memory cells. Re-programming is possible an unlimited number of times. The values stored in these

memory cells determine the logic functions and interconnections implemented in the FPGA. The FPGA can either actively read its configuration data from an external serial PROM (Master Serial mode), or the configuration data can be written into the FPGA from an external device (Slave Serial mode). Spartan series FPGAs can be used where hardware must be adapted to different user applications. FPGAs are ideal for shortening design and development cycles, and also offer a cost-effective solution for production rates well beyond 50,000 systems per month.

IOB

IOB

IOB

IOB

IOB

IOB

IOB

IOB CLB IOB CLB CLB CLB

IOB

BSCAN

OSC

IOB IOB

IOB CLB IOB Routing Channels IOB CLB IOB CLB CLB CLB CLB CLB CLB

IOB IOB

IOB IOB

IOB CLB IOB CLB CLB CLB

IOB IOB

IOB

IOB

IOB

IOB

IOB

IOB

IOB

IOB

RDBK

START -UP

VersaRing Routing Channels

DS060_01_081100

Figure 1: Basic FPGA Block Diagram

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Spartan and Spartan-XL FPGA Families Data Sheet

Spartan and Spartan-XL devices provide system clock rates exceeding 80 MHz and internal performance in excess of 150 MHz. In addition to the conventional benefit of high volume programmable logic solutions, Spartan series FPGAs also offer on-chip edge-triggered single-port and dual-port RAM, clock enables on all flip-flops, fast carry logic, and many other features. The Spartan/XL families leverage the highly successful XC4000 architecture with many of that familys features and benefits. Technology advancements have been derived from the XC4000XLA process developments.

Configurable Logic Blocks (CLBs)

The CLBs are used to implement most of the logic in an FPGA. The principal CLB elements are shown in the simplified block diagram in Figure 2. There are three look-up tables (LUT) which are used as logic function generators, two flip-flops and two groups of signal steering multiplexers. There are also some more advanced features provided by the CLB which will be covered in the Advanced Features Description, page 13.

Function Generators
Two 16 x 1 memory look-up tables (F-LUT and G-LUT) are used to implement 4-input function generators, each offering unrestricted logic implementation of any Boolean function of up to four independent input signals (F1 to F4 or G1 to G4). Using memory look-up tables the propagation delay is independent of the function implemented. A third 3-input function generator (H-LUT) can implement any Boolean function of its three inputs. Two of these inputs are controlled by programmable multiplexers (see box "A" of Figure 2). These inputs can come from the F-LUT or G-LUT outputs or from CLB inputs. The third input always comes from a CLB input. The CLB can, therefore, implement certain functions of up to nine inputs, like parity checking. The three LUTs in the CLB can also be combined to do any arbitrarily defined Boolean function of five inputs.

Logic Functional Description

The Spartan series uses a standard FPGA structure as shown in Figure 1, page 2. The FPGA consists of an array of configurable logic blocks (CLBs) placed in a matrix of routing channels. The input and output of signals is achieved through a set of input/output blocks (IOBs) forming a ring around the CLBs and routing channels. CLBs provide the functional elements for implementing the users logic. IOBs provide the interface between the package pins and internal signal lines. Routing channels provide paths to interconnect the inputs and outputs of the CLBs and IOBs.

The functionality of each circuit block is customized during configuration by programming internal static memory cells. The values stored in these memory cells determine the logic functions and interconnections implemented in the FPGA.

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Spartan and Spartan-XL FPGA Families Data Sheet

B G-LUT
G4 G3 G2 G1 SR H1 DIN F4 F3 F2 F1 F4 Logic F3 Function of G F2 F1-F4 F1 G4 Logic G3 Function of G G2 G1-G4 G1 G D CK EC SR Q YQ

H-LUT
Logic Function H H1 of F-G-H1 F SR D CK EC Q XQ Y

F-LUT
K EC Multiplexer Controlled by Configuration Program

DS060_02_0506 01

Figure 2: Spartan/XL Simplified CLB Logic Diagram (some features not shown) A CLB can implement any of the following functions: Any function of up to four variables, plus any second function of up to four unrelated variables, plus any third function of up to three unrelated variables
Note: When three separate functions are generated, one of the function outputs must be captured in a flip-flop internal to the CLB. Only two unregistered function generator outputs are available from the CLB.

Flip-Flops
Each CLB contains two flip-flops that can be used to register (store) the function generator outputs. The flip-flops and function generators can also be used independently (see Figure 2). The CLB input DIN can be used as a direct input to either of the two flip-flops. H1 can also drive either flip-flop via the H-LUT with a slight additional delay. The two flip-flops have common clock (CK), clock enable (EC) and set/reset (SR) inputs. Internally both flip-flops are also controlled by a global initialization signal (GSR) which is described in detail in Global Signals: GSR and GTS, page 20.

Any single function of five variables Any function of four variables together with some functions of six variables Some functions of up to nine variables.

Implementing wide functions in a single block reduces both the number of blocks required and the delay in the signal path, achieving both increased capacity and speed. The versatility of the CLB function generators significantly improves system speed. In addition, the design-software tools can deal with each function generator independently. This flexibility improves cell usage.

Latches (Spartan-XL Family Only)

The Spartan-XL family CLB storage elements can also be configured as latches. The two latches have common clock (K) and clock enable (EC) inputs. Functionality of the storage element is described in Table 2.

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Spartan and Spartan-XL FPGA Families Data Sheet Clock Input Q SR SR D Q Q D Q Each flip-flop can be triggered on either the rising or falling clock edge. The CLB clock line is shared by both flip-flops. However, the clock is individually invertible for each flip-flop (see CK path in Figure 3). Any inverter placed on the clock line in the design is automatically absorbed into the CLB. Clock Enable The clock enable line (EC) is active High. The EC line is shared by both flip-flops in a CLB. If either one is left disconnected, the clock enable for that flip-flop defaults to the active state. EC is not invertible within the CLB. The clock enable is synchronous to the clock and must satisfy the setup and hold timing specified for the device. Set/Reset Dont care Rising edge (clock not inverted). The set/reset line (SR) is an asynchronous active High control of the flip-flop. SR can be configured as either set or reset at each flip-flop. This configuration option determines the state in which each flip-flop becomes operational after configuration. It also determines the effect of a GSR pulse during normal operation, and the effect of a pulse on the SR line of the CLB. The SR line is shared by both flip-flops. If SR is not specified for a flip-flop the set/reset for that flip-flop defaults to the inactive state. SR is not invertible within the CLB.

Table 2: CLB Storage Element Functionality Mode Power-Up or GSR Flip-Flop Operation CK X X EC X X 1* 0 Latch Operation (Spartan-XL) Both Legend: X 1 0 X X 1* 1* 0 SR X 1 0* 0* 0* 0* 0* D X X D X X D X

SR 0* 1*

Set or Reset value. Reset is default. Input is Low or unconnected (default value) Input is High or unconnected (default value)

CLB Signal Flow Control

SR

GND GSR SD D D Q Q

In addition to the H-LUT input control multiplexers (shown in box "A" of Figure 2, page 4) there are signal flow control multiplexers (shown in box "B" of Figure 2) which select the signals which drive the flip-flop inputs and the combinatorial CLB outputs (X and Y). Each flip-flop input is driven from a 4:1 multiplexer which selects among the three LUT outputs and DIN as the data source. Each combinatorial output is driven from a 2:1 multiplexer which selects between two of the LUT outputs. The X output can be driven from the F-LUT or H-LUT, the Y output from G-LUT or H-LUT. Control Signals
Multiplexer Controlled by Configuration Program
DS060_03_041901

CK RD EC Vcc

Figure 3: CLB Flip-Flop Functional Block Diagram

There are four signal control multiplexers on the input of the CLB. These multiplexers allow the internal CLB control signals (H1, DIN, SR, and EC in Figure 2 and Figure 4) to be driven from any of the four general control inputs (C1-C4 in Figure 4) into the CLB. Any of these inputs can drive any of the four internal control signals.

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Spartan and Spartan-XL FPGA Families Data Sheet

DIN

GSR

H1 D C1 C2 SR C3 EC C4 EC Vcc CK D

SD Q Q

RD

Multiplexer Controlled by Configuration Program Multiplexer Controlled by Configuration Program

DS060_04_081100 DS060_05_041901

Figure 4: CLB Control Signal Interface The four internal control signals are: EC: Enable Clock SR: Asynchronous Set/Reset or H function generator Input 0 DIN: Direct In or H function generator Input 2 H1: H function generator Input 1.

Figure 5: IOB Flip-Flop/Latch Functional Block Diagram

IOB Input Signal Path

The input signal to the IOB can be configured to either go directly to the routing channels (via I1 and I2 in Figure 6) or to the input register. The input register can be programmed as either an edge-triggered flip-flop or a level-sensitive latch. The functionality of this register is shown in Table 3, and a simplified block diagram of the register can be seen in Figure 5. Table 3: Input Register Functionality Mode Power-Up or GSR Flip-Flop 0 Latch Both Legend: X SR 0* 1* Dont care. Rising edge (clock not inverted). Set or Reset value. Reset is default. Input is Low or unconnected (default value) Input is High or unconnected (default value) 1 0 X CK X EC X 1* X 1* 1* 0 D X D X X D X Q SR D Q Q D Q

Input/Output Blocks (IOBs)

User-configurable input/output blocks (IOBs) provide the interface between external package pins and the internal logic. Each IOB controls one package pin and can be configured for input, output, or bidirectional signals. Figure 6 shows a simplified functional block diagram of the Spartan/XL FPGA IOB.

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Spartan and Spartan-XL FPGA Families Data Sheet using an option in the bitstream generation software. The Spartan family output levels are also configurable; the two global adjustments of input threshold and output level are independent. The inputs of Spartan devices can be driven by the outputs of any 3.3V device, if the Spartan family inputs are in TTL mode. Input and output thresholds are TTL on all configuration pins until the configuration has been loaded into the device and specifies how they are to be used. Spartan-XL family inputs are TTL compatible and 3.3V CMOS compatible. Supported sources for Spartan/XL device inputs are shown in Table 4. Spartan-XL family I/Os are fully 5V tolerant even though the VCC is 3.3V. This allows 5V signals to directly connect to the Spartan-XL family inputs without damage, as shown in Table 4. In addition, the 3.3V VCC can be applied before or after 5V signals are applied to the I/Os. This makes the Spartan-XL devices immune to power supply sequencing problems.

The register choice is made by placing the appropriate library symbol. For example, IFD is the basic input flip-flop (rising edge triggered), and ILD is the basic input latch (transparent-High). Variations with inverted clocks are also available. The clock signal inverter is also shown in Figure 5 on the CK line. The Spartan family IOB data input path has a one-tap delay element: either the delay is inserted (default), or it is not. The Spartan-XL family IOB data input path has a two-tap delay element, with choices of a full delay, a partial delay, or no delay. The added delay guarantees a zero hold time with respect to clocks routed through the global clock buffers. (See Global Nets and Buffers, page 12 for a description of the global clock buffers in the Spartan/XL families.) For a shorter input register setup time, with positive hold-time, attach a NODELAY attribute or property to the flip-flop.The output of the input register goes to the routing channels (via I1 and I2 in Figure 6). The I1 and I2 signals that exit the IOB can each carry either the direct or registered input signal. The 5V Spartan family input buffers can be globally configured for either TTL (1.2V) or CMOS (VCC/2) thresholds,
GTS T

D CK

Q OUTPUT DRIVER Programmable Slew Rate Programmable TTL/CMOS Drive (Spartan only) Package Pad INPUT BUFFER

OK EC

I1

I2 D IK EC CK EC Q

Delay Programmable Pull-Up/ Pull-Down Network

Multiplexer Controlled by Configuration Program

DS060_06_041901

Figure 6: Simplified Spartan/XL IOB Block Diagram

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Spartan and Spartan-XL FPGA Families Data Sheet Spartan-XL Family VCC Clamping

Table 4: Supported Sources for Spartan/XL Inputs Spartan Inputs Source

Any device, VCC = 3.3V, CMOS outputs Spartan family, VCC = 5V, TTL outputs Any device, VCC = 5V, TTL outputs (VOH 3.7V) Any device, VCC = 5V, CMOS outputs

Spartan-XL Inputs 3.3V CMOS

5V, TTL

5V, CMOS Unreliable Data

Spartan-XL FPGAs have an optional clamping diode connected from each I/O to VCC. When enabled they clamp ringing transients back to the 3.3V supply rail. This clamping action is required in 3.3V PCI applications. VCC clamping is a global option affecting all I/O pins. Spartan-XL devices are fully 5V TTL I/O compatible if VCC clamping is not enabled. With VCC clamping enabled, the Spartan-XL devices will begin to clamp input voltages to one diode voltage drop above VCC. If enabled, TTL I/O compatibility is maintained but full 5V I/O tolerance is sacrificed. The user may select either 5V tolerance (default) or 3.3V PCI compatibility. In both cases negative voltage is clamped to one diode voltage drop below ground. Spartan-XL devices are compatible with TTL, LVTTL, PCI 3V, PCI 5V and LVCMOS signalling. The various standards are illustrated in Table 5.

(default mode)

Table 5: I/O Standards Supported by Spartan-XL FPGAs Signaling Standard TTL LVTTL PCI5V PCI3V LVCMOS 3V VCC Clamping Not allowed OK Not allowed Required OK Output Drive 12/24 mA 12/24 mA 24 mA 12 mA 12/24 mA VIH MAX 5.5 3.6 5.5 3.6 3.6 VIH MIN 2.0 2.0 2.0 50% of VCC 50% of VCC VIL MAX 0.8 0.8 0.8 30% of VCC 30% of VCC VOH MIN 2.4 2.4 2.4 90% of VCC 90% of VCC VOL MAX 0.4 0.4 0.4 10% of VCC 10% of VCC

Additional Fast Capture Input Latch (Spartan-XL Family Only) The Spartan-XL family OB has an additional optional latch on the input. This latch is clocked by the clock used for the output flip-flop rather than the input clock. Therefore, two different clocks can be used to clock the two input storage elements. This additional latch allows the fast capture of input data, which is then synchronized to the internal clock by the IOB flip-flop or latch. To place the Fast Capture latch in a design, use one of the special library symbols, ILFFX or ILFLX. ILFFX is a transparent-Low Fast Capture latch followed by an active High input flip-flop. ILFLX is a transparent Low Fast Capture latch followed by a transparent High input latch. Any of the clock inputs can be inverted before driving the library element, and the inverter is absorbed into the IOB.

Table 6: Output Flip-Flop Functionality Mode Power-Up or GSR Flip-Flop Clock X X X 0 Legend: X SR 0* 1* Z Dont care Rising edge (clock not inverted). Set or Reset value. Reset is default. Input is Low or unconnected (default value) Input is High or unconnected (default value) 3-state Clock Enable X 0 1* X X T 0* 0* 0* 1 0* D X X D X X Q SR Q D Z Q

IOB Output Signal Path

Output signals can be optionally inverted within the IOB, and can pass directly to the output buffer or be stored in an edge-triggered flip-flop and then to the output buffer. The functionality of this flip-flop is shown in Table 6.

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Spartan and Spartan-XL FPGA Families Data Sheet By default, a 5V Spartan device output buffer pull-up structure is configured as a TTL-like totem-pole. The High driver is an n-channel pull-up transistor, pulling to a voltage one transistor threshold below VCC. Alternatively, the outputs can be globally configured as CMOS drivers, with additional p-channel pull-up transistors pulling to VCC. This option, applied using the bitstream generation software, applies to all outputs on the device. It is not individually programmable. All Spartan-XL device outputs are configured as CMOS drivers, therefore driving rail-to-rail. The Spartan-XL family outputs are individually programmable for 12 mA or 24 mA output drive. Any 5V Spartan device with its outputs configured in TTL mode can drive the inputs of any typical 3.3V device. Supported destinations for Spartan/XL device outputs are shown in Table 7. Three-State Register (Spartan-XL Family Only) Spartan-XL devices incorporate an optional register controlling the three-state enable in the IOBs. The use of the three-state control register can significantly improve output enable and disable time. Output Slew Rate The slew rate of each output buffer is, by default, reduced, to minimize power bus transients when switching non-critical signals. For critical signals, attach a FAST attribute or property to the output buffer or flip-flop. Spartan/XL devices have a feature called "Soft Start-up," designed to reduce ground bounce when all outputs are turned on simultaneously at the end of configuration. When the configuration process is finished and the device starts up, the first activation of the outputs is automatically slew-rate limited. Immediately following the initial activation of the I/O, the slew rate of the individual outputs is determined by the individual configuration option for each IOB. Pull-up and Pull-down Network Programmable pull-up and pull-down resistors are used for tying unused pins to VCC or Ground to minimize power consumption and reduce noise sensitivity. The configurable pull-up resistor is a p-channel transistor that pulls to VCC. The configurable pull-down resistor is an n-channel transistor that pulls to Ground. The value of these resistors is typically 20 K 100 K (See "Spartan Family DC Characteristics Over Operating Conditions" on page 43.).

Output Multiplexer/2-Input Function Generator (Spartan-XL Family Only) The output path in the Spartan-XL family IOB contains an additional multiplexer not available in the Spartan family IOB. The multiplexer can also be configured as a 2-input function generator, implementing a pass gate, AND gate, OR gate, or XOR gate, with 0, 1, or 2 inverted inputs. When configured as a multiplexer, this feature allows two output signals to time-share the same output pad, effectively doubling the number of device outputs without requiring a larger, more expensive package. The select input is the pin used for the output flip-flop clock, OK. When the multiplexer is configured as a 2-input function generator, logic can be implemented within the IOB itself. Combined with a Global buffer, this arrangement allows very high-speed gating of a single signal. For example, a wide decoder can be implemented in CLBs, and its output gated with a Read or Write Strobe driven by a global buffer. The user can specify that the IOB function generator be used by placing special library symbols beginning with the letter "O." For example, a 2-input AND gate in the IOB function generator is called OAND2. Use the symbol input pin labeled "F" for the signal on the critical path. This signal is placed on the OK pin the IOB input with the shortest delay to the function generator. Two examples are shown in Figure 7.
D0 D1

OMUX2
O

F OAND2

S0
DS060_07_081100

Figure 7: AND and MUX Symbols in Spartan-XL IOB Output Buffer An active High 3-state signal can be used to place the output buffer in a high-impedance state, implementing 3-state outputs or bidirectional I/O. Under configuration control, the output (O) and output 3-state (T) signals can be inverted. The polarity of these signals is independently configured for each IOB (see Figure 6, page 7). An output can be configured as open-drain (open-collector) by tying the 3-state pin (T) to the output signal, and the input pin (I) to Ground.

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Spartan and Spartan-XL FPGA Families Data Sheet This high value makes them unsuitable as wired-AND pull-up resistors. Table 7: Supported Destinations for Spartan/XL Outputs Spartan-XL Outputs Destination Any device, VCC = 3.3V, CMOS-threshold inputs Any device, VCC = 5V, TTL-threshold inputs Any device, VCC = 5V, CMOS-threshold inputs 3.3V, CMOS Spartan Outputs 5V, TTL 5V, CMOS Some(1)

falling-edge or rising-edge triggered flip-flops. The clock inputs for each IOB are independent. Common Clock Enables The input and output flip-flops in each IOB have a common clock enable input (see EC signal in Figure 5), which through configuration, can be activated individually for the input or output flip-flop, or both. This clock enable operates exactly like the EC signal on the Spartan/XL FPGA CLB. It cannot be inverted within the IOB.

Routing Channel Description

All internal routing channels are composed of metal segments with programmable switching points and switching matrices to implement the desired routing. A structured, hierarchical matrix of routing channels is provided to achieve efficient automated routing. This section describes the routing channels available in Spartan/XL devices. Figure 8 shows a general block diagram of the CLB routing channels. The implementation software automatically assigns the appropriate resources based on the density and timing requirements of the design. The following description of the routing channels is for information only and is simplified with some minor details omitted. For an exact interconnect description the designer should open a design in the FPGA Editor and review the actual connections in this tool. The routing channels will be discussed as follows; CLB routing channels which run along each row and column of the CLB array. IOB routing channels which form a ring (called a VersaRing) around the outside of the CLB array. It connects the I/O with the CLB routing channels. Global routing consists of dedicated networks primarily designed to distribute clocks throughout the device with minimum delay and skew. Global routing can also be used for other high-fanout signals.

Unreliable Data

Notes: 1. Only if destination device has 5V tolerant inputs.

After configuration, voltage levels of unused pads, bonded or unbonded, must be valid logic levels, to reduce noise sensitivity and avoid excess current. Therefore, by default, unused pads are configured with the internal pull-up resistor active. Alternatively, they can be individually configured with the pull-down resistor, or as a driven output, or to be driven by an external source. To activate the internal pull-up, attach the PULLUP library component to the net attached to the pad. To activate the internal pull-down, attach the PULLDOWN library component to the net attached to the pad. Set/Reset As with the CLB registers, the GSR signal can be used to set or clear the input and output registers, depending on the value of the INIT attribute or property. The two flip-flops can be individually configured to set or clear on reset and after configuration. Other than the global GSR net, no user-controlled set/reset signal is available to the I/O flip-flops (Figure 5). The choice of set or reset applies to both the initial state of the flip-flop and the response to the GSR pulse. Independent Clocks Separate clock signals are provided for the input (IK) and output (OK) flip-flops. The clock can be independently inverted for each flip-flop within the IOB, generating either

CLB Routing Channels

The routing channels around the CLB are derived from three types of interconnects; single-length, double-length, and longlines. At the intersection of each vertical and horizontal routing channel is a signal steering matrix called a Programmable Switch Matrix (PSM). Figure 8 shows the basic routing channel configuration showing single-length lines, double-length lines and longlines as well as the CLBs and PSMs. The CLB to routing channel interface is shown as well as how the PSMs interface at the channel intersections.

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DS060 (v1.8) June 26, 2008 Product Specification

Spartan and Spartan-XL FPGA Families Data Sheet

PSM

PSM

PSM

8 Singles 2 Doubles 3 Longs

CLB

CLB
3 Longs 2 Doubles

PSM

PSM

PSM

2 Doubles

3 Longs 8 Singles 3 Longs

2 Doubles
DS060_09_041901

Figure 8: Spartan/XL CLB Routing Channels and Interface Block Diagram CLB Interface A block diagram of the CLB interface signals is shown in Figure 9. The input signals to the CLB are distributed evenly on all four sides providing maximum routing flexibility. In general, the entire architecture is symmetrical and regular. It is well suited to established placement and routing algorithms. Inputs, outputs, and function generators can freely swap positions within a CLB to avoid routing congestion during the placement and routing operation. The exceptions are the clock (K) input and CIN/COUT signals. The K input is routed to dedicated global vertical lines as well as four single-length lines and is on the left side of the CLB. The CIN/COUT signals are routed through dedicated interconnects which do not interfere with the general routing structure. The output signals from the CLB are available to drive both vertical and horizontal channels.
YQ G4 C4 F4

Programmable Switch Matrices The horizontal and vertical single- and double-length lines intersect at a box called a programmable switch matrix (PSM). Each PSM consists of programmable pass transistors used to establish connections between the lines (see Figure 10). For example, a single-length signal entering on the right side of the switch matrix can be routed to a single-length line on the top, left, or bottom sides, or any combination thereof, if multiple branches are required. Similarly, a double-length signal can be routed to a double-length line on any or all of the other three edges of the programmable switch matrix. Single-Length Lines Single-length lines provide the greatest interconnect flexibility and offer fast routing between adjacent blocks. There are eight vertical and eight horizontal single-length lines associated with each CLB. These lines connect the switching matrices that are located in every row and column of CLBs. Single-length lines are connected by way of the programmable switch matrices, as shown in Figure 10. Routing connectivity is shown in Figure 8. Single-length lines incur a delay whenever they go through a PSM. Therefore, they are not suitable for routing signals for long distances. They are normally used to conduct signals within a localized area and to provide the branching for nets with fanout greater than one.

CIN COUT G1

Y G3

C3 C1 K F3 F1 X
Rev 1.1

CLB

XQ

C2

F2

G2

DS060_08_081100

Figure 9: CLB Interconnect Signals

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Spartan and Spartan-XL FPGA Families Data Sheet

Six Pass Transistors Per Switch Matrix Interconnect Point

DS060_10_081100

Figure 10: Programmable Switch Matrix Double-Length Lines The double-length lines consist of a grid of metal segments, each twice as long as the single-length lines: they run past two CLBs before entering a PSM. Double-length lines are grouped in pairs with the PSMs staggered, so that each line goes through a PSM at every other row or column of CLBs (see Figure 8). There are four vertical and four horizontal double-length lines associated with each CLB. These lines provide faster signal routing over intermediate distances, while retaining routing flexibility. Longlines Longlines form a grid of metal interconnect segments that run the entire length or width of the array. Longlines are intended for high fan-out, time-critical signal nets, or nets that are distributed over long distances. Each Spartan/XL device longline has a programmable splitter switch at its center. This switch can separate the line into two independent routing channels, each running half the width or height of the array. Routing connectivity of the longlines is shown in Figure 8. The longlines also interface to some 3-state buffers which is described later in 3-State Long Line Drivers, page 19.

I/O Routing
Spartan/XL devices have additional routing around the IOB ring. This routing is called a VersaRing. The VersaRing facilitates pin-swapping and redesign without affecting board layout. Included are eight double-length lines, and four longlines.

Global Nets and Buffers

The Spartan/XL devices have dedicated global networks. These networks are designed to distribute clocks and other high fanout control signals throughout the devices with minimal skew. Four vertical longlines in each CLB column are driven exclusively by special global buffers. These longlines are in addition to the vertical longlines used for standard interconnect. In the 5V Spartan devices, the four global lines can be driven by either of two types of global buffers; Primary Global buffers (BUFGP) or Secondary Global buffers (BUFGS). Each of these lines can be accessed by one particular Primary Global buffer, or by any of the Secondary Global buffers, as shown in Figure 11. In the 3V Spartan-XL devices, the four global lines can be driven by any of the eight Global Low-Skew Buffers (BUFGLS). The clock pins of every CLB and IOB can also be sourced from local interconnect.

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Spartan and Spartan-XL FPGA Families Data Sheet

IOB

IOB

IOB

IOB

locals

locals

locals

BUFGS PGCK1 SGCK1

locals

BUFGP SGCK4 PGCK4

4 BUFGP 4 IOB locals X4 locals IOB Any BUFGS One BUFGP per Global Line locals BUFGS CLB CLB locals CLB CLB

4 BUFGS locals 4

IOB Any BUFGS One BUFGP per Global Line locals BUFGP locals X4 locals IOB

X4

X4

PGCK2
locals locals locals

SGCK3 BUFGP
locals

SGCK2

PGCK3 BUFGS

IOB

IOB

IOB

IOB

ds060_11_080400

Figure 11: 5V Spartan Family Global Net Distribution The four Primary Global buffers offer the shortest delay and negligible skew. Four Secondary Global buffers have slightly longer delay and slightly more skew due to potentially heavier loading, but offer greater flexibility when used to drive non-clock CLB inputs. The eight Global Low-Skew buffers in the Spartan-XL devices combine short delay, negligible skew, and flexibility. The Primary Global buffers must be driven by the semi-dedicated pads (PGCK1-4). The Secondary Global buffers can be sourced by either semi-dedicated pads (SGCK1-4) or internal nets. Each corner of the device has one Primary buffer and one Secondary buffer. The Spartan-XL family has eight global low-skew buffers, two in each corner. All can be sourced by either semi-dedicated pads (GCK1-8) or internal nets. Using the library symbol called BUFG results in the software choosing the appropriate clock buffer, based on the timing requirements of the design. A global buffer should be specified for all timing-sensitive global signal distribution. To use a global buffer, place a BUFGP (primary buffer), BUFGS (secondary buffer), BUFGLS (Spartan-XL family global low-skew buffer), or BUFG (any buffer type) element in a schematic or in HDL code.

Advanced Features Description

Distributed RAM
Optional modes for each CLB allow the function generators (F-LUT and G-LUT) to be used as Random Access Memory (RAM). Read and write operations are significantly faster for this on-chip RAM than for off-chip implementations. This speed advantage is due to the relatively short signal propagation delays within the FPGA.

Memory Configuration Overview

There are two available memory configuration modes: single-port RAM and dual-port RAM. For both these modes, write operations are synchronous (edge-triggered), while read operations are asynchronous. In the single-port mode, a single CLB can be configured as either a 16 x 1, (16 x 1) x 2, or 32 x 1 RAM array. In the dual-port mode, a single CLB can be configured only as one 16 x 1 RAM array. The different CLB memory configurations are summarized in Table 8. Any of these possibilities can be individually programmed into a Spartan/XL FPGA CLB. Table 8: CLB Memory Configurations
Mode 16 x 1 (16 x 1) x 2 32 x 1

Single-Port Dual-Port

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Spartan and Spartan-XL FPGA Families Data Sheet The 16 x 1 single-port configuration contains a RAM array with 16 locations, each one-bit wide. One 4-bit address decoder determines the RAM location for write and read operations. There is one input for writing data and one output for reading data, all at the selected address. The (16 x 1) x 2 single-port configuration combines two 16 x 1 single-port configurations (each according to the preceding description). There is one data input, one data output and one address decoder for each array. These arrays can be addressed independently. The 32 x 1 single-port configuration contains a RAM array with 32 locations, each one-bit wide. There is one data input, one data output, and one 5-bit address decoder. The dual-port mode 16 x 1 configuration contains a RAM array with 16 locations, each one-bit wide. There are two 4-bit address decoders, one for each port. One port consists of an input for writing and an output for reading, all at a selected address. The other port consists of one output for reading from an independently selected address.

Table 9: Single-Port RAM Signals RAM Signal D0 or D1 A[3:0] A4 (32 x 1 only) WE WCLK SPO Function Data In Address Address Write Enable Clock Single Port Out (Data Out)
n

CLB Signal DIN or H1 F[4:1] or G[4:1] H1 SR K FOUT or GOUT

WRITE ROW SELECT

A[n-1:0]

The appropriate choice of RAM configuration mode for a given design should be based on timing and resource requirements, desired functionality, and the simplicity of the design process. Selection criteria include the following: Whereas the 32 x 1 single-port, the (16 x 1) x 2 single-port, and the 16 x 1 dual-port configurations each use one entire CLB, the 16 x 1 single-port configuration uses only one half of a CLB. Due to its simultaneous read/write capability, the dual-port RAM can transfer twice as much data as the single-port RAM, which permits only one data operation at any given time. CLB memory configuration options are selected by using the appropriate library symbol in the design entry. Single-Port Mode There are three CLB memory configurations for the single-port RAM: 16 x 1, (16 x 1) x 2, and 32 x 1, the functional organization of which is shown in Figure 12. The single-port RAM signals and the CLB signals (Figure 2, page 4) from which they are originally derived are shown in Table 9.

WE D0 or D1

INPUT REGISTER

16 x 1 32 x 1 RAM ARRAY

WRITE CONTROL

READ OUT

READ ROW SELECT

SPO
DS060_12_043010

WCLK

Notes: 1. The (16 x 1) x 2 configuration combines two 16 x 1 single-port RAMs, each with its own independent address bus and data input. The same WE and WCLK signals are connected to both RAMs. 2. n = 4 for the 16 x 1 and (16 x 1) x 2 configurations. n = 5 for the 32 x 1 configuration.

Figure 12: Logic Diagram for the Single-Port RAM Writing data to the single-port RAM is essentially the same as writing to a data register. It is an edge-triggered (synchronous) operation performed by applying an address to the A inputs and data to the D input during the active edge of WCLK while WE is High. The timing relationships are shown in Figure 13. The High logic level on WE enables the input data register for writing. The active edge of WCLK latches the address, input data, and WE signals. Then, an internal write pulse is generated that loads the data into the memory cell.

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Spartan and Spartan-XL FPGA Families Data Sheet inverted with respect to the sense of the flip-flop clock inputs. Consequently, within the same CLB, data at the RAM SPO line can be stored in a flip-flop with either the same or the inverse clock polarity used to write data to the RAM. The WE input is active High and cannot be inverted within the CLB.
TDSS TDHS

TWPS WCLK (K) TWSS WE TWHS

DATA IN TASS ADDRESS TILO TWOS OLD NEW

DS060_13_080400

TAHS

Allowing for settling time, the data on the SPO output reflects the contents of the RAM location currently addressed. When the address changes, following the asynchronous delay TILO, the data stored at the new address location will appear on SPO. If the data at a particular RAM address is overwritten, after the delay TWOS, the new data will appear on SPO. Dual-Port Mode In dual-port mode, the function generators (F-LUT and G-LUT) are used to create a 16 x 1 dual-port memory. Of the two data ports available, one permits read and write operations at the address specified by A[3:0] while the second provides only for read operations at the address specified independently by DPRA[3:0]. As a result, simultaneous read/write operations at different addresses (or even at the same address) are supported. The functional organization of the 16 x 1 dual-port RAM is shown in Figure 14. The dual-port RAM signals and the

TILO

DATA OUT

Figure 13: Data Write and Access Timing for RAM WCLK can be configured as active on either the rising edge (default) or the falling edge. While the WCLK input to the RAM accepts the same signal as the clock input to the associated CLBs flip-flops, the sense of this WCLK input can be
4

WRITE ROW SELECT

A[3:0]

4 INPUT REGISTER

16 x 1 RAM

WE D

READ ROW SELECT

WRITE CONTROL

READ OUT

SPO

WCLK

WRITE ROW SELECT

16 x 1 RAM

READ ROW SELECT

DPRA[3:0]

WRITE CONTROL

READ OUT

DPO

DS060_14_043001

Figure 14: Logic Diagram for the Dual-Port RAM

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Spartan and Spartan-XL FPGA Families Data Sheet CLB signals from which they are originally derived are shown in Table 10. Table 10: Dual-Port RAM Signals RAM Signal D A[3:0] Function Data In Read Address for Single-Port. Write Address for Single-Port and Dual-Port. DPRA[3:0] WE WCLK SPO DPO Read Address for Dual-Port Write Enable Clock Single Port Out (addressed by A[3:0]) Dual Port Out (addressed by DPRA[3:0]) G[4:1] CLB Signal DIN F[4:1]

attached to the RAM or ROM symbol, as described in the library guide. If not defined, all RAM contents are initialized to zeros, by default. RAM initialization occurs only during device configuration. The RAM content is not affected by GSR. More Information on Using RAM Inside CLBs Three application notes are available from Xilinx that discuss synchronous (edge-triggered) RAM: "Xilinx Edge-Triggered and Dual-Port RAM Capability," "Implementing FIFOs in Xilinx RAM," and "Synchronous and Asynchronous FIFO Designs." All three application notes apply to both the Spartan and the Spartan-XL families.

Fast Carry Logic

SR K FOUT GOUT Each CLB F-LUT and G-LUT contains dedicated arithmetic logic for the fast generation of carry and borrow signals. This extra output is passed on to the function generator in the adjacent CLB. The carry chain is independent of normal routing resources. (See Figure 15.) Dedicated fast carry logic greatly increases the efficiency and performance of adders, subtractors, accumulators, comparators and counters. It also opens the door to many new applications involving arithmetic operation, where the previous generations of FPGAs were not fast enough or too inefficient. High-speed address offset calculations in microprocessor or graphics systems, and high-speed addition in digital signal processing are two typical applications. The two 4-input function generators can be configured as a 2-bit adder with built-in hidden carry that can be expanded to any length. This dedicated carry circuitry is so fast and efficient that conventional speed-up methods like carry generate/propagate are meaningless even at the 16-bit level, and of marginal benefit at the 32-bit level. This fast carry logic is one of the more significant features of the Spartan

The RAM16X1D primitive used to instantiate the dual-port RAM consists of an upper and a lower 16 x 1 memory array. The address port labeled A[3:0] supplies both the read and write addresses for the lower memory array, which behaves the same as the 16 x 1 single-port RAM array described previously. Single Port Out (SPO) serves as the data output for the lower memory. Therefore, SPO reflects the data at address A[3:0]. The other address port, labeled DPRA[3:0] for Dual Port Read Address, supplies the read address for the upper memory. The write address for this memory, however, comes from the address A[3:0]. Dual Port Out (DPO) serves as the data output for the upper memory. Therefore, DPO reflects the data at address DPRA[3:0]. By using A[3:0] for the write address and DPRA[3:0] for the read address, and reading only the DPO output, a FIFO that can read and write simultaneously is easily generated. The simultaneous read/write capability possible with the dual-port RAM can provide twice the effective data throughput of a single-port RAM alternating read and write operations. The timing relationships for the dual-port RAM mode are shown in Figure 13. Note that write operations to RAM are synchronous (edge-triggered); however, data access is asynchronous. Initializing RAM at FPGA Configuration Both RAM and ROM implementations in the Spartan/XL families are initialized during device configuration. The initial contents are defined via an INIT attribute or property
16

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

DS060_15_081100

Figure 15: Available Spartan/XL Carry Propagation Paths

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Spartan and Spartan-XL FPGA Families Data Sheet and control inputs with the function generators. The carry outputs connect to the function generators, where they are combined with the operands to form the sums. Figure 17, page 19 shows the details of the Spartan/XL FPGA carry logic. This diagram shows the contents of the box labeled "CARRY LOGIC" in Figure 16. The fast carry logic can be accessed by placing special library symbols, or by using Xilinx Relationally Placed Macros (RPMs) that already include these symbols.

and Spartan-XL families, speeding up arithmetic and counting functions. The carry chain in 5V Spartan devices can run either up or down. At the top and bottom of the columns where there are no CLBs above and below, the carry is propagated to the right. The default is always to propagate up the column, as shown in the figures. The carry chain in Spartan-XL devices can only run up the column, providing even higher speed. Figure 16, page 18 shows a Spartan/XL FPGA CLB with dedicated fast carry logic. The carry logic shares operand

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Spartan and Spartan-XL FPGA Families Data Sheet

CARRY LOGIC

C OUT

D IN

G H Y

G CARRY

G4

G3 G G2 D IN H G F G1 EC C OUT0 H1 H S/R D Q YQ

D IN F CARRY H G F S/R D Q XQ

F4

EC

F3 F F2 F1 H X F

C IN

S/R

EC
DS060_16_080400

Figure 16: Fast Carry Logic in Spartan/XL CLB

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Spartan and Spartan-XL FPGA Families Data Sheet

C OUT G1 M 1 0 I G4 G3 C OUT0 M F2 1 F1 M M F3 M 0 1 3 1 0 M CIN

DS060_17_080400

M 1 G2

M 0 1 F4

TO FUNCTION GENERATORS

Figure 17: Detail of Spartan/XL Dedicated Carry Logic

3-State Long Line Drivers

A pair of 3-state buffers is associated with each CLB in the array. These 3-state buffers (BUFT) can be used to drive signals onto the nearest horizontal longlines above and below the CLB. They can therefore be used to implement multiplexed or bidirectional buses on the horizontal longlines, saving logic resources. There is a weak keeper at each end of these two horizontal longlines. This circuit prevents undefined floating levels. However, it is overridden by any driver. The buffer enable is an active High 3-state (i.e., an active Low enable), as shown in Table 11.

Three-State Buffer Example

Figure 18 shows how to use the 3-state buffers to implement a multiplexer. The selection is accomplished by the buffer 3-state signal. Pay particular attention to the polarity of the T pin when using these buffers in a design. Active High 3-state (T) is identical to an active Low output enable, as shown in Table 11. Table 11: Three-State Buffer Functionality IN X IN T 1 0 OUT Z IN

~100 k

Z = (DA A) + (DB B) + (DC C) + (DN N)

DA A "Weak Keeper" BUFT

DB B BUFT

DC C BUFT

DN N BUFT

DS060_18_080400

Figure 18: 3-state Buffers Implement a Multiplexer

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Spartan and Spartan-XL FPGA Families Data Sheet

On-Chip Oscillator
Spartan/XL devices include an internal oscillator. This oscillator is used to clock the power-on time-out, for configuration memory clearing, and as the source of CCLK in Master configuration mode. The oscillator runs at a nominal 8 MHz frequency that varies with process, VCC, and temperature. The output frequency falls between 4 MHz and 10 MHz. The oscillator output is optionally available after configuration. Any two of four resynchronized taps of a built-in divider are also available. These taps are at the fourth, ninth, fourteenth and nineteenth bits of the divider. Therefore, if the primary oscillator output is running at the nominal 8 MHz, the user has access to an 8-MHz clock, plus any two of 500 kHz, 16 kHz, 490 Hz and 15 Hz. These frequencies can vary by as much as -50% or +25%. These signals can be accessed by placing the OSC4 library element in a schematic or in HDL code. The oscillator is automatically disabled after configuration if the OSC4 symbol is not used in the design.

connected to GTS. A specific pin location can be assigned to this input using a LOC attribute or property, just as with any other user-programmable pad. An inverter can optionally be inserted after the input buffer to invert the sense of the Global 3-state signal. Alternatively, GTS can be driven from any internal node.

STARTUP
PAD IBUF GSR GTS CLK Q2 Q3 Q1, Q4 DONEIN
DS060_19_080400

Figure 19: Symbols for Global Set/Reset

Boundary Scan
The "bed of nails" has been the traditional method of testing electronic assemblies. This approach has become less appropriate, due to closer pin spacing and more sophisticated assembly methods like surface-mount technology and multi-layer boards. The IEEE Boundary Scan Standard 1149.1 was developed to facilitate board-level testing of electronic assemblies. Design and test engineers can embed a standard test logic structure in their device to achieve high fault coverage for I/O and internal logic. This structure is easily implemented with a four-pin interface on any boundary scan compatible device. IEEE 1149.1-compatible devices may be serial daisy-chained together, connected in parallel, or a combination of the two. The Spartan and Spartan-XL families implement IEEE 1149.1-compatible BYPASS, PRELOAD/SAMPLE and EXTEST boundary scan instructions. When the boundary scan configuration option is selected, three normal user I/O pins become dedicated inputs for these functions. Another user output pin becomes the dedicated boundary scan output. The details of how to enable this circuitry are covered later in this section. By exercising these input signals, the user can serially load commands and data into these devices to control the driving of their outputs and to examine their inputs. This method is an improvement over bed-of-nails testing. It avoids the need to over-drive device outputs, and it reduces the user interface to four pins. An optional fifth pin, a reset for the control logic, is described in the standard but is not implemented in the Spartan/XL devices. The dedicated on-chip logic implementing the IEEE 1149.1 functions includes a 16-state machine, an instruction register and a number of data registers. The functional details can be found in the IEEE 1149.1 specification and are also discussed in the Xilinx application note: "Boundary Scan in FPGA Devices."

Global Signals: GSR and GTS

Global Set/Reset
A separate Global Set/Reset line, as shown in Figure 3, page 5 for the CLB and Figure 5, page 6 for the IOB, sets or clears each flip-flop during power-up, reconfiguration, or when a dedicated Reset net is driven active. This global net (GSR) does not compete with other routing resources; it uses a dedicated distribution network. Each flip-flop is configured as either globally set or reset in the same way that the local set/reset (SR) is specified. Therefore, if a flip-flop is set by SR, it is also set by GSR. Similarly, if in reset mode, it is reset by both SR and GSR. GSR can be driven from any user-programmable pin as a global reset input. To use this global net, place an input pad and input buffer in the schematic or HDL code, driving the GSR pin of the STARTUP symbol. (See Figure 19.) A specific pin location can be assigned to this input using a LOC attribute or property, just as with any other user-programmable pad. An inverter can optionally be inserted after the input buffer to invert the sense of the GSR signal. Alternatively, GSR can be driven from any internal node.

Global 3-State
A separate Global 3-state line (GTS) as shown in Figure 6, page 7 forces all FPGA outputs to the high-impedance state, unless boundary scan is enabled and is executing an EXTEST instruction. GTS does not compete with other routing resources; it uses a dedicated distribution network. GTS can be driven from any user-programmable pin as a global 3-state input. To use this global net, place an input pad and input buffer in the schematic or HDL code, driving the GTS pin of the STARTUP symbol. This is similar to what is shown in Figure 19 for GSR except the IBUF would be

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Spartan and Spartan-XL FPGA Families Data Sheet The other standard data register is the single flip-flop BYPASS register. It synchronizes data being passed through the FPGA to the next downstream boundary scan device. The FPGA provides two additional data registers that can be specified using the BSCAN macro. The FPGA provides two user pins (BSCAN.SEL1 and BSCAN.SEL2) which are the decodes of two user instructions. For these instructions, two corresponding pins (BSCAN.TDO1 and BSCAN.TDO2) allow user scan data to be shifted out on TDO. The data register clock (BSCAN.DRCK) is available for control of test logic which the user may wish to implement with CLBs. The NAND of TCK and RUN-TEST-IDLE is also provided (BSCAN.IDLE).

Figure 20 is a diagram of the Spartan/XL FPGA boundary scan logic. It includes three bits of Data Register per IOB, the IEEE 1149.1 Test Access Port controller, and the Instruction Register with decodes. Spartan/XL devices can also be configured through the boundary scan logic. See Configuration Through the Boundary Scan Pins, page 37.

Data Registers
The primary data register is the boundary scan register. For each IOB pin in the FPGA, bonded or not, it includes three bits for In, Out and 3-state Control. Non-IOB pins have appropriate partial bit population for In or Out only. PROGRAM, CCLK and DONE are not included in the boundary scan register. Each EXTEST CAPTURE-DR state captures all In, Out, and 3-state pins. The data register also includes the following non-pin bits: TDO.T, and TDO.O, which are always bits 0 and 1 of the data register, respectively, and BSCANT.UPD, which is always the last bit of the data register. These three boundary scan bits are special-purpose Xilinx test signals.

Instruction Set
The Spartan/XL FPGA boundary scan instruction set also includes instructions to configure the device and read back the configuration data. The instruction set is coded as shown in Table 12.

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Spartan and Spartan-XL FPGA Families Data Sheet

DATA IN IOB.T 1 0 IOB IOB IOB IOB IOB D Q D sd Q 0 1

LE

IOB

IOB

1 0

sd D Q D Q

IOB

IOB LE

IOB

IOB IOB.I 1 0 1 sd D Q D Q

IOB

IOB

IOB

IOB

IOB

IOB

LE 1 IOB.Q IOB.T 0

IOB

BYPASS REGISTER INSTRUCTION REGISTER

IOB

TDI

M TDO U X

0 1 0 D Q D sd Q 1

LE

1 0 D Q D

sd Q

LE

1 IOB.I 0

DATAOUT SHIFT/ CLOCK DATA CAPTURE REGISTER

UPDATE

EXTEST

DS060_20_080400

Figure 20: Spartan/XL Boundary Scan Logic

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Spartan and Spartan-XL FPGA Families Data Sheet

Table 12: Boundary Scan Instructions

Instruction I2 0 0 0 0 1 1 1 I1 0 0 1 1 0 0 1 I0 0 1 0 1 0 1 0 Test Selected EXTEST SAMPLE/ PRELOAD USER 1 USER 2 READBACK CONFIGURE IDCODE (Spartan-XL only) BYPASS TDO Source DR DR BSCAN. TDO1 BSCAN. TDO2 Readback Data DOUT IDCODE Register Bypass Register I/O Data Source DR Pin/Logic User Logic

Bit 0 ( TDO end) Bit 1 Bit 2

TDO.T TDO.O Top-edge IOBs (Right to Left) Left-edge IOBs (Top to Bottom)

MODE.I
User Logic

Bottom-edge IOBs (Left to Right)

Pin/Logic

Right-edge IOBs (Bottom to Top)

Disabled DS060_21_080400

(TDI end)

BSCANT.UPD

Figure 21: Boundary Scan Bit Sequence

-

Bit Sequence
The bit sequence within each IOB is: In, Out, 3-state. The input-only pins contribute only the In bit to the boundary scan I/O data register, while the output-only pins contributes all three bits. The first two bits in the I/O data register are TDO.T and TDO.O, which can be used for the capture of internal signals. The final bit is BSCANT.UPD, which can be used to drive an internal net. These locations are primarily used by Xilinx for internal testing. From a cavity-up view of the chip (as shown in the FPGA Editor), starting in the upper right chip corner, the boundary scan data-register bits are ordered as shown in Figure 21. The device-specific pinout tables for the Spartan/XL devices include the boundary scan locations for each IOB pin.

BSDL (Boundary Scan Description Language) files for Spartan/XL devices are available on the Xilinx website in the File Download area. Note that the 5V Spartan devices and 3V Spartan-XL devices have different BSDL files.

Including Boundary Scan in a Design

If boundary scan is only to be used during configuration, no special elements need be included in the schematic or HDL code. In this case, the special boundary scan pins TDI, TMS, TCK and TDO can be used for user functions after configuration. To indicate that boundary scan remain enabled after configuration, place the BSCAN library symbol and connect the TDI, TMS, TCK and TDO pad symbols to the appropriate pins, as shown in Figure 22.
Optional IBUF BSCAN TDI TMS TCK From User Logic
TDI TMS TCK TDO1 TDO2 TDO DRCK IDLE SEL1 SEL2

To User Logic

TDO

To User Logic

DS060_22_080400

Figure 22: Boundary Scan Example

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Spartan and Spartan-XL FPGA Families Data Sheet Even if the boundary scan symbol is used in a design, the input pins TMS, TCK, and TDI can still be used as inputs to be routed to internal logic. Care must be taken not to force the chip into an undesired boundary scan state by inadvertently applying boundary scan input patterns to these pins. The simplest way to prevent this is to keep TMS High, and then apply whatever signal is desired to TDI and TCK. Avoiding Inadvertent Boundary Scan If TMS or TCK is used as user I/O, care must be taken to ensure that at least one of these pins is held constant during configuration. In some applications, a situation may occur where TMS or TCK is driven during configuration. This may cause the device to go into boundary scan mode and disrupt the configuration process. To prevent activation of boundary scan during configuration, do either of the following: TMS: Tie High to put the Test Access Port controller in a benign RESET state. TCK: Tie High or Lowdo not toggle this clock input.

Configuration State: The configuration state is available to JTAG controllers. Configuration Disable: The JTAG port can be prevented from configuring the FPGA. TCK Startup: TCK can now be used to clock the start-up block in addition to other user clocks. CCLK Holdoff: Changed the requirement for Boundary Scan Configure or EXTEST to be issued prior to the release of INIT pin and CCLK cycling. Reissue Configure: The Boundary Scan Configure can be reissued to recover from an unfinished attempt to configure the device. Bypass FF: Bypass FF and IOB is modified to provide DRCLOCK only during BYPASS for the bypass flip-flop, and during EXTEST or SAMPLE/PRELOAD for the IOB register.

Power-Down (Spartan-XL Family Only)

All Spartan/XL devices use a combination of efficient segmented routing and advanced process technology to provide low power consumption under all conditions. The 3.3V Spartan-XL family adds a dedicated active Low power-down pin (PWRDWN) to reduce supply current to 100 A typical. The PWRDWN pin takes advantage of one of the unused No Connect locations on the 5V Spartan device. The user must de-select the "5V Tolerant I/Os" option in the Configuration Options to achieve the specified Power Down current. The PWRDWN pin has a default internal pull-up resistor, allowing it to be left unconnected if unused. VCC must continue to be supplied during Power-down, and configuration data is maintained. When the PWRDWN pin is pulled Low, the input and output buffers are disabled. The inputs are internally forced to a logic Low level, including the MODE pins, DONE, CCLK, and TDO, and all internal pull-up resistors are turned off. The PROGRAM pin is not affected by Power Down. The GSR net is asserted during Power Down, initializing all the flip-flops to their start-up state. PWRDWN has a minimum pulse width of 50 ns (Figure 23). On entering the Power-down state, the inputs will be disabled and the flip-flops set/reset, and then the outputs are disabled about 10 ns later. The user may prefer to assert the GTS or GSR signals before PWRDWN to affect the order of events. When the PWRDWN signal is returned High, the inputs will be enabled first, followed immediately by the release of the GSR signal initializing the flip-flops. About 10 ns later, the outputs will be enabled. Allow 50 ns after the release of PWRDWN before using the device.

For more information regarding boundary scan, refer to the Xilinx Application Note, "Boundary Scan in FPGA Devices. " Boundary Scan Enhancements (Spartan-XL Family Only) Spartan-XL devices have improved boundary scan functionality and performance in the following areas: IDCODE: The IDCODE register is supported. By using the IDCODE, the device connected to the JTAG port can be determined. The use of the IDCODE enables selective configuration dependent on the FPGA found. The IDCODE register has the following binary format: vvvv:ffff:fffa:aaaa:aaaa:cccc:cccc:ccc1 where c = the company code (49h for Xilinx) a = the array dimension in CLBs (ranges from 0Ah for XCS05XL to 1Ch for XCS40XL) f = the family code (02h for Spartan-XL family) v = the die version number Table 13: IDCODEs Assigned to Spartan-XL FPGAs FPGA XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL IDCODE 0040A093h 0040E093h 00414093h 00418093h 0041C093h

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Spartan and Spartan-XL FPGA Families Data Sheet

TPWDW PWRDWN

50 ns Power Down Mode Outputs

50 ns

Description Power Down Time Power Down Pulse Width

Symbol TPWD TPWDW

Min 50 ns 50 ns
DS060_23_041901

Figure 23: PWRDWN Pulse Timing Power-down retains the configuration, but loses all data stored in the device flip-flops. All inputs are interpreted as Low, but the internal combinatorial logic is fully functional. Make sure that the combination of all inputs Low and all flip-flops set or reset in your design will not generate internal oscillations, or create permanent bus contention by activating internal bus drivers with conflicting data onto the same long line. During configuration, the PWRDWN pin must be High. If the Power Down state is entered before or during configuration, the device will restart configuration once the PWRDWN signal is removed. Note that the configuration pins are affected by Power Down and may not reflect their normal function. If there is an external pull-up resistor on the DONE pin, it will be High during Power Down even if the device is not yet configured. Similarly, if PWRDWN is asserted before configuration is completed, the INIT pin will not indicate status information. Note that the PWRDWN pin is not part of the Boundary Scan chain. Therefore, the Spartan-XL family has a separate set of BSDL files than the 5V Spartan family. Boundary scan logic is not usable during Power Down. configuration bit defines the state of a static memory cell that controls either a function look-up table bit, a multiplexer input, or an interconnect pass transistor. The Xilinx development system translates the design into a netlist file. It automatically partitions, places and routes the logic and generates the configuration data in PROM format.

Configuration Mode Control

5V Spartan devices have two configuration modes. MODE = 1 sets Slave Serial mode MODE = 0 sets Master Serial mode M1/M0 = 11 sets Slave Serial mode M1/M0 = 10 sets Master Serial mode M1/M0 = 0X sets Express mode

3V Spartan-XL devices have three configuration modes.

In addition to these modes, the device can be configured through the Boundary Scan logic (See "Configuration Through the Boundary Scan Pins" on page 37.). The Mode pins are sampled prior to starting configuration to determine the configuration mode. After configuration, these pin are unused. The Mode pins have a weak pull-up resistor turned on during configuration. With the Mode pins High, Slave Serial mode is selected, which is the most popular configuration mode. Therefore, for the most common configuration mode, the Mode pins can be left unconnected. If the Master Serial mode is desired, the MODE/M0 pin should be connected directly to GND, or through a pull-down resistor of 1 K or less.

Configuration and Test

Configuration is the process of loading design-specific programming data into one or more FPGAs to define the functional operation of the internal blocks and their interconnections. This is somewhat like loading the command registers of a programmable peripheral chip. Spartan/XL devices use several hundred bits of configuration data per CLB and its associated interconnects. Each

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25

Spartan and Spartan-XL FPGA Families Data Sheet During configuration, some of the I/O pins are used temporarily for the configuration process. All pins used during configuration are shown in Table 14 and Table 15. Table 14: Pin Functions During Configuration (Spartan Family Only) Configuration Mode (MODE Pin) Slave Serial (High) MODE (I) HDC (High) LDC (Low) INIT DONE PROGRAM (I) CCLK (I) DIN (I) DOUT TDI TCK TMS TDO Master Serial (Low) MODE (I) HDC (High) LDC (Low) INIT DONE PROGRAM (I) CCLK (O) DIN (I) DOUT TDI TCK TMS TDO User Operation MODE I/O I/O I/O DONE PROGRAM CCLK (I) I/O SGCK4-I/O TDI-I/O TCK-I/O TMS-I/O TDO-(O) ALL OTHERS
Notes: 1. A shaded table cell represents the internal pull-up used before and during configuration. 2. (I) represents an input; (O) represents an output. 3. INIT is an open-drain output during configuration.

Table 15: Pin Functions During Configuration (Spartan-XL Family Only)

CONFIGURATION MODE <M1:M0>

Slave Serial [1:1] M1 (High) (I) M0 (High) (I) HDC (High) LDC (Low) INIT DONE PROGRAM (I) CCLK (I)

Master Serial [1:0] M1 (High) (I) M0 (Low) (I) HDC (High) LDC (Low) INIT DONE PROGRAM (I) CCLK (O)

Express [0:X] M1(Low) (I) M0 (I) HDC (High) LDC (Low) INIT DONE PROGRAM (I) CCLK (I) DATA 7 (I) DATA 6 (I) DATA 5 (I) DATA 4 (I) DATA 3 (I) DATA 2 (I) DATA 1 (I)

User Operation M1 M0 I/O I/O I/O DONE PROGRAM CCLK (I) I/O I/O I/O I/O I/O I/O I/O I/O GCK6-I/O TDI-I/O TCK-I/O TMS-I/O TDO-(O) I/O ALL OTHERS

DIN (I) DOUT TDI TCK TMS TDO

DIN (I) DOUT TDI TCK TMS TDO

DATA 0 (I) DOUT TDI TCK TMS TDO CS1

Notes: 1. A shaded table cell represents the internal pull-up used before and during configuration. 2. (I) represents an input; (O) represents an output. 3. INIT is an open-drain output during configuration.

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DS060 (v1.8) June 26, 2008 Product Specification

Spartan and Spartan-XL FPGA Families Data Sheet falling CCLK edge, and the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge. See the timing diagram in Figure 24. In the bitstream generation software, the user can specify Fast Configuration Rate, which, starting several bits into the first frame, increases the CCLK frequency by a factor of eight. For actual timing values please refer to the specification section. Be sure that the serial PROM and slaves are fast enough to support this data rate. Earlier families such as the XC3000 series do not support the Fast Configuration Rate option. The SPROM CE input can be driven from either LDC or DONE. Using LDC avoids potential contention on the DIN pin, if this pin is configured as user I/O, but LDC is then restricted to be a permanently High user output after configuration. Using DONE can also avoid contention on DIN, provided the Early DONE option is invoked. Figure 25 shows a full master/slave system. The leftmost device is in Master Serial mode, all other devices in the chain are in Slave Serial mode.

Master Serial Mode

The Master serial mode uses an internal oscillator to generate a Configuration Clock (CCLK) for driving potential slave devices and the Xilinx serial-configuration PROM (SPROM). The CCLK speed is selectable as either 1 MHz (default) or 8 MHz. Configuration always starts at the default slow frequency, then can switch to the higher frequency during the first frame. Frequency tolerance is 50% to +25%. In Master Serial mode, the CCLK output of the device drives a Xilinx SPROM that feeds the FPGA DIN input. Each rising edge of the CCLK output increments the Serial PROM internal address counter. The next data bit is put on the SPROM data output, connected to the FPGA DIN pin. The FPGA accepts this data on the subsequent rising CCLK edge. When used in a daisy-chain configuration the Master Serial FPGA is placed as the first device in the chain and is referred to as the lead FPGA. The lead FPGA presents the preamble data, and all data that overflows the lead device, on its DOUT pin. There is an internal pipeline delay of 1.5 CCLK periods, which means that DOUT changes on the
CCLK (Output) TCKDS TDSCK Serial Data In n

n+1

n+2

Serial DOUT (Output)

n3

n2

n1

n
DS060_24_080400

Symbol CCLK TDSCK TCKDS DIN setup DIN hold

Description

Min 20 0

Units ns ns

Notes: 1. At power-up, VCC must rise from 2.0V to VCC min in less than 25 ms, otherwise delay configuration by pulling PROGRAM Low until VCC is valid. 2. Master Serial mode timing is based on testing in slave mode.

Figure 24: Master Serial Mode Programming Switching Characteristics

Slave Serial Mode

In Slave Serial mode, the FPGA receives serial configuration data on the rising edge of CCLK and, after loading its configuration, passes additional data out, resynchronized on the next falling edge of CCLK. In this mode, an external signal drives the CCLK input of the FPGA (most often from a Master Serial device). The serial configuration bitstream must be available at the DIN input of the lead FPGA a short setup time before each rising CCLK edge.

The lead FPGA then presents the preamble dataand all data that overflows the lead deviceon its DOUT pin. There is an internal delay of 0.5 CCLK periods, which means that DOUT changes on the falling CCLK edge, and the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge. Figure 25 shows a full master/slave system. A Spartan/XL device in Slave Serial mode should be connected as shown in the third device from the left.

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Spartan and Spartan-XL FPGA Families Data Sheet Slave Serial is the default mode if the Mode pins are left unconnected, as they have weak pull-up resistors during configuration. Multiple slave devices with identical configurations can be wired with parallel DIN inputs. In this way, multiple devices can be configured simultaneously.

and is captured by each FPGA when it recognizes the 0010 preamble. Following the length-count data, each FPGA outputs a High on DOUT until it has received its required number of data frames. After an FPGA has received its configuration data, it passes on any additional frame start bits and configuration data on DOUT. When the total number of configuration clocks applied after memory initialization equals the value of the 24-bit length count, the FPGAs begin the start-up sequence and become operational together. FPGA I/O are normally released two CCLK cycles after the last configuration bit is received. The daisy-chained bitstream is not simply a concatenation of the individual bitstreams. The PROM File Formatter must be used to combine the bitstreams for a daisy-chained configuration.

Serial Daisy Chain

Multiple devices with different configurations can be connected together in a "daisy chain," and a single combined bitstream used to configure the chain of slave devices. To configure a daisy chain of devices, wire the CCLK pins of all devices in parallel, as shown in Figure 25. Connect the DOUT of each device to the DIN of the next. The lead or master FPGA and following slaves each passes resynchronized configuration data coming from a single source. The header data, including the length count, is passed through

Note: M2, M1, M0 can be shorted to VCC if not used as I/O

VCC
3.3K 3.3K 3.3K

MODE DOUT

N/C

MODE DIN DOUT

M0 M1 M2 DIN CCLK DOUT

Spartan Master Serial

CCLK DIN PROGRAM DONE LDC INIT

VCC
3.3K

CCLK

Xilinx SPROM
CLK DATA VPP

+5V

Spartan Slave

FPGA Slave

CEO CE RESET/OE (Low Reset Option Used)

PROGRAM DONE

INIT

RESET D/P

INIT

PROGRAM
DS060_25_061301

Figure 25: Master/Slave Serial Mode Circuit Diagram

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Spartan and Spartan-XL FPGA Families Data Sheet

DIN TDCC CCLK

Bit n TCCD

Bit n + 1 TCCL

TCCH DOUT (Output) Bit n 1

TCCO Bit n
DS060_26_080400

Symbol TDCC TCCD TCCO TCCH TCCL FCC CCLK

Description DIN setup DIN hold DIN to DOUT High time Low time Frequency

Min 20 0 40 40 -

Max 30 12.5

Units ns ns ns ns ns MHz

Notes: 1. Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High.

Figure 26: Slave Serial Mode Programming Switching Characteristics

Express Mode (Spartan-XL Family Only)

Express mode is similar to Slave Serial mode, except that data is processed one byte per CCLK cycle instead of one bit per CCLK cycle. An external source is used to drive CCLK, while byte-wide data is loaded directly into the configuration data shift registers (Figure 27). A CCLK frequency of 1 MHz is equivalent to a 8 MHz serial rate, because eight bits of configuration data are loaded per CCLK cycle. Express mode does not support CRC error checking, but does support constant-field error checking. A length count is not used in Express mode. Express mode must be specified as an option to the development system. The Express mode bitstream is not compatible with the other configuration modes (see Table 16, page 32.) Express mode is selected by a <0X> on the Mode pins (M1, M0). The first byte of parallel configuration data must be available at the D inputs of the FPGA a short setup time before the second rising CCLK edge. Subsequent data bytes are clocked in on each consecutive rising CCLK edge (Figure 28).

are in Express mode. Concatenated bitstreams are used to configure the chain of Express mode devices so that each device receives a separate header. CCLK pins are tied together and D0-D7 pins are tied together for all devices along the chain. A status signal is passed from DOUT to CS1 of successive devices along the chain. Frame data is accepted only when CS1 is High and the devices configuration memory is not already full. The lead device in the chain has its CS1 input tied High (or floating, since there is an internal pull-up). The status pin DOUT is pulled Low after the header is received, and remains Low until the devices configuration memory is full. DOUT is then pulled High to signal the next device in the chain to accept the next header and configuration data on the D0-D7 bus. The DONE pins of all devices in the chain should be tied together, with one or more active internal pull-ups. If a large number of devices are included in the chain, deactivate some of the internal pull-ups, since the Low-driving DONE pin of the last device in the chain must sink the current from all pull-ups in the chain. The DONE pull-up is activated by default. It can be deactivated using a development system option. The requirement that all DONE pins in a daisy chain be wired together applies only to Express mode, and only if all devices in the chain are to become active simultaneously. All Spartan-XL devices in Express mode are synchronized
29

Pseudo Daisy Chain

Multiple devices with different configurations can be configured in a pseudo daisy chain provided that all of the devices

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Spartan and Spartan-XL FPGA Families Data Sheet to the DONE pin. User I/Os for each device become active after the DONE pin for that device goes High. (The exact timing is determined by development system options.) Since the DONE pin is open-drain and does not drive a High value, tying the DONE pins of all devices together prevents all devices in the chain from going High until the last device
V CC 8 M0 CS1 DATA BUS 8 VCC 3.3K PROGRAM INIT PROGRAM INIT CCLK DONE D0-D7 M1 DOUT 8 M0 CS1 D0-D7 M1 DOUT To Additional Optional Daisy-Chained Devices

in the chain has completed its configuration cycle. If the DONE pin of a device is left unconnected, the device becomes active as soon as that device has been configured. Only devices supporting Express mode can be used to form an Express mode daisy chain.

Spartan-XL

Optional Daisy-Chained Spartan-XL

PROGRAM INIT CCLK DONE

CCLK

To Additional Optional Daisy-Chained Devices

DS060_27_080400

Figure 27: Express Mode Circuit Diagram

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Spartan and Spartan-XL FPGA Families Data Sheet

CCLK TIC INIT TCD TDC D0-D7

BYTE 0 BYTE 1 BYTE 6

DOUT Header Received FPGA Filled

DS060_28_080400

Symbol TIC TDC TCD TCCH TCCL FCC CCLK

Description INIT (High) setup time D0-D7 setup time D0-D7 hold time CCLK High time CCLK Low time CCLK Frequency

Min 5 20 0 45 45 -

Max 10

Units s ns ns ns ns MHz

Notes: 1. If not driven by the preceding DOUT, CS1 must remain High until the

device is fully configured.

Figure 28: Express Mode Programming Switching Characteristics

Setting CCLK Frequency

In Master mode, CCLK can be generated in either of two frequencies. In the default slow mode, the frequency ranges from 0.5 MHz to 1.25 MHz for Spartan/XL devices. In fast CCLK mode, the frequency ranges from 4 MHz to 10 MHz for Spartan/XL devices. The frequency is changed to fast by an option when running the bitstream generation software.

Express mode data is shown with D0 at the left and D7 at the right. The configuration data stream begins with a string of eight ones, a preamble code, followed by a 24-bit length count and a separator field of ones (or 24 fill bits, in Spartan-XL family Express mode). This header is followed by the actual configuration data in frames. The length and number of frames depends on the device type (see Table 17). Each frame begins with a start field and ends with an error check. In serial modes, a postamble code is required to signal the end of data for a single device. In all cases, additional start-up bytes of data are required to provide four clocks for the startup sequence at the end of configuration. Long daisy chains require additional startup bytes to shift the last data through the chain. All start-up bytes are "dont cares".

Data Stream Format

The data stream ("bitstream") format is identical for both serial configuration modes, but different for the Spartan-XL family Express mode. In Express mode, the device becomes active when DONE goes High, therefore no length count is required. Additionally, CRC error checking is not supported in Express mode. The data stream format is shown in Table 16. Bit-serial data is read from left to right.

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Spartan and Spartan-XL FPGA Families Data Sheet

Table 16: Spartan/XL Data Stream Formats Serial Modes (D0...) 11111111b 0010b COUNT[23:0] 1111b 0b DATA[n1:0] xxxx (CRC) or 0110b 01111111b FFh Express Mode (D0-D7) (Spartan-XL only) FFFFh 11110010b COUNT[23:0](1) 11010010b 11111110b(2) DATA[n1:0] 11010010b FFD2FFFFFFh FFFFFFFFFFFFFFh

Data Type Fill Byte Preamble Code Length Count Fill Bits Field Check Code Start Field Data Frame CRC or Constant Field Check Extend Write Cycle Postamble Start-Up Bytes(3) Legend: Unshaded Light Dark

A selection of CRC or non-CRC error checking is allowed by the bitstream generation software. The Spartan-XL family Express mode only supports non-CRC error checking. The non-CRC error checking tests for a designated end-of-frame field for each frame. For CRC error checking, the software calculates a running CRC and inserts a unique four-bit partial check at the end of each frame. The 11-bit CRC check of the last frame of an FPGA includes the last seven data bits. Detection of an error results in the suspension of data loading before DONE goes High, and the pulling down of the INIT pin. In Master serial mode, CCLK continues to operate externally. The user must detect INIT and initialize a new configuration by pulsing the PROGRAM pin Low or cycling VCC.

Cyclic Redundancy Check (CRC) for Configuration and Readback

The Cyclic Redundancy Check is a method of error detection in data transmission applications. Generally, the transmitting system performs a calculation on the serial bitstream. The result of this calculation is tagged onto the data stream as additional check bits. The receiving system performs an identical calculation on the bitstream and compares the result with the received checksum. Each data frame of the configuration bitstream has four error bits at the end, as shown in Table 16. If a frame data error is detected during the loading of the FPGA, the configuration process with a potentially corrupted bitstream is terminated. The FPGA pulls the INIT pin Low and goes into a Wait state.

Once per bitstream Once per data frame Once per device

Notes: 1. Not used by configuration logic. 2. 11111111b for XCS40XL only. 3. Development system may add more start-up bytes.

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Spartan and Spartan-XL FPGA Families Data Sheet

Table 17: Spartan/XL Program Data Device Max System Gates CLBs (Row x Col.) IOBs Part Number Supply Voltage Bits per Frame Frames Program Data PROM Size (bits) Express Mode PROM Size (bits) 5V 126 428 53,936 53,984 XCS05 5,000 100 (10 x 10) 80 3.3V 127 429 54,491 54,544 79,072 5V 166 572 94,960 95,008 XCS10 10,000 196 (14 x 14) 112 3.3V 167 573 95,699 95,752 128,488 5V 226 788 178,096 178,144 XCS20 20,000 400 (20 x 20) 160 3.3V 227 789 179,111 179,160 221,056 5V 266 932 247,920 247,968 XCS30 30,000 576 (24 x 24) 192 3.3V 267 933 249,119 249,168 298,696 5V 306 1,076 329,264 329,312 XCS40 40,000 784 (28 x 28) 205(4) 3.3V 307 1,077 330,647 330,696 387,856

XCS05 XCS05XL XCS10 XCS10XL XCS20 XCS20XL XCS30 XCS30XL XCS40 XCS40XL

Notes: 1. Bits per Frame = (10 x number of rows) + 7 for the top + 13 for the bottom + 1 + 1 start bit + 4 error check bits (+1 for Spartan-XL device) Number of Frames = (36 x number of columns) + 26 for the left edge + 41 for the right edge + 1 (+ 1 for Spartan-XL device) Program Data = (Bits per Frame x Number of Frames) + 8 postamble bits PROM Size = Program Data + 40 (header) + 8, rounded up to the nearest byte 2. The user can add more "1" bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra "one" bits, even for extra leading ones at the beginning of the header. 3. Express mode adds 57 (XCS05XL, XCS10XL), or 53 (XCS20XL, XCS30XL, XCS40XL) bits per frame, + additional start-up bits. 4. XCS40XL provided 224 max I/O in CS280 package discontinued by PDN2004-01.

During Readback, 11 bits of the 16-bit checksum are added to the end of the Readback data stream. The checksum is computed using the CRC-16 CCITT polynomial, as shown in Figure 29. The checksum consists of the 11 most significant bits of the 16-bit code. A change in the checksum indicates a change in the Readback bitstream. A comparison to a previous checksum is meaningful only if the readback

data is independent of the current device state. CLB outputs should not be included (Readback Capture option not used), and if RAM is present, the RAM content must be unchanged. Statistically, one error out of 2048 might go undetected.

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Spartan and Spartan-XL FPGA Families Data Sheet

X2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

X15 X16 15

SERIAL DATA IN

Polynomial: X16 + X15 + X2 + 1

0 15 14 13 12 11 10 9

LAST DATA FRAME

START BIT

CRC CHECKSUM

Readback Data Stream

DS060_29_080400

Figure 29: Circuit for Generating CRC-16

Configuration Sequence
There are four major steps in the Spartan/XL FPGA power-up configuration sequence. Configuration Memory Clear Initialization Configuration Start-up

Low. During this time delay, or as long as the PROGRAM input is asserted, the configuration logic is held in a Configuration Memory Clear state. The configuration-memory frames are consecutively initialized, using the internal oscillator. At the end of each complete pass through the frame addressing, the power-on time-out delay circuitry and the level of the PROGRAM pin are tested. If neither is asserted, the logic initiates one additional clearing of the configuration frames and then tests the INIT input.

The full process is illustrated in Figure 30.

Configuration Memory Clear

When power is first applied or is reapplied to an FPGA, an internal circuit forces initialization of the configuration logic. When VCC reaches an operational level, and the circuit passes the write and read test of a sample pair of configuration bits, a time delay is started. This time delay is nominally 16 ms. The delay is four times as long when in Master Serial Mode to allow ample time for all slaves to reach a stable VCC. When all INIT pins are tied together, as recommended, the longest delay takes precedence. Therefore, devices with different time delays can easily be mixed and matched in a daisy chain. This delay is applied only on power-up. It is not applied when reconfiguring an FPGA by pulsing the PROGRAM pin

Initialization
During initialization and configuration, user pins HDC, LDC, INIT and DONE provide status outputs for the system interface. The outputs LDC, INIT and DONE are held Low and HDC is held High starting at the initial application of power. The open drain INIT pin is released after the final initialization pass through the frame addresses. There is a deliberate delay before a Master-mode device recognizes an inactive INIT. Two internal clocks after the INIT pin is recognized as High, the device samples the MODE pin to determine the configuration mode. The appropriate interface lines become active and the configuration preamble and data can be loaded.

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Spartan and Spartan-XL FPGA Families Data Sheet

Configuration
Boundary Scan Instructions Available: VCC Valid Yes
Test MODE, Generate One Time-Out Pulse of 16 or 64 ms

No

PROGRAM = Low Yes

Keep Clearing Configuration Memory EXTEST* SAMPLE/PRELOAD Completely Clear BYPASS Configuration Memory ~1.3 s per Frame CONFIGURE* Once More (* if PROGRAM = High) INIT High? if Master Yes Sample Mode Line LDC Output = L, HDC Output = H Master CCLK Goes Active Load One Configuration Data Frame No Master Delays Before Sampling Mode Line

The 0010 preamble code indicates that the following 24 bits represent the length count for serial modes. The length count is the total number of configuration clocks needed to load the complete configuration data. (Four additional configuration clocks are required to complete the configuration process, as discussed below.) After the preamble and the length count have been passed through to any device in the daisy chain, its DOUT is held High to prevent frame start bits from reaching any daisy-chained devices. In Spartan-XL family Express mode, the length count bits are ignored, and DOUT is held Low, to disable the next device in the pseudo daisy chain. A specific configuration bit, early in the first frame of a master device, controls the configuration-clock rate and can increase it by a factor of eight. Therefore, if a fast configuration clock is selected by the bitstream, the slower clock rate is used until this configuration bit is detected. Each frame has a start field followed by the frame-configuration data bits and a frame error field. If a frame data error is detected, the FPGA halts loading, and signals the error by pulling the open-drain INIT pin Low. After all configuration frames have been loaded into an FPGA using a serial mode, DOUT again follows the input data so that the remaining data is passed on to the next device. In Spartan-XL family Express mode, when the first device is fully programmed, DOUT goes High to enable the next device in the chain.

Frame Error No SAMPLE/PRELOAD BYPASS Configuration memory Full Yes Pass Configuration Data to DOUT

Yes

Pull INIT Low and Stop

Delaying Configuration After Power-Up

There are two methods of delaying configuration after power-up: put a logic Low on the PROGRAM input, or pull the bidirectional INIT pin Low, using an open-collector (open-drain) driver. (See Figure 30.) A Low on the PROGRAM input is the more radical approach, and is recommended when the power-supply rise time is excessive or poorly defined. As long as PROGRAM is Low, the FPGA keeps clearing its configuration memory. When PROGRAM goes High, the configuration memory is cleared one more time, followed by the beginning of configuration, provided the INIT input is not externally held Low. Note that a Low on the PROGRAM input automatically forces a Low on the INIT output. The Spartan/XL FPGA PROGRAM pin has a permanent weak pull-up. Avoid holding PROGRAM Low for more than 500 s. The 500 s maximum limit is only a recommendation, not a requirement. The only effect of holding PROGRAM Low for more than 500 s is an increase in current, measured at about 40 mA in the XCS40XL. This increased current cannot damage the device. This applies only during reconfiguration, not during power-up. The INIT pin can also be held Low to delay reconfiguration, and the same characteristics apply as for the PROGRAM pin. Using an open-collector or open-drain driver to hold INIT Low before the beginning of configuration causes the FPGA

No

CCLK Count Equals Length Count Yes Start-Up Sequence F EXTEST SAMPLE PRELOAD BYPASS USER 1 USER 2 CONFIGURE READBACK Operational

No

If Boundary Scan is Selected

DS060_30_080400

Figure 30: Power-up Configuration Sequence

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I/O Active

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Spartan and Spartan-XL FPGA Families Data Sheet to wait after completing the configuration memory clear operation. When INIT is no longer held Low externally, the device determines its configuration mode by capturing the state of the Mode pins, and is ready to start the configuration process. A master device waits up to an additional 300 s to make sure that any slaves in the optional daisy chain have seen that INIT is High. For more details on Configuration, refer to the Xilinx Application Note "FPGA Configuration Guidelines" (XAPP090).

Figure 31 describes start-up timing in detail. The three events DONE going High, the internal GSR being de-activated, and the user I/O going active can all occur in any arbitrary sequence. This relative timing is selected by options in the bitstream generation software. Heavy lines in Figure 31 show the default timing. The thin lines indicate all other possible timing options. The start-up logic must be clocked until the "F" (Finished) state is reached. The default option, and the most practical one, is for DONE to go High first, disconnecting the configuration data source and avoiding any contention when the I/Os become active one clock later. GSR is then released another clock period later to make sure that user operation starts from stable internal conditions. This is the most common sequence, shown with heavy lines in Figure 31, but the designer can modify it to meet particular requirements. Start-Up Clock Normally, the start-up sequence is controlled by the internal device oscillator (CCLK), which is asynchronous to the system clock. As a configuration option, they can be triggered by an on-chip user net called UCLK. This user net can be accessed by placing the STARTUP library symbol, and the start-up modes are known as UCLK_NOSYNC or UCLK_SYNC. This allows the device to wake up in synchronism with the user system. DONE Pin Note that DONE is an open-drain output and does not go High unless an internal pull-up is activated or an external pull-up is attached. The internal pull-up is activated as the default by the bitstream generation software. The DONE pin can also be wire-ANDed with DONE pins of other FPGAs or with other external signals, and can then be used as input to the start-up control logic. This is called Start-up Timing Synchronous to Done In and is selected by either CCLK_SYNC or UCLK_SYNC. When DONE is not used as an input, the operation is called Start-up Timing Not Synchronous to DONE In, and is selected by either CCLK_NOSYNC or UCLK_NOSYNC. Express mode configuration always uses either CCLK_SYNC or UCLK_SYNC timing, while the other configuration modes can use any of the four timing sequences. When the UCLK_SYNC option is enabled, the user can externally hold the open-drain DONE output Low, and thus stall all further progress in the start-up sequence until DONE is released and has gone High. This option can be used to force synchronization of several FPGAs to a common user clock, or to guarantee that all devices are successfully configured before any I/Os go active.

Start-Up
Start-up is the transition from the configuration process to the intended user operation. This transition involves a change from one clock source to another, and a change from interfacing parallel or serial configuration data where most outputs are 3-stated, to normal operation with I/O pins active in the user system. Start-up must make sure that the user logic wakes up gracefully, that the outputs become active without causing contention with the configuration signals, and that the internal flip-flops are released from the Global Set/Reset (GSR) at the right time. Start-Up Initiation Two conditions have to be met in order for the start-up sequence to begin: The chip's internal memory must be full, and The configuration length count must be met, exactly.

In all configuration modes except Express mode, Spartan/XL devices read the expected length count from the bitstream and store it in an internal register. The length count varies according to the number of devices and the composition of the daisy chain. Each device also counts the number of CCLKs during configuration. In Express mode, there is no length count. The start-up sequence for each device begins when the device has received its quota of configuration data. Wiring the DONE pins of several devices together delays start-up of all devices until all are fully configured. Start-Up Events The device can be programmed to control three start-up events. The release of the open-drain DONE output The termination of the Global Three-State and the change of configuration-related pins to the user function, activating all IOBs. The termination of the Global Set/Reset initialization of all CLB and IOB storage elements.

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Spartan and Spartan-XL FPGA Families Data Sheet

Length Count Match

CCLK Period

CCLK
F DONE C1 I/O C2 C3 C4 F = Finished, no more configuration clocks needed Daisy-chain lead device must have latest F Heavy lines describe default timing

CCLK_NOSYNC

C2 GSR Active C2 DONE IN

C3

C4

C3

C4 F

DONE C1, C2 or C3 I/O

CCLK_SYNC

Di GSR Active Di

Di+1

Di+1 F

DONE C1 I/O U2 U3 U4

UCLK_NOSYNC
GSR Active

U2

U3

U4

U2 DONE IN

U3

U4 F

DONE C1 I/O U2

UCLK_SYNC
GSR Active Synchronization Uncertainty

Di

Di+1

Di+2

Di

Di+1

Di+2

UCLK Period
DS060_39_082801

Figure 31: Start-up Timing

Configuration Through the Boundary Scan Pins

Spartan/XL devices can be configured through the boundary scan pins. The basic procedure is as follows: Power up the FPGA with INIT held Low (or drive the PROGRAM pin Low for more than 300 ns followed by a High while holding INIT Low). Holding INIT Low allows enough time to issue the CONFIG command to the FPGA. The pin can be used as I/O after configuration if a resistor is used to hold INIT Low. Issue the CONFIG command to the TMS input.

Wait for INIT to go High. Sequence the boundary scan Test Access Port to the SHIFT-DR state. Toggle TCK to clock data into TDI pin.

The user must account for all TCK clock cycles after INIT goes High, as all of these cycles affect the Length Count compare. For more detailed information, refer to the Xilinx application note, "Boundary Scan in FPGA Devices." This application note applies to Spartan and Spartan-XL devices.

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Spartan and Spartan-XL FPGA Families Data Sheet

Readback
The user can read back the content of configuration memory and the level of certain internal nodes without interfering with the normal operation of the device. Readback not only reports the downloaded configuration bits, but can also include the present state of the device, represented by the content of all flip-flops and latches in CLBs and IOBs, as well as the content of function generators used as RAMs. Although readback can be performed while the device is operating, for best results and to freeze a known capture state, it is recommended that the clock inputs be stopped until readback is complete. Readback of Spartan-XL family Express mode bitstreams results in data that does not resemble the original bitstream, because the bitstream format differs from other modes. Spartan/XL FPGA Readback does not use any dedicated pins, but uses four internal nets (RDBK.TRIG, RDBK.DATA, RDBK.RIP and RDBK.CLK) that can be routed to any IOB. To access the internal Readback signals, instantiate the READBACK library symbol and attach the appropriate pad symbols, as shown in Figure 32. After Readback has been initiated by a Low-to-High transition on RDBK.TRIG, the RDBK.RIP (Read In Progress) output goes High on the next rising edge of RDBK.CLK. Subsequent rising edges of this clock shift out Readback data on the RDBK.DATA net. Readback data does not include the preamble, but starts with five dummy bits (all High) followed by the Start bit (Low)
If Unconnected, Default is CCLK

of the first frame. The first two data bits of the first frame are always High. Each frame ends with four error check bits. They are read back as High. The last seven bits of the last frame are also read back as High. An additional Start bit (Low) and an 11-bit Cyclic Redundancy Check (CRC) signature follow, before RDBK.RIP returns Low.

Readback Options
Readback options are: Readback Capture, Readback Abort, and Clock Select. They are set with the bitstream generation software. Readback Capture When the Readback Capture option is selected, the data stream includes sampled values of CLB and IOB signals. The rising edge of RDBK.TRIG latches the inverted values of the four CLB outputs, the IOB output flip-flops and the input signals I1 and I2. Note that while the bits describing configuration (interconnect, function generators, and RAM content) are not inverted, the CLB and IOB output signals are inverted. RDBK.TRIG is located in the lower-left corner of the device. When the Readback Capture option is not selected, the values of the capture bits reflect the configuration data originally written to those memory locations. If the RAM capability of the CLBs is used, RAM data are available in Readback, since they directly overwrite the F and G function-table configuration of the CLB.

CLK READ_TRIGGER
IBUF

DATA READBACK RIP

OBUF

READ_DATA

TRIG

DS060_31_080400

Figure 32: Readback Example

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Spartan and Spartan-XL FPGA Families Data Sheet met. For example, if a processor is controlling Readback, an interrupt may force it to stop in the middle of a readback. This necessitates stopping the clock, and thus violating the specification. The specification is mandatory only on clocking data at the end of a frame prior to the next start bit. The transfer mechanism will load the data to a shift register during the last six clock cycles of the frame, prior to the start bit of the following frame. This loading process is dynamic, and is the source of the maximum High and Low time requirements. Therefore, the specification only applies to the six clock cycles prior to and including any start bit, including the clocks before the first start bit in the Readback data stream. At other times, the frame data is already in the register and the register is not dynamic. Thus, it can be shifted out just like a regular shift register. The user must precisely calculate the location of the Readback data relative to the frame. The system must keep track of the position within a data frame, and disable interrupts before frame boundaries. Frame lengths and data formats are listed in Table 16 and Table 17.

Readback Abort When the Readback Abort option is selected, a High-to-Low transition on RDBK.TRIG terminates the Readback operation and prepares the logic to accept another trigger. After an aborted Readback, additional clocks (up to one Readback clock per configuration frame) may be required to re-initialize the control logic. The status of Readback is indicated by the output control net RDBK.RIP. RDBK.RIP is High whenever a readback is in progress. Clock Select CCLK is the default clock. However, the user can insert another clock on RDBK.CLK. Readback control and data are clocked on rising edges of RDBK.CLK. If Readback must be inhibited for security reasons, the Readback control nets are simply not connected. RDBK.CLK is located in the lower right chip corner. Violating the Maximum High and Low Time Specification for the Readback Clock The Readback clock has a maximum High and Low time specification. In some cases, this specification cannot be

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Spartan and Spartan-XL FPGA Families Data Sheet

Readback Switching Characteristics Guidelines

The following guidelines reflect worst-case values over the recommended operating conditions.
Finished Internal Net

rdbk.TRIG
TRTRC TRCRT TRTRC TRCRT

rdclk.I
TRCL TRCH

rdbk.RIP
TRCRR

rdbk.DATA

DUMMY

DUMMY

VALID

VALID

TRCRD
DS060_32_080400

Figure 33: Spartan and Spartan-XL Readback Timing Diagram Spartan and Spartan-XL Readback Switching Characteristics Symbol TRTRC TRCRT TRCRD TRCRR TRCH TRCL rdclk.I rdbk.TRIG Description rdbk.TRIG setup to initiate and abort Readback rdbk.TRIG hold to initiate and abort Readback rdbk.DATA delay rdbk.RIP delay High time Low time Min 200 50 250 250 Max 250 250 500 500 Units ns ns ns ns ns ns

Notes: 1. Timing parameters apply to all speed grades. 2. If rdbk.TRIG is High prior to Finished, Finished will trigger the first Readback.

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Spartan and Spartan-XL FPGA Families Data Sheet

Configuration Switching Characteristics

VCC
TPOR

RE-PROGRAM
>300 ns

PROGRAM
TPI

INIT
TICCK TCCLK

CCLK Output or Input

<300 ns

Mode Pins (Required)

DONE Response
<300 ns

I/O

DS060_33_080400

Master Mode
Symbol TPOR TPI TICCK TCCLK TCCLK Description Power-on reset Program Latency CCLK (output) delay CCLK (output) period, slow CCLK (output) period, fast Min 40 30 40 640 100 Max 130 200 250 2000 250 Units ms s per CLB column s ns ns

Slave Mode
Symbol TPOR TPI TICCK TCCLK Description Power-on reset Program latency CCLK (input) delay (required) CCLK (input) period (required) Min 10 30 4 80 Max 33 200 Units ms s per CLB column s ns

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Spartan and Spartan-XL FPGA Families Data Sheet

Spartan Family Detailed Specifications

Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as follows: Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or families. Values are subject to change. Use as estimates, not for production. Preliminary: Based on preliminary characterization. Further changes are not expected. Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final. Notwithstanding the definition of the above terms, all specifications are subject to change without notice. Except for pin-to-pin input and output parameters, the AC parameter delay specifications included in this document are derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction temperature conditions. The parameters included are common to popular designs and typical applications.

Spartan Family Absolute Maximum Ratings(1)

Symbol VCC VIN VTS TSTG TJ Supply voltage relative to GND Input voltage relative to GND(2,3) Voltage applied to 3-state output(2,3) Description Value 0.5 to +7.0 0.5 to VCC +0.5 0.5 to VCC +0.5 65 to +150 Plastic packages +125 Units V V V C C

Storage temperature (ambient) Junction temperature

Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. 2. Maximum DC overshoot (above VCC) or undershoot (below GND) must be limited to either 0.5V or 10 mA, whichever is easier to achieve. 3. Maximum AC (during transitions) conditions are as follows; the device pins may undershoot to 2.0V or overshoot to +7.0V, provided this overshoot or undershoot lasts no more than 11 ns with a forcing current no greater than 100 mA. 4. For soldering guidelines, see the Package Infomation on the Xilinx website.

Spartan Family Recommended Operating Conditions

Symbol VCC VIH VIL TIN Description Supply voltage relative to GND, TJ = 0C to +85C Supply voltage relative to GND, TJ = 40C to High-level input voltage(2) Low-level input voltage(2) +100C(1) Commercial Industrial TTL inputs CMOS inputs TTL inputs CMOS inputs Input signal transition time Min 4.75 4.5 2.0 70% 0 0 Max 5.25 5.5 VCC 100% 0.8 20% 250 Units V V V VCC V VCC ns

Notes: 1. At junction temperatures above those listed as Recommended Operating Conditions, all delay parameters increase by 0.35% per C. 2. Input and output measurement thresholds are: 1.5V for TTL and 2.5V for CMOS.

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Spartan and Spartan-XL FPGA Families Data Sheet

Spartan Family DC Characteristics Over Operating Conditions

Symbol VOH VOL VDR ICCO IL CIN IRPU IRPD Description High-level output voltage @ IOH = 4.0 mA, VCC min High-level output voltage @ IOH = 1.0 mA, VCC min Low-level output voltage @ IOL = 12.0 mA, VCC min(1) TTL outputs CMOS outputs TTL outputs CMOS outputs Data retention supply voltage (below which configuration data may be lost) Quiescent FPGA supply current(2) Input or output leakage current Input capacitance (sample tested) Pad pull-up (when selected) @ VIN = 0V (sample tested) Pad pull-down (when selected) @ VIN = 5V (sample tested) Commercial Industrial Min 2.4 VCC 0.5 3.0 10 0.02 0.02 Max 0.4 0.4 3.0 6.0 +10 10 0.25 Units V V V V V mA mA A pF mA mA

Notes: 1. With 50% of the outputs simultaneously sinking 12 mA, up to a maximum of 64 pins. 2. With no output current loads, no active input pull-up resistors, all package pins at VCC or GND, and the FPGA configured with a Tie option.

Spartan Family Global Buffer Switching Characteristic Guidelines

All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature).

Speed Grade -4 Symbol TPG Description From pad through Primary buffer, to any clock K Device XCS05 XCS10 XCS20 XCS30 XCS40 TSG From pad through Secondary buffer, to any clock K XCS05 XCS10 XCS20 XCS30 XCS40 Max 2.0 2.4 2.8 3.2 3.5 2.5 2.9 3.3 3.6 3.9 -3 Max 4.0 4.3 5.4 5.8 6.4 4.4 4.7 5.8 6.2 6.7 Units ns ns ns ns ns ns ns ns ns ns

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Spartan and Spartan-XL FPGA Families Data Sheet

Spartan Family CLB Switching Characteristic Guidelines

All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all Spartan devices and expressed in nanoseconds unless otherwise noted. Speed Grade Symbol Clocks TCH TCL TILO TIHO Description -4 Min 3.0 3.0 1.8 2.9 2.3 1.3 2.0 2.5 0.0 3.0 11.5 Max 1.2 2.0 1.7 1.7 2.8 1.2 2.0 0.5 2.1 3.0 166 Min 4.0 4.0 2.4 3.9 3.3 2.0 2.6 4.0 0.0 4.0 13.5 -3 Max 1.6 2.7 2.2 2.1 3.7 1.4 2.6 0.6 2.8 4.0 125 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz

Clock High time Clock Low time F/G inputs to X/Y outputs F/G inputs via H to X/Y outputs

Combinatorial Delays

THH1O C inputs via H1 via H to X/Y outputs CLB Fast Carry Logic TOPCY Operand inputs (F1, F2, G1, G4) to COUT TASCY TINCY TSUM TBYP Add/Subtract input (F3) to COUT Initialization inputs (F1, F3) to COUT CIN through function generators to X/Y outputs CIN to COUT, bypass function generators

Sequential Delays

TCKO Clock K to Flip-Flop outputs Q Setup Time before Clock K TICK F/G inputs TIHCK THH1CK TDICK TECCK F/G inputs via H C inputs via H1 through H C inputs via DIN C inputs via EC

TRCK C inputs via S/R, going Low (inactive) Hold Time after Clock K All Hold times, all devices Set/Reset Direct TRPW Width (High) TRIO TMRW TMRQ FTOG Delay from C inputs via S/R, going High to Q Minimum GSR pulse width Delay from GSR input to any Q Toggle Frequency (MHz) (for export control purposes)
Global Set/Reset

See page 50 for TRRI values per device.

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Spartan and Spartan-XL FPGA Families Data Sheet

Spartan Family CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines

All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all Spartan devices and are expressed in nanoseconds unless otherwise noted. Speed Grade -4 Symbol Single Port RAM Write Operation TWCS Address write cycle time (clock K period) TWCTS TWPS TWPTS TASS TASTS TAHS TAHTS TDSS TDSTS TDHS TDHTS TWSS TWSTS TWHS TWHTS TWOS TWOTS
Read Operation

-3 Max 6.5 7.0 1.2 2.0 Min 11.6 11.6 5.8 5.8 2.0 2.0 0.0 0.0 2.7 1.7 0.0 0.0 1.6 1.6 0.0 0.0 2.6 3.8 2.4 3.9 Max 7.9 9.3 1.6 2.7 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Size(1) 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1

Min 8.0 8.0 4.0 4.0 1.5 1.5 0.0 0.0 1.5 1.5 0.0 0.0 1.5 1.5 0.0 0.0 2.6 3.8 1.8 2.9

Clock K pulse width (active edge) Address setup time before clock K Address hold time after clock K DIN setup time before clock K DIN hold time after clock K WE setup time before clock K WE hold time after clock K Data valid after clock K

TRC TRCT TILO TIHO TICK TIHCK

Address read cycle time Data valid after address change (no Write Enable) Address setup time before clock K

16x2 32x1 16x2 32x1 16x2 32x1

Notes: 1. Timing for 16 x 1 RAM option is identical to 16 x 2 RAM timing.

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Spartan and Spartan-XL FPGA Families Data Sheet

Spartan Family CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines (continued)
All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all Spartan devices and are expressed in nanoseconds unless otherwise noted.

Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics

-4 Symbol
Write Operation

-3 Max Min Max Units

Dual Port RAM

Size(1)

Min

TWCDS TWPDS TASDS TAHDS TDSDS TDHDS TWSDS TWHDS TWODS

Address write cycle time (clock K period) Clock K pulse width (active edge) Address setup time before clock K Address hold time after clock K DIN setup time before clock K DIN hold time after clock K WE setup time before clock K WE hold time after clock K Data valid after clock K

16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1

8.0 4.0 1.5 0 1.5 0 1.5 0 -

6.5

11.6 5.8 2.1 0 1.6 0 1.6 0 -

7.0

ns ns ns ns ns ns ns ns ns

Notes: 1. Read Operation timing for 16 x 1 dual-port RAM option is identical to 16 x 2 single-port RAM timing

Spartan Family CLB RAM Synchronous (Edge-Triggered) Write Timing

Single Port
TWPS WCLK (K) TWSS WE TDSS DATA IN TASS ADDRESS TAHS
ADDRESS WCLK (K)

Dual Port
TWPDS

TWHS
WE

TWSDS

TWHDS

TDHS
DATA IN

TDSDS

TDHDS

TASDS

TAHDS

TILO DATA OUT

TILO TWOS
OLD NEW

TILO DATA OUT

TILO TWODS
OLD NEW
DS060_34_011300

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Spartan and Spartan-XL FPGA Families Data Sheet

Spartan Family Pin-to-Pin Output Parameter Guidelines

All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report.

Spartan Family Output Flip-Flop, Clock-to-Out

Speed Grade -4 Symbol Description Global Primary Clock to TTL Output using OFF TICKOF Fast Device XCS05 XCS10 XCS20 XCS30 XCS40 TICKO Slew-rate limited XCS05 XCS10 XCS20 XCS30 XCS40
Global Secondary Clock to TTL Output using OFF

-3 Max 8.7 9.1 9.3 9.4 10.2 11.5 12.0 12.2 12.8 12.8 9.2 9.6 9.8 9.9 10.7 12.0 12.5 12.7 13.2 14.3 1.0 2.0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Max 5.3 5.7 6.1 6.5 6.8 9.0 9.4 9.8 10.2 10.5 5.8 6.2 6.6 7.0 7.3 9.5 9.9 10.3 10.7 11.0 0.8 1.5

TICKSOF

Fast

XCS05 XCS10 XCS20 XCS30 XCS40

TICKSO

Slew-rate limited

XCS05 XCS10 XCS20 XCS30 XCS40

Delay Adder for CMOS Outputs Option

TCMOSOF TCMOSO

Fast Slew-rate limited

All devices All devices

Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column,and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load. For different loads, see Figure 33. 3. OFF = Output Flip-Flop

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Spartan and Spartan-XL FPGA Families Data Sheet Capacitive Load Factor Figure 33 shows the relationship between I/O output delay and load capacitance. It allows a user to adjust the specified output delay if the load capacitance is different than 50 pF. For example, if the actual load capacitance is 120 pF, add 2.5 ns to the specified delay. If the load capacitance is 20 pF, subtract 0.8 ns from the specified output delay. Figure 33 is usable over the specified operating conditions of voltage and temperature and is independent of the output slew rate control.
3

Delta Delay (ns)

-1

-2 0 20 40 60 80 100 120 140

Capacitance (pF)
DS060_35_080400

Figure 34: Delay Factor at Various Capacitive Loads

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Spartan and Spartan-XL FPGA Families Data Sheet

Spartan Family Pin-to-Pin Input Parameter Guidelines

All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading.

Spartan Family Primary and Secondary Setup and Hold

Speed Grade -4 Symbol Description Input Setup/Hold Times Using Primary Clock and IFF TPSUF/TPHF No Delay Device XCS05 XCS10 XCS20 XCS30 XCS40 TPSU/TPH With Delay XCS05 XCS10 XCS20 XCS30 XCS40
Input Setup/Hold Times Using Secondary Clock and IFF

-3 Min 1.8 / 2.5 1.5 / 3.4 1.2 / 4.0 0.9 / 4.5 0.6 / 5.2 6.0 / 0.0 6.0 / 0.0 6.0 / 0.0 6.0 / 0.0 6.8 / 0.0 1.5 / 3.0 1.2 / 3.9 0.9 / 4.5 0.6 / 5.0 0.3 / 5.7 5.7 / 0.0 5.7 / 0.0 5.7 / 0.5 5.7 / 0.5 6.5 / 0.0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Min 1.2 / 1.7 1.0 / 2.3 0.8 / 2.7 0.6 / 3.0 0.4 / 3.5 4.3 / 0.0 4.3 / 0.0 4.3 / 0.0 4.3 / 0.0 5.3 / 0.0 0.9 / 2.2 0.7 / 2.8 0.5 / 3.2 0.3 / 3.5 0.1 / 4.0 4.0 / 0.0 4.0 / 0.0 4.0 / 0.5 4.0 / 0.5 5.0 / 0.0

TSSUF/TSHF

No Delay

XCS05 XCS10 XCS20 XCS30 XCS40

TSSU/TSH

With Delay

XCS05 XCS10 XCS20 XCS30 XCS40

Notes: 1. Setup time is measured with the fastest route and the lightest load. Hold time is measured using the furthest distance and a reference load of one clock pin per IOB/CLB. 2. IFF = Input Flip-flop or Latch

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Spartan and Spartan-XL FPGA Families Data Sheet

Spartan Family IOB Input Switching Characteristic Guidelines

All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Speed Grade -4 Symbol
Setup Times - TTL Inputs(1)

-3 Max 1.5 2.8 2.7 3.2 9.0 9.5 10.0 10.5 11.0 Min 2.1 2.0 0.9 0.0 4.0 4.1 4.2 5.0 5.5 13.5 Max 2.0 3.6 2.8 3.9 11.3 11.9 12.5 13.1 13.8 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Description Clock Enable (EC) to Clock (IK), no delay Pad to Clock (IK), no delay Clock Enable (EC) to Clock (IK), no delay All Other Hold Times
Inputs(1)

Device All devices All devices All devices All devices All devices All devices All devices All devices XCS05 XCS10 XCS20 XCS30 XCS40

Min 1.6 1.5 0.0 0.0 3.6 3.7 3.8 4.5 5.5 11.5 -

TECIK TPICK TIKEC

Hold Times

Propagation Delays - TTL

TPID TPLI TIKRI TIKLI TDelay

Pad to I1, I2 Pad to I1, I2 via transparent input latch, no delay Clock (IK) to I1, I2 (flip-flop) Clock (IK) to I1, I2 (latch enable, active Low) TECIKD = TECIK + TDelay TPICKD = TPICK + TDelay TPDLI = TPLI + TDelay

Delay Adder for Input with Delay Option

Global Set/Reset

TMRW TRRI

Minimum GSR pulse width Delay from GSR input to any Q

All devices XCS05 XCS10 XCS20 XCS30 XCS40

Notes: 1. Delay adder for CMOS Inputs option: for -3 speed grade, add 0.4 ns; for -4 speed grade, add 0.2 ns. 2. Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock input, see the pin-to-pin parameters in the Pin-to-Pin Input Parameters table. 3. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.

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Spartan and Spartan-XL FPGA Families Data Sheet

Spartan Family IOB Output Switching Characteristic Guidelines

All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values are expressed in nanoseconds unless otherwise noted. Speed Grade -4 Symbol
Clocks

-3 Max 3.3 6.9 3.6 7.2 3.0 6.0 9.6 Min 4.0 4.0 3.8 0.0 2.7 0.5 13.5 12.0 12.5 13.0 13.5 14.0 15.0 15.7 16.2 16.9 17.5 Max 4.5 7.0 4.8 7.3 3.8 7.3 9.8 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Description Clock High Clock Low Clock (OK) to Pad, fast Clock (OK to Pad, slew-rate limited Output (O) to Pad, fast Output (O) to Pad, slew-rate limited 3-state to Pad High-Z (slew-rate independent) 3-state to Pad active and valid, fast 3-state to Pad active and valid, slew-rate limited Output (O) to clock (OK) setup time Output (O) to clock (OK) hold time Clock Enable (EC) to clock (OK) setup time Clock Enable (EC) to clock (OK) hold time Minimum GSR pulse width Delay from GSR input to any Pad

Device All devices All devices All devices All devices All devices All devices All devices All devices All devices All devices All devices All devices All devices All devices XCS05 XCS10 XCS20 XCS30 XCS40

Min 3.0 3.0 2.5 0.0 2.0 0.0 11.5 -

TCH TCL TOKPOF TOKPOS TOPF TOPS TTSHZ TTSONF TTSONS TOOK TOKO TECOK TOKEC TMRW TRPO

Propagation Delays - TTL Outputs(1,2)

Setup and Hold Times

Global Set/Reset

Notes: 1. Delay adder for CMOS Outputs option (with fast slew rate option): for -3 speed grade, add 1.0 ns; for -4 speed grade, add 0.8 ns. 2. Delay adder for CMOS Outputs option (with slow slew rate option): for -3 speed grade, add 2.0 ns; for -4 speed grade, add 1.5 ns. 3. Output timing is measured at ~50% VCC threshold, with 50 pF external capacitive loads including test fixture. Slew-rate limited output rise/fall times are approximately two times longer than fast output rise/fall times. 4. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.

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Spartan and Spartan-XL FPGA Families Data Sheet

Spartan-XL Family Detailed Specifications

Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as follows: Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device families. Values are subject to change. Use as estimates, not for production. Preliminary: Based on preliminary characterization. Further changes are not expected. Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final. Notwithstanding the definition of the above terms, all specifications are subject to change without notice. Except for pin-to-pin input and output parameters, the AC parameter delay specifications included in this document are derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction temperature conditions. The parameters included are common to popular designs and typical applications.

Spartan-XL Family Absolute Maximum Ratings(1)

Symbol VCC VIN VTS TSTG TJ Supply voltage relative to GND Input voltage relative to GND Voltage applied to 3-state output Storage temperature (ambient) Junction temperature Plastic packages 5V Tolerant I/O Checked(2, 3) Not 5V Tolerant I/Os(4, 5) 5V Tolerant I/O Checked(2, 3) Not 5V Tolerant I/Os(4, 5) Description Value 0.5 to 4.0 0.5 to 5.5 0.5 to VCC + 0.5 0.5 to 5.5 0.5 to VCC + 0.5 65 to +150 +125 Units V V V V V C C

Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. 2. With 5V Tolerant I/Os selected, the Maximum DC overshoot must be limited to either +5.5V or 10 mA and undershoot (below GND) must be limited to either 0.5V or 10 mA, whichever is easier to achieve. 3. With 5V Tolerant I/Os selected, the Maximum AC (during transitions) conditions are as follows; the device pins may undershoot to 2.0V or overshoot to + 7.0V, provided this overshoot or undershoot lasts no more than 11 ns with a forcing current no greater than 100 mA. 4. Without 5V Tolerant I/Os selected, the Maximum DC overshoot or undershoot must be limited to either 0.5V or 10 mA, whichever is easier to achieve. 5. Without 5V Tolerant I/Os selected, the Maximum AC conditions are as follows; the device pins may undershoot to 2.0V or overshoot to VCC + 2.0V, provided this overshoot or undershoot lasts no more than 11 ns with a forcing current no greater than 100 mA. 6. For soldering guidelines, see the Package Infomation on the Xilinx website.

Spartan-XL Family Recommended Operating Conditions

Symbol VCC VIH VIL TIN Description Supply voltage relative to GND, TJ = 0C to +85C Supply voltage relative to GND, TJ = 40C to +100C(1) High-level input voltage(2) Low-level input voltage(2) Input signal transition time Commercial Industrial Min 3.0 3.0 50% of VCC 0 Max 3.6 3.6 5.5 30% of VCC 250 Units V V V V ns

Notes: 1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per C. 2. Input and output measurement threshold is ~50% of VCC.

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Spartan and Spartan-XL FPGA Families Data Sheet

Spartan-XL Family DC Characteristics Over Operating Conditions

Symbol VOH VOL Description High-level output voltage @ IOH = 4.0 mA, VCC min (LVTTL) High-level output voltage @ IOH = 500 A, (LVCMOS) Low-level output voltage @ IOL = 12.0 mA, VCC min Low-level output voltage @ IOL = 24.0 mA, VCC min VDR ICCO ICCPD IL CIN IRPU IRPD (LVTTL)(1) (LVTTL)(2) Min 2.4 90% VCC 2.5 10 0.02 0.02 Typ. 0.1 0.1 0.1 0.1 Max 0.4 0.4 10% VCC 2.5 5 2.5 5 10 10 0.25 Units V V V V V V mA mA mA mA A pF mA mA

Low-level output voltage @ IOL = 1500 A, (LVCMOS) Data retention supply voltage (below which configuration data may be lost) Quiescent FPGA supply current(3,4) Power Down FPGA supply current(3,5) Input or output leakage current Input capacitance (sample tested) Pad pull-up (when selected) @ VIN = 0V (sample tested) Pad pull-down (when selected) @ VIN = 3.3V (sample tested) Commercial Industrial Commercial Industrial

Notes: 1. With up to 64 pins simultaneously sinking 12 mA (default mode). 2. With up to 64 pins simultaneously sinking 24 mA (with 24 mA option selected). 3. With 5V tolerance not selected, no internal oscillators, and the FPGA configured with the Tie option. 4. With no output current loads, no active input resistors, and all package pins at VCC or GND. 5. With PWRDWN active.

Supply Current Requirements During Power-On

Spartan-XL FPGAs require that a minimum supply current ICCPO be provided to the VCC lines for a successful power on. If more current is available, the FPGA can consume more than ICCPO min., though this cannot adversely affect reliability. Symbol I CCPO TCCPO VCC ramp time(2,3) Description Total VCC supply current required during power-on A maximum limit for ICCPO is not specified. Be careful when using foldback/crowbar supplies and fuses. It is possible to control the magnitude of ICCPO by limiting the supply current available to the FPGA. A current limit below the trip level will avoid inadvertently activating over-current protection circuits. Min 100 Max 50 Units mA ms

Notes: 1. The ICCPO requirement applies for a brief time (commonly only a few milliseconds) when VCC ramps from 0 to 3.3V. 2. The ramp time is measured from GND to VCC max on a fully loaded board. 3. VCC must not dip in the negative direction during power on.

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Spartan and Spartan-XL FPGA Families Data Sheet

Spartan-XL Family Global Buffer Switching Characteristic Guidelines

All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature).

Speed Grade -5 Symbol TGLS Description From pad through buffer, to any clock K Device XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL Max 1.4 1.7 2.0 2.3 2.6 -4 Max 1.5 1.8 2.1 2.5 2.8 Units ns ns ns ns ns

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Spartan and Spartan-XL FPGA Families Data Sheet

Spartan-XL Family CLB Switching Characteristic Guidelines

All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all Spartan-XL devices and expressed in nanoseconds unless otherwise noted. Speed Grade -5 Symbol
Clocks

-4 Max 1.0 1.7 1.5 1.5 1.2 2.3 250 Min 2.3 2.3 0.7 1.6 0.0 2.8 11.5 Max 1.1 2.0 1.8 1.8 1.4 2.7 217 Units ns ns ns ns ns ns ns ns ns ns ns ns ns MHz

Description Clock High time Clock Low time F/G inputs to X/Y outputs F/G inputs via H to X/Y outputs F/G inputs via transparent latch to Q outputs C inputs via H1 via H to X/Y outputs Clock K to Flip-Flop or latch outputs Q F/G inputs F/G inputs via H All Hold times, all devices

Min 2.0 2.0 0.6 1.3 0.0 2.5 10.5 -

TCH TCL TILO TIHO TITO THH1O TCKO TICK TIHCK

Combinatorial Delays

Sequential Delays

Setup Time before Clock K

Hold Time after Clock K

Set/Reset Direct

TRPW TRIO TMRW TMRQ FTOG

Width (High) Delay from C inputs via S/R, going High to Q Minimum GSR Pulse Width Delay from GSR input to any Q Toggle Frequency (MHz) (for export control purposes)

Global Set/Reset

See page 60 for TRRI values per device.

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Spartan and Spartan-XL FPGA Families Data Sheet

Spartan-XL Family CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines

All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all Spartan-XL devices and are expressed in nanoseconds unless otherwise noted. Speed Grade -5 Symbol Single Port RAM Write Operation TWCS Address write cycle time (clock K period) TWCTS TWPS TWPTS TASS TASTS TDSS TDSTS TWSS TWSTS All hold times after clock K TWOS TWOTS
Read Operation

-4 Max 4.5 5.4 1.0 1.7 Min 8.4 8.4 3.6 3.6 1.5 1.7 1.7 2.1 1.6 1.5 0.0 3.1 5.5 0.7 1.6 Max 5.3 6.3 1.1 2.0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Size(1) 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2

Min 7.7 7.7 3.1 3.1 1.3 1.5 1.5 1.8 1.4 1.3 0.0 2.6 3.8 0.6 1.3

Clock K pulse width (active edge) Address setup time before clock K DIN setup time before clock K WE setup time before clock K

Data valid after clock K

TRC TRCT TILO TIHO TICK TIHCK

Address read cycle time Data Valid after address change (no Write Enable) Address setup time before clock K

16x2 32x1 16x2 32x1 16x2 32x1

Notes: 1. Timing for 16 x 1 RAM option is identical to 16 x 2 RAM timing.

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Spartan and Spartan-XL FPGA Families Data Sheet

Spartan-XL Family CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines (cont.)
All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all Spartan-XL devices and are expressed in nanoseconds unless otherwise noted. -5 Symbol
Write Operation(1)

-4 Max Min Max Units

Dual Port RAM

Size

Min

TWCDS TWPDS TASDS TDSDS TWSDS

Address write cycle time (clock K period) Clock K pulse width (active edge) Address setup time before clock K DIN setup time before clock K WE setup time before clock K All hold times after clock K

16x1 16x1 16x1 16x1 16x1 16x1 16x1

7.7 3.1 1.3 1.7 1.4 0 -

5.2

8.4 3.6 1.5 2.0 1.6 0 -

6.1

ns ns ns ns ns ns ns

TWODS

Data valid after clock K

Notes: 1. Read Operation timing for 16 x 1 dual-port RAM option is identical to 16 x 2 single-port RAM timing

Spartan-XL Family CLB RAM Synchronous (Edge-Triggered) Write Timing

Single Port
TWPS WCLK (K) TWSS WE TDSS DATA IN TASS ADDRESS TAHS
ADDRESS WCLK (K)

Dual Port
TWPDS

TWHS
WE

TWSDS

TWHDS

TDHS
DATA IN

TDSDS

TDHDS

TASDS

TAHDS

TILO DATA OUT

TILO TWOS
OLD NEW

TILO DATA OUT

TILO TWODS
OLD NEW
DS060_34_011300

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Spartan and Spartan-XL FPGA Families Data Sheet

Spartan-XL Family Pin-to-Pin Output Parameter Guidelines

All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operSpartan-XL Family Output Flip-Flop, Clock-to-Out Speed Grade -5 Symbol
Global Clock to Output using OFF

ating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading.

-4 Max 5.2 5.5 5.8 6.2 6.5 1.7 Units ns ns ns ns ns ns

Description Fast

Device XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL

Max 4.6 4.9 5.2 5.5 5.8 1.5

TICKOF

Slew Rate Adjustment

TSLOW

For Output SLOW option add

All Devices

Notes: 1. Output delays are representative values where one global clock input drives one vertical clock line in each accessible column,and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load. 3. OFF = Output Flip Flop

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Spartan and Spartan-XL FPGA Families Data Sheet

Spartan-XL Family Pin-to-Pin Input Parameter Guidelines

All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operSpartan-XL Family Setup and Hold Speed Grade -5 Symbol Description Input Setup/Hold Times Using Global Clock and IFF TSUF/THF No Delay Device XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL TSU/TH Full Delay XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL Max 1.1/2.0 1.0/2.2 0.9/2.4 0.8/2.6 0.7/2.8 3.9/0.0 4.1/0.0 4.3/0.0 4.5/0.0 4.7/0.0 -4 Max 1.6/2.6 1.5/2.8 1.4/3.0 1.3/3.2 1.2/3.4 5.1/0.0 5.3/0.0 5.5/0.0 5.7/0.0 5.9/0.0 Units ns ns ns ns ns ns ns ns ns ns ating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading.

Notes: 1. IFF = Input Flip-Flop or Latch 2. Setup time is measured with the fastest route and the lightest load. Hold time is measured using the furthest distance and a reference load of one clock pin per IOB/CLB.

Capacitive Load Factor Figure 35 shows the relationship between I/O output delay and load capacitance. It allows a user to adjust the specified output delay if the load capacitance is different than 50 pF. For example, if the actual load capacitance is 120 pF, add 2.5 ns to the specified delay. If the load capacitance is 20 pF, subtract 0.8 ns from the specified output delay. Figure 35 is usable over the specified operating conditions of voltage and temperature and is independent of the output slew rate control.
3

Delta Delay (ns)

-1

-2 0 20 40 60 80 100 120 140

Capacitance (pF)
DS060_35_080400

Figure 35: Delay Factor at Various Capacitive Loads

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Spartan and Spartan-XL FPGA Families Data Sheet

Spartan-XL Family IOB Input Switching Characteristic Guidelines

All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Speed Grade -5 Symbol
Setup Times

-4 Max Min Max Units

Description

Device

Min

TECIK TPICK TPOCK

Clock Enable (EC) to Clock (IK) Pad to Clock (IK), no delay Pad to Fast Capture Latch Enable (OK), no delay

All devices All devices All devices

0.0 1.0 0.7

0.0 1.2 0.8

ns ns ns

Hold Times

All Hold Times

Propagation Delays

All devices

0.0

0.0

ns

TPID TPLI TIKRI TIKLI TDelay

Pad to I1, I2 Pad to I1, I2 via transparent input latch, no delay Clock (IK) to I1, I2 (flip-flop) Clock (IK) to I1, I2 (latch enable, active Low)

All devices All devices All devices All devices

0.9 2.1 1.0 1.1

1.1 2.5 1.1 1.2

ns ns ns ns

Delay Adder for Input with Full Delay Option

TPICKD = TPICK + TDelay TPDLI = TPLI + TDelay

XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL

4.0 4.8 5.0 5.5 6.5

4.7 5.6 5.9 6.5 7.6

ns ns ns ns ns

Global Set/Reset

TMRW TRRI

Minimum GSR pulse width Delay from GSR input to any Q

All devices XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL

10.5 -

9.0 9.5 10.0 11.0 12.0

11.5 -

10.5 11.0 11.5 12.5 13.5

ns ns ns ns ns ns

Notes: 1. Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock input, see the pin-to-pin parameters in the Pin-to-Pin Input Parameters table. 2. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.

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Spartan and Spartan-XL FPGA Families Data Sheet

Spartan-XL Family IOB Output Switching Characteristic Guidelines

All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values are expressed in nanoseconds unless otherwise noted. Speed Grade -5 Symbol Description Propagation Delays TOKPOF Clock (OK) to Pad, fast TOPF TTSHZ TTSONF TOFPF TOKFPF Output (O) to Pad, fast 3-state to Pad High-Z (slew-rate independent) 3-state to Pad active and valid, fast Output (O) to Pad via Output Mux, fast Select (OK) to Pad via Output Mux, fast Device All devices All devices All devices All devices All devices All devices All devices All devices All devices All devices All devices All devices XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL Min 0.5 0.0 0.0 0.1 10.5 Max 3.2 2.5 2.8 2.6 3.7 3.3 1.5 11.9 12.4 12.9 13.9 14.9 Min 0.5 0.0 0.0 0.2 11.5 -4 Max 3.7 2.9 3.3 3.0 4.4 3.9 1.7 14.0 14.5 15.0 16.0 17.0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

TSLOW For Output SLOW option add Setup and Hold Times TOOK Output (O) to clock (OK) setup time TOKO TECOK Output (O) to clock (OK) hold time Clock Enable (EC) to clock (OK) setup time

TOKEC Clock Enable (EC) to clock (OK) hold time Global Set/Reset TMRW Minimum GSR pulse width TRPO Delay from GSR input to any Pad

Notes: 1. Output timing is measured at ~50% VCC threshold, with 50 pF external capacitive loads including test fixture. Slew-rate limited output rise/fall times are approximately two times longer than fast output rise/fall times. 2. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.

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Spartan and Spartan-XL FPGA Families Data Sheet

Pin Descriptions
There are three types of pins in the Spartan/XL devices: Permanently dedicated pins User I/O pins that can have special functions Unrestricted user-programmable I/O pins. Any user I/O can be configured to drive the Global Set/Reset net GSR or the global three-state net GTS. See Global Signals: GSR and GTS, page 20 for more information. Device pins for Spartan/XL devices are described in Table 18. Some Spartan-XL devices are available in Pb-free package options. The Pb-free package options have the same pinouts as the standard package options.

Before and during configuration, all outputs not used for the configuration process are 3-stated with the I/O pull-up resistor network activated. After configuration, if an IOB is unused it is configured as an input with the I/O pull-up resistor network remaining activated. Table 18: Pin Descriptions I/O During Config. I/O After Config.

Pin Name

Pin Description

Permanently Dedicated Pins

VCC

Eight or more (depending on package) connections to the nominal +5V supply voltage (+3.3V for Spartan-XL devices). All must be connected, and each must be decoupled with a 0.01 0.1 F capacitor to Ground. Eight or more (depending on package type) connections to Ground. All must be connected. During configuration, Configuration Clock (CCLK) is an output in Master mode and is an input in Slave mode. After configuration, CCLK has a weak pull-up resistor and can be selected as the Readback Clock. There is no CCLK High or Low time restriction on Spartan/XL devices, except during Readback. See Violating the Maximum High and Low Time Specification for the Readback Clock, page 39 for an explanation of this exception. DONE is a bidirectional signal with an optional internal pull-up resistor. As an open-drain output, it indicates the completion of the configuration process. As an input, a Low level on DONE can be configured to delay the global logic initialization and the enabling of outputs. The optional pull-up resistor is selected as an option in the program that creates the configuration bitstream. The resistor is included by default.

GND CCLK

X I or O

X I

DONE

I/O

PROGRAM

PROGRAM is an active Low input that forces the FPGA to clear its configuration memory. It is used to initiate a configuration cycle. When PROGRAM goes High, the FPGA finishes the current clear cycle and executes another complete clear cycle, before it goes into a WAIT state and releases INIT. The PROGRAM pin has a permanent weak pull-up, so it need not be externally pulled up to VCC.

MODE (Spartan) M0, M1 (Spartan-XL)

The Mode input(s) are sampled after INIT goes High to determine the configuration mode to be used. During configuration, these pins have a weak pull-up resistor. For the most popular configuration mode, Slave Serial, the mode pins can be left unconnected. For Master Serial mode, connect the Mode/M0 pin directly to system ground.

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Spartan and Spartan-XL FPGA Families Data Sheet

Table 18: Pin Descriptions (Continued) I/O During Config. I I/O After Config. I

Pin Name PWRDWN

Pin Description PWRDWN is an active Low input that forces the FPGA into the Power Down state and reduces power consumption. When PWRDWN is Low, the FPGA disables all I/O and initializes all flip-flops. All inputs are interpreted as Low independent of their actual level. VCC must be maintained, and the configuration data is maintained. PWRDWN halts configuration if asserted before or during configuration, and re-starts configuration when removed. When PWRDWN returns High, the FPGA becomes operational by first enabling the inputs and flip-flops and then enabling the outputs. PWRDWN has a default internal pull-up resistor.

User I/O Pins That Can Have Special Functions

TDO

If boundary scan is used, this pin is the Test Data Output. If boundary scan is not used, this pin is a 3-state output without a register, after configuration is completed. To use this pin, place the library component TDO instead of the usual pad symbol. An output buffer must still be used.

TDI, TCK, TMS

I/O or I (JTAG)

If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select inputs respectively. They come directly from the pads, bypassing the IOBs. These pins can also be used as inputs to the CLB logic after configuration is completed. If the BSCAN symbol is not placed in the design, all boundary scan functions are inhibited once configuration is completed, and these pins become user-programmable I/O. In this case, they must be called out by special library elements. To use these pins, place the library components TDI, TCK, and TMS instead of the usual pad symbols. Input or output buffers must still be used.

HDC

I/O

High During Configuration (HDC) is driven High until the I/O go active. It is available as a control output indicating that configuration is not yet completed. After configuration, HDC is a user-programmable I/O pin. Low During Configuration (LDC) is driven Low until the I/O go active. It is available as a control output indicating that configuration is not yet completed. After configuration, LDC is a user-programmable I/O pin. Before and during configuration, INIT is a bidirectional signal. A 1 k to 10 k external pull-up resistor is recommended. As an active Low open-drain output, INIT is held Low during the power stabilization and internal clearing of the configuration memory. As an active Low input, it can be used to hold the FPGA in the internal WAIT state before the start of configuration. Master mode devices stay in a WAIT state an additional 30 to 300 s after INIT has gone High. During configuration, a Low on this output indicates that a configuration data error has occurred. After the I/O go active, INIT is a user-programmable I/O pin.

LDC

I/O

INIT

I/O

I/O

PGCK1 PGCK4 (Spartan)

Weak Pull-up

I or I/O

Four Primary Global inputs each drive a dedicated internal global net with short delay and minimal skew. If not used to drive a global buffer, any of these pins is a user-programmable I/O. The PGCK1-PGCK4 pins drive the four Primary Global Buffers. Any input pad symbol connected directly to the input of a BUFGP symbol is automatically placed on one of these pins.

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Spartan and Spartan-XL FPGA Families Data Sheet Table 18: Pin Descriptions (Continued) I/O During Config. Weak Pull-up (except SGCK4 is DOUT) I/O After Config. I or I/O

Pin Name SGCK1 SGCK4 (Spartan)

Pin Description Four Secondary Global inputs each drive a dedicated internal global net with short delay and minimal skew. These internal global nets can also be driven from internal logic. If not used to drive a global net, any of these pins is a user-programmable I/O pin. The SGCK1-SGCK4 pins provide the shortest path to the four Secondary Global Buffers. Any input pad symbol connected directly to the input of a BUFGS symbol is automatically placed on one of these pins.

GCK1 GCK8 (Spartan-XL)

Weak Pull-up (except GCK6 is DOUT)

I or I/O

Eight Global inputs each drive a dedicated internal global net with short delay and minimal skew. These internal global nets can also be driven from internal logic. If not used to drive a global net, any of these pins is a user-programmable I/O pin. The GCK1-GCK8 pins provide the shortest path to the eight Global Low-Skew Buffers. Any input pad symbol connected directly to the input of a BUFGLS symbol is automatically placed on one of these pins.

CS1 (Spartan-XL) D0-D7 (Spartan-XL) DIN

I I I

I/O I/O I/O

During Express configuration, CS1 is used as a serial-enable signal for daisy-chaining. During Express configuration, these eight input pins receive configuration data. After configuration, they are user-programmable I/O pins. During Slave Serial or Master Serial configuration, DIN is the serial configuration data input receiving data on the rising edge of CCLK. After configuration, DIN is a user-programmable I/O pin. During Slave Serial or Master Serial configuration, DOUT is the serial configuration data output that can drive the DIN of daisy-chained slave FPGAs. DOUT data changes on the falling edge of CCLK, one-and-a-half CCLK periods after it was received at the DIN input. In Spartan-XL family Express mode, DOUT is the status output that can drive the CS1 of daisy-chained FPGAs, to enable and disable downstream devices. After configuration, DOUT is a user-programmable I/O pin.

DOUT

I/O

Unrestricted User-Programmable I/O Pins

I/O

Weak Pull-up

I/O

These pins can be configured to be input and/or output after configuration is completed. Before configuration is completed, these pins have an internal high-value pull-up resistor network that defines the logic level as High.

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Device-Specific Pinout Tables

Device-specific tables include all packages for each Spartan and Spartan-XL device. They follow the pad locations around the die, and include boundary scan register locations. Some Spartan-XL devices are available in Pb-free package options. The Pb-free package options have the same pinouts as the standard package options.

XCS05 and XCS05XL Device Pinouts

XCS05/XL Pad Name Not Connected(1), PWRDWN(2) I/O, PGCK2(1), GCK3 (2) I/O (HDC) I/O I/O (LDC) I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK3(1), GCK4(2) GND DONE VCC PROGRAM I/O (D7(2)) I/O, PGCK3(1), GCK5(2) I/O (D6(2)) I/O I/O (D5(2)) I/O I/O I/O I/O (D4(2)) I/O VCC GND I/O (D3(2)) I/O I/O I/O (D2(2)) I/O I/O (D1(2)) PC84(4) P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 VQ100 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 Bndry Scan 126(1) 127(3) 130(3) 133(3) 136(3) 139(3) 142(3) 145(3) 148(3) 151(3) 154(3) 157(3) 160(3) 163(3) 166(3) 169(3) 172(3) 175(3) 178(3) 181(3) 184(3) 187(3) 190(3) 193(3) 196(3) 199(3) 202(3) 205(3) 208(3) 211(3) 214(3) 217(3) 220(3) 223(3) 229(3) 232(3) 235(3)
65

XCS05 and XCS05XL Device Pinouts

XCS05/XL Pad Name VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK1(1), GCK8(2) VCC GND I/O, PGCK1(1), GCK1(2) I/O I/O, TDI I/O, TCK I/O, TMS I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK2(1), GCK2(2) Not Connected(1), M1(2) GND MODE(1), M0 (2) VCC PC84(4) P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 VQ100 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 Bndry Scan 32 35 38 41 44 47 50 53 56 59 62 65 68 71 74 77 83 86 89 92 95 98 104 107 110 113 116 119 122 125 -

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Spartan and Spartan-XL FPGA Families Data Sheet

XCS05 and XCS05XL Device Pinouts

XCS05/XL Pad Name I/O I/O (D0(2), DIN) I/O, SGCK4(1), GCK6(2) (DOUT) CCLK VCC O, TDO GND I/O I/O, PGCK4(1), GCK7(2) I/O (CS1(2)) I/O I/O I/O I/O I/O I/O I/O GND PC84(4) P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P1 VQ100 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 Bndry Scan 238(3) 241(3) 244(3) 0 2 5 8 11 14 17 20 23 26 29 -

XCS10 and XCS10XL Device Pinouts

XCS10/XL Bndry Pad Name PC84(4) VQ100 CS144(2,4) TQ144 Scan I/O, P10 P99 A2 P143 83 SGCK1(1) GCK8(2) VCC P11 P100 B2 P144 GND P12 P1 A1 P1 I/O, P13 P2 B1 P2 86 PGCK1(1) GCK1(2) I/O P14 P3 C2 P3 89 I/O C1 P4 92 I/O D4 P5 95 I/O, TDI P15 P4 D3 P6 98 I/O, TCK P16 P5 D2 P7 101 GND D1 P8 I/O E4 P9 104 I/O E3 P10 107 I/O, TMS P17 P6 E2 P11 110 I/O P18 P7 E1 P12 113 I/O F4 P13 116 I/O P8 F3 P14 119 I/O P19 P9 F2 P15 122 I/O P20 P10 F1 P16 125 GND P21 P11 G2 P17 VCC P22 P12 G1 P18 I/O P23 P13 G3 P19 128 I/O P24 P14 G4 P20 131 I/O P15 H1 P21 134 I/O H2 P22 137 I/O P25 P16 H3 P23 140 I/O P26 P17 H4 P24 143 I/O J1 P25 146 I/O J2 P26 149 GND J3 P27 I/O P27 P18 J4 P28 152 I/O P19 K1 P29 155 I/O K2 P30 158 I/O K3 P31 161 I/O P28 P20 L1 P32 164 I/O, P29 P21 L2 P33 167 SGCK2(1) GCK2(2) P30 P22 L3 P34 170 Not Connected(1) M1(2) GND P31 P23 M1 P35 (1), MODE P32 P24 M2 P36 173 M0(2)

Notes: 1. 5V Spartan family only 2. 3V Spartan-XL family only 3. The PWRDWN on the XCS05XL is not part of the Boundary Scan chain. For the XCS05XL, subtract 1 from all Boundary Scan numbers from GCK3 on (127 and higher). 4. PC84 package discontinued by PDN2004-01

XCS10 and XCS10XL Device Pinouts

XCS10/XL Bndry Pad Name PC84(4) VQ100 CS144(2,4) TQ144 Scan VCC P2 P89 D7 P128 I/O P3 P90 A6 P129 44 I/O P4 P91 B6 P130 47 I/O P92 C6 P131 50 I/O P93 D6 P132 53 I/O P5 P94 A5 P133 56 I/O P6 P95 B5 P134 59 I/O C5 P135 62 I/O D5 P136 65 GND A4 P137 I/O P7 P96 B4 P138 68 I/O P8 P97 C4 P139 71 I/O A3 P140 74 I/O B3 P141 77 I/O P9 P98 C3 P142 80

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XCS10 and XCS10XL Device Pinouts

XCS10/XL Bndry Pad Name PC84(4) VQ100 CS144(2,4) TQ144 Scan VCC P33 P25 N1 P37 P34 P26 N2 P38 174 (1) Not Connected(1)
PWRDWN(2
)

XCS10 and XCS10XL Device Pinouts

XCS10/XL Bndry Pad Name PC84(4) VQ100 CS144(2,4) TQ144 Scan I/O, P57 P54 L13 P76 262 (3) (1) PGCK3 GCK5(2) I/O K10 P77 265 (3) I/O K11 P78 268 (3) (2)) I/O (D6 P58 P55 K12 P79 271 (3) I/O P56 K13 P80 274 (3) GND J10 P81 I/O J11 P82 277 (3) I/O J12 P83 280 (3) (2)) I/O (D5 P59 P57 J13 P84 283 (3) I/O P60 P58 H10 P85 286 (3) I/O P59 H11 P86 289 (3) I/O P60 H12 P87 292 (3) I/O (D4(2)) P61 P61 H13 P88 295 (3) I/O P62 P62 G12 P89 298 (3) VCC P63 P63 G13 P90 GND P64 P64 G11 P91 I/O (D3(2)) P65 P65 G10 P92 301 (3) I/O P66 P66 F13 P93 304 (3) I/O P67 F12 P94 307 (3) I/O F11 P95 310 (3) I/O (D2(2)) P67 P68 F10 P96 313 (3) I/O P68 P69 E13 P97 316 (3) I/O E12 P98 319 (3) I/O E11 P99 322 (3) GND E10 P100 P69 P70 D13 P101 325 (3) I/O (D1(2)) I/O P70 P71 D12 P102 328 (3) I/O D11 P103 331 (3) I/O C13 P104 334 (3) (2), I/O (D0 P71 P72 C12 P105 337 (3) DIN) P72 P73 C11 P106 340 (3) I/O, (1) SGCK4 GCK6(2) (DOUT) CCLK P73 P74 B13 P107 VCC P74 P75 B12 P108 O, TDO P75 P76 A13 P109 0 GND P76 P77 A12 P110 I/O P77 P78 B11 P111 2 I/O, P78 P79 A11 P112 5 PGCK4(1) GCK7(2) I/O D10 P113 8 I/O C10 P114 11 I/O (CS1(2)) P79 P80 B10 P115 14

I/O, PGCK2(1) GCK3(2) I/O (HDC) I/O I/O I/O I/O (LDC) GND I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O, SGCK3(1) GCK4(2) GND DONE VCC
PROGRAM

P35

P27

M3

P39

175(3)

P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51

P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48

N3 K4 L4 M4 N4 K5 L5 M5 N5 K6 L6 M6 N6 M7 N7 L7 K7 N8 M8 L8 K8 N9 M9 L9 K9 N10 M10 L10 N11 M11 L11

P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70

178 (3) 181 (3) 184 (3) 187 (3) 190 (3) 193 (3) 196 (3) 199 (3) 202 (3) 205 (3) 208 (3) 211 (3) 214 (3) 217 (3) 220 (3) 223 (3) 226 (3) 229 (3) 232 (3) 235 (3) 238 (3) 241 (3) 244 (3) 247 (3) 250 (3) 253 (3) 256 (3)

I/O (D7(2))

P52 P53 P54 P55 P56

P49 P50 P51 P52 P53

N12 M12 N13 M13 L12

P71 P72 P73 P74 P75

259 (3)

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Spartan and Spartan-XL FPGA Families Data Sheet

XCS10 and XCS10XL Device Pinouts

XCS10/XL Bndry Pad Name PC84(4) VQ100 CS144(2,4) TQ144 Scan I/O P80 P81 A10 P116 17 GND C9 P118 I/O B9 P119 20 I/O A9 P120 23 I/O P81 P82 D8 P121 26 I/O P82 P83 C8 P122 29 I/O P84 B8 P123 32 I/O P85 A8 P124 35 I/O P83 P86 B7 P125 38 I/O P84 P87 A7 P126 41 GND P1 P88 C7 P127 Notes:

Additional XCS10/XL Package Pins

TQ144 Not Connected Pins P117 5/5/97 CS144 Not Connected Pins D9 4/28/99 -

1. 2. 3. 4.

5V Spartan family only 3V Spartan-XL family only The PWRDWN on the XCS10XL is not part of the Boundary Scan chain. For the XCS10XL, subtract 1 from all Boundary Scan numbers from GCK3 on (175 and higher). PC84 and CS144 packages discontinued by PDN2004-01

XCS20 and XCS20XL Device Pinouts XCS20 and XCS20XL Device Pinouts
XCS20/XL Pad Name VCC I/O I/O I/O I/O I/O I/O I/O I/O VCC(2) I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O VQ100 CS144(2,4) P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 D7 A6 B6 C6 D6 A5 B5 C5 D5 A4 B4 C4 A3 B3 C3 TQ144 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 PQ208 P183 P184 P185 P186 P187 P188 P189 P190 P191 P192 P193 P194 P195 P196 P197 P198 P199 P200 P201 P204 P205 P206 Bndry Scan 62 65 68 71 74 77 80 83 86 89 92 95 98 101 104 107 110 113 116 XCS20/XL Pad Name I/O, SGCK1(1), GCK8(2) VCC GND I/O, PGCK1(1), GCK1(2) I/O I/O I/O I/O, TDI I/O, TCK I/O I/O I/O I/O GND I/O I/O I/O, TMS I/O VCC(2) I/O I/O VQ100 CS144(2,4) P99 A2 TQ144 P143 PQ208 P207 Bndry Scan 119

P100 P1 P2

B2 A1 B1

P144 P1 P2

P208 P1 P2

122

P3 P4 P5 P6 P7 -

C2 C1 D4 D3 D2 D1 E4 E3 E2 E1 -

P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 -

P3 P4 P5 P6 P7 P8 P9 P10 P11 P13 P14 P15 P16 P17 P18 P19 P20

125 128 131 134 137 140 143 146 149 152 155 158 161 164 167

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Spartan and Spartan-XL FPGA Families Data Sheet

XCS20 and XCS20XL Device Pinouts

XCS20/XL Pad Name I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O VCC(2) I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK2(1), GCK2(2) Not Connected(1) M1(2) GND MODE(1), M0(2) VCC Not Connected(1) PWRDWN(2) I/O, PGCK2(1), GCK3(2) I/O (HDC) I/O I/O I/O P27 M3 P39 P55 247 (3) VQ100 CS144(2,4) P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 F4 F3 F2 F1 G2 G1 G3 G4 H1 H2 H3 H4 J1 J2 J3 J4 K1 K2 K3 L1 L2 TQ144 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 PQ208 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 Bndry Scan 170 173 176 179 182 185 188 191 194 197 200 203 206 209 212 215 218 221 224 227 230 233 236 239

XCS20 and XCS20XL Device Pinouts

XCS20/XL Pad Name I/O (LDC) I/O I/O I/O I/O GND I/O I/O I/O I/O VCC(2) I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O VCC(2) I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK3(1), GCK4(2) GND DONE VCC VQ100 CS144(2,4) P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 N4 K5 L5 M5 N5 K6 L6 M6 N6 M7 N7 L7 K7 N8 M8 L8 K8 N9 M9 L9 K9 N10 M10 L10 N11 M11 L11 TQ144 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 PQ208 P60 P61 P62 P63 P64 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 Bndry Scan 262 (3) 265 (3) 268 (3) 271 (3) 274 (3) 277 (3) 280 (3) 283 (3) 286 (3) 289 (3) 292 (3) 295 (3) 298 (3) 301 (3) 304 (3) 307 (3) 310 (3) 313 (3) 316 (3) 319 (3) 322 (3) 325 (3) 328 (3) 331 (3) 334 (3) 337 (3) 340 (3) 343 (3) 346 (3) 349 (3) 352 (3) 355 (3) 358 (3) 361 (3) 364 (3)

P22

L3

P34

P50

242

P23 P24 P25 P26

M1 M2 N1 N2

P35 P36 P37 P38

P51 P52 P53 P54

245 246 (1)

P28 P29

N3 K4 L4 M4

P40 P41 P42 P43

P56 P57 P58 P59

250 (3) 253 (3) 256 (3) 259 (3)

P49 P50 P51

N12 M12 N13

P71 P72 P73

P103 P104 P105

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Spartan and Spartan-XL FPGA Families Data Sheet

XCS20 and XCS20XL Device Pinouts

XCS20/XL Pad Name PROGRAM I/O (D7(2)) I/O, PGCK3(1), GCK5(2) I/O I/O I/O (D6(2)) I/O I/O I/O I/O I/O GND I/O I/O VCC(2) I/O I/O I/O I/O I/O I/O I/O (D4(2)) I/O VCC GND I/O (D3(2)) I/O I/O I/O I/O I/O I/O (D2(2)) I/O VCC(2) I/O I/O GND I/O I/O I/O I/O I/O (D1(2)) I/O I/O (D5(2)) VQ100 CS144(2,4) P52 P53 P54 M13 L12 L13 TQ144 P74 P75 P76 PQ208 P106 P107 P108 Bndry Scan 367
(3)

XCS20 and XCS20XL Device Pinouts

XCS20/XL Pad Name I/O I/O (D0(2), DIN) I/O, SGCK4(1), GCK6(2) (DOUT) CCLK VCC O, TDO GND I/O I/O, PGCK4(1), GCK7(2) I/O I/O I/O (CS1(2))
(3)

VQ100 CS144(2,4) P72 P73 C13 C12 C11

TQ144 P104 P105 P106

PQ208 P152 P153 P154

Bndry Scan 478 (3) 481 (3) 484 (3)

370 (3)

P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 -

K10 K11 K12 K13 J10 J11 J12 J13 H10 H11 H12 H13 G12 G13 G11 G10 F13 F12 F11 F10 E13 E12 E11 E10 D13 D12 D11

P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103

P109 P110 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P145 P146 P147 P148 P149 P150 P151

373 (3) 376 (3) 379 (3) 382 (3) 385 (3) 388 (3) 391 (3) 394 (3) 397 (3) 400 (3) 403 406 (3) 409 (3) 412 (3) 415 (3) 418 (3) 421 (3) 424 (3) 427 (3) 430 (3) 433 (3) 436 (3) 439 (3) 442 (3) 445 (3) 448 (3) 451 (3) 454 (3) 457 (3) 460 (3) 463 (3) 466 (3) 469 (3) 472 (3) 475 (3)

P74 P75 P76 P77 P78 P79

B13 B12 A13 A12 B11 A11

P107 P108 P109 P110 P111 P112

P155 P156 P157 P158 P159 P160

0 2 5

P80 P81 P82 P83 P84 P85 P86 P87 P88

D10 C10 B10 A10 D9 C9 B9 A9 D8 C8 B8 A8 B7 A7 C7

P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127

P161 P162 P163 P164 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 P181 P182

8 11 14 17 20 23 26 29 32 35 38 41 44 47 50 53 56 59 -

I/O I/O I/O I/O I/O GND I/O I/O VCC(2) I/O I/O I/O I/O I/O I/O I/O I/O GND
2/8/00

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Spartan and Spartan-XL FPGA Families Data Sheet

Additional XCS20/XL Package Pins

PQ208 Not Connected Pins P33 (1) P39 P111 P121(1) P192(1) P202

P12 P86 (1) P165

9/16/98

P18 (1) P92 P173(1)

P65 P140(1) P203

P71 (1) P144 -

Notes: 1. 5V Spartan family only 2. 3V Spartan-XL family only 3. The PWRDWN on the XCS20XL is not part of the Boundary Scan chain. For the XCS20XL, subtract 1 from all Boundary Scan numbers from GCK3 on (247 and higher). 4. CS144 package discontinued by PDN2004-01

XCS30 and XCS30XL Device Pinouts

XCS30/XL Pad Name VCC I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK1(1), GCK8(2) VCC GND I/O, PGCK1(1), GCK1(2) I/O I/O VQ100(5) P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P1 P2 P3 TQ144 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P1 P2 P3 P4 PQ208 P183 P184 P185 P186 P187 P188 P189 P190 P191 P192 P193 P194 P195 P196 P197 P198 P199 P200 P201 P202 P203 P204 P205 P206 P207 P208 P1 P2 P3 P4 PQ240 P212 P213 P214 P215 P216 P217 P218 P220 P221 P222 P223 P224 P225 P226 P227 P228 P229 P230 P231 P232 P233 P234 P235 P236 P237 P238 P239 P240 P1 P2 P3 P4 BG256(5) VCC(4) C10 D10 A9 B9 C9 D9 A8 B8 VCC(4) A6 C7 B6 A5 GND(4) C6 B5 A4 C5 B4 A3 D5 C4 B3 B2 A2 C3 VCC(4) GND(4) B1 C2 D2 CS280(2,5) C10 D10 E10 A9 B9 C9 D9 A8 B8 A7 B7 C7 D7 A6 GND(4) B6 C6 D6 E6 A5 C5 B4 C4 A3 A2 B3 B2 A1 GND(4) C3 C2 B1 Bndry Scan 74 77 80 83 86 89 92 95 98 101 104 107 110 113 116 119 122 125 128 131 134 137 140 143 146 149 152

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XCS30 and XCS30XL Device Pinouts (Continued)

XCS30/XL Pad Name I/O I/O, TDI I/O, TCK I/O I/O I/O I/O I/O I/O GND I/O I/O I/O, TMS I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VQ100(5) P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 TQ144 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 PQ208 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 PQ240 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 BG256(5) D3 E4 C1 D1 E3 E2 E1 F3 F2 GND(4) G3 G2 G1 H3 VCC(4) H2 H1 J2 J1 K2 K3 K1 L1 GND(4) VCC(4) L2 L3 L4 M1 M2 M3 N1 N2 VCC(4) P1 P2 R1 P3 GND(4) T1 R3 T2 U1 T3 U2 CS280(2,5) C1 D4 D3 E2 E4 E1 F5 F3 F2 GND(4) F4 F1 G3 G2 G1 G4 H1 H4 J1 J2 J3 J4 K1 GND(4) K2 K3 K4 K5 L1 L2 L3 M2 M3 M4 N1 N2 N3 N4 GND(4) P1 P2 P3 P4 P5 R1 Bndry Scan 155 158 161 164 167 170 173 176 179 182 185 188 191 194 197 200 203 206 209 212 215 218 221 224 227 230 233 236 239 242 245 248 251 254 257 260 263 266 269

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Spartan and Spartan-XL FPGA Families Data Sheet

XCS30 and XCS30XL Device Pinouts (Continued)

XCS30/XL Pad Name I/O I/O I/O I/O I/O I/O, SGCK2(1), GND MODE(1), VCC Not Connected (1), PWRDWN(2) I/O, PGCK2(1), GCK3(2) I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 Y2 W4 V4 U5 Y3 Y4 V5 W5 Y5 V6 W6 Y6 GND(4) W7 Y7 V8 W8 VCC(4) Y8 U9 Y9 W10 V10 Y10 Y11 W11 VCC(4) GND(4) V11 U11 Y12 W12 V12 W2 W3 T4 U4 V4 W4 T5 W5 R6 U6 V6 T6 GND(4) W6 U7 V7 W7 T7 W8 U8 W9 V9 U9 T9 W10 V10 U10 GND(4) T10 R10 W11 V11 U11 295 (3) 298 (3) 301 (3) 304 (3) 307 (3) 310 (3) 313 (3) 316 (3) 319 (3) 322 (3) 325 (3) 328 (3) 331 (3) 334 (3) 337 (3) 340 (3) 343 (3) 346 (3) 349 (3) 352 (3) 355 (3) 358 (3) 361 (3) 364 (3) 367 (3) 370 (3) 373 (3) 376 (3) 379 (3) M0(2) GCK2(2) Not Connected(1), M1(2) VQ100(5) P18 P19 P20 P21 P22 P23 P24 P25 P26 TQ144 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 PQ208 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 PQ240 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 BG256(5) V1 T4 U3 V2 W1 V3 W2 GND(4) Y1 VCC(4) W3 CS280(2,5) T1 T2 T3 U1 V1 U2 V2 GND(4) W1 U3 V3 Bndry Scan 272 275 278 281 284 287 290 293 294 (1)

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Spartan and Spartan-XL FPGA Families Data Sheet

XCS30 and XCS30XL Device Pinouts (Continued)

XCS30/XL Pad Name I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK3(1), GCK4(2) GND DONE VCC PROGRAM I/O (D7(2)) I/O, PGCK3(1), GCK5(2) I/O I/O I/O I/O I/O (D6(2)) I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O (D5(2)) I/O VQ100(5) P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 TQ144 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 PQ208 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 PQ240 P97 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 BG256(5) U12 V13 Y14 VCC(4) Y15 V14 W15 Y16 GND(4) V15 W16 Y17 V16 W17 Y18 U16 V17 W18 Y19 V18 W19 GND(4) Y20 VCC(4) V19 U19 U18 T17 V20 U20 T18 T19 T20 R18 R19 R20 P18 GND(4) P20 N18 N19 N20 VCC(4) M17 M18 CS280(2,5) T11 U12 T12 W13 V13 U13 T13 W14 GND(4) V14 U14 T14 R14 W15 U15 V16 U16 W17 W18 V17 V18 GND(4) W19 U17 U18 V19 U19 T16 T17 T18 T19 R16 R19 P15 P17 P18 P16 GND(4) P19 N17 N18 N19 N16 M19 M17 Bndry Scan 382 (3) 385 (3) 388 (3) 391 (3) 394 (3) 397 (3) 400 (3) 403 (3) 406 (3) 409 (3) 412 (3) 415 (3) 418 (3) 421 (3) 424 (3) 427 (3) 430 (3) 433 (3) 436 (3) 439 (3) 442 (3) 445 (3) 448 (3) 451 (3) 454 (3) 457 (3) 460 (3) 463 (3) 466 (3) 469 (3) 472 (3) 475 (3) 478 (3) 481 (3) 484 (3) 487 (3) 490 (3)

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DS060 (v1.8) June 26, 2008 Product Specification

Spartan and Spartan-XL FPGA Families Data Sheet

XCS30 and XCS30XL Device Pinouts (Continued)

XCS30/XL Pad Name I/O I/O I/O I/O I/O (D4(2)) I/O VCC GND I/O (D3(2)) I/O I/O I/O I/O I/O I/O (D2(2)) I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O (D1(2)) I/O I/O I/O I/O (D0(2), DIN) I/O, SGCK4(1), GCK6(2) (DOUT) CCLK VCC O, TDO GND I/O I/O, PGCK4(1), GCK7(2) I/O I/O I/O (CS1)(2) I/O I/O P74 P75 P76 P77 P78 P79 P80 P81 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P155 P156 P157 P158 P159 P160 P161 P162 P163 P164 P165 P179 P180 P181 P182 P183 P184 P185 P186 P187 P188 P189 A20 VCC(4) A19 GND(4) B18 B17 C17 D16 A18 A17 C16 A19 C17 B17 GND(4) A18 A17 D16 C16 B16 A16 D15 0 2 5 8 11 14 17 20 VQ100(5) P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 TQ144 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 PQ208 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 PQ240 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 BG256(5) M20 L19 L18 L20 K20 K19 VCC(4) GND(4) K18 K17 J20 J19 J18 J17 H19 H18 VCC(4) G19 F20 G18 F19 GND(4) F18 E19 D20 E18 D19 C20 E17 D18 C19 B20 C18 B19 CS280(2,5) L19 L18 L17 L16 K19 K18 K17 GND(4) K16 K15 J19 J18 J17 J16 H17 H16 G19 G18 G17 G16 F19 GND(4) F18 F17 F16 F15 E19 E17 E16 D19 C19 B19 C18 B18 Bndry Scan 493 (3) 496 (3) 499 (3) 502 (3) 505 (3) 508 (3) 511 (3) 514 (3) 517 (3) 520 (3) 523 (3) 526 (3) 529 (3) 532 (3) 535 (3) 538 (3) 541 (3) 544 (3) 547 (3) 550 (3) 553 (3) 556 (3) 559 (3) 562 (3) 565 (3) 568 (3) 571 (3) 574 (3) 577 (3) 580 (3)

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Spartan and Spartan-XL FPGA Families Data Sheet

XCS30 and XCS30XL Device Pinouts (Continued)

XCS30/XL Pad Name I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O GND
2/8/00

VQ100(5) P82 P83 P84 P85 P86 P87 P88

TQ144 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127

PQ208 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 P181 P182

PQ240 P190 P191 P192 P193 P194 P196 P197 P198 P199 P200 P201 P202 P203 P205 P206 P207 P208 P209 P210 P211

BG256(5) B16 A16 C15 B15 A15 GND(4) B14 A14 C13 B13 VCC(4) C12 B12 A12 B11 C11 A11 A10 B10 GND(4)

CS280(2,5) A15 E14 C14 B14 D14 GND(4) A14 C13 B13 A13 D13 B12 D12 A11 B11 C11 D11 A10 B10 GND(4)

Bndry Scan 23 26 29 32 35 38 41 44 47 50 53 56 59 62 65 68 71 -

Notes: 1. 5V Spartan family only 2. 3V Spartan-XL family only 3. The PWRDWN on the XCS30XL is not part of the Boundary Scan chain. For the XCS30XL, subtract 1 from all Boundary Scan numbers from GCK3 on (295 and higher). 4. Pads labeled GND(4) or VCC(4) are internally bonded to Ground or VCC planes within the package. 5. CS280 package, and VQ100 and BG256 packages for XCS30 only, discontinued by PDN2004-01

Additional XCS30/XL Package Pins

PQ240 GND Pins

GND Pins

A1 G20 P143 P158 A7 J4 Y13

6/4/97

B7 H4 U8 A13 M4 -

D4 H17 U13 C8 M19 -

D8 N3 U17 D12 V9 -

D13 N4 W14 H20 W9 -

D17 N17 J3 W13 -

P22 P204 P195

2/12/98

P37 P219 -

P83 -

P98 -

U4

Not Connected Pins

Not Connected Pins

BG256 VCC Pins CS280

C14 E20 K4 R4 U15

D6 F1 L17 R17 V7

D7 F4 P4 U6 W20

D11 F17 P17 U7 -

D14 G4 P19 U10 -

D15 G17 R2 U14 A1 G1 T7 A7 G19 U3 C10 K2 U10

VCC Pins C17 K17 U17 GND Pins D13 M4 W13 G1 N16 -

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CS280

XCS40 and XCS40XL Device Pinouts

VCC Pins
XCS40/XL Pad Name PQ208 P200 P201 P202 P203 P204 P205 P206 P207 PQ240 P232 P233 P234 P235 P236 P237 P238 P239 BG256 CS280(2,5) B4 A3 D5 C4 B3 B2 A2 C3 A5 C5 D5 A4 B4 C4 A3 A2 B3 B2 Bndry Scan 140 143 146 149 152 155 158 161 164 167

E5 E13 J15 N15 R13

E7 G5 L5 R7 -

E8 G15 L15 R8 -

E9 H5 M5 R9 -

E11 H15 M15 R11 -

E12 J5 N5 R12 -

I/O I/O I/O I/O I/O I/O I/O I/O

Not Connected Pins A4 D2 H2 M16 R17 W12 A12 D5 H3 M18 T8 W16 C8 D8 H18 R2 T15 C12 D17 H19 R4 U5 C15 D18 L4 R5 V8 D1 E15 M1 R15 V12 -

I/O I/O, SGCK1(1), GCK8(2) VCC GND I/O, PGCK1(1), GCK1(2) I/O I/O I/O I/O, TDI I/O, TCK I/O

P208 P1 P2

P240 P1 P2

VCC(4) GND(4) B1

VCC(4) GND(4) C3

170

Not Connected Pins (VCC in XCS40XL) B5 V5

5/21/02

B15 V15

E3 -

E18 -

R3 -

R18 -

P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24

P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28

C2 D2 D3 E4 C1 D1 E3 E2 E1 F3 F2 GND(4) G3 G2 G1 H3 VCC(4) H2 H1 J4 J3 J2 J1 K2 K3 K1 L1

C2 B1 C1 D4 D3 D2 D1 E2 E4 E1 F5 F3 F2 GND(4) F4 F1 G3 G2 VCC(4) G4 H1 H3 H2 H4 J1 J2 J3 J4 K1

173 176 179 182 185 188 191 194 197 200 203 206 209 212 215 218 221 224 227 230 233 236 239 242 245 248 251

XCS40 and XCS40XL Device Pinouts

XCS40/XL Pad Name VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O PQ208 P183 P184 P185 P186 P187 P188 P189 P190 P191 P192 P193 P194 P195 P196 P197 P198 P199 PQ240 P212 P213 P214 P215 P216 P217 P218 P220 P221 P222 P223 P224 P225 P226 P227 P228 P229 P230 P231 BG256 CS280(2,5) VCC(4) C10 D10 A9 B9 C9 D9 A8 B8 C8 A7 VCC(4) A6 C7 B6 A5 GND(4) C6 B5 A4 C5 VCC(4) D10 E10 A9 B9 C9 D9 A8 B8 C8 D8 VCC(4) B7 C7 D7 A6 GND(4) B6 C6 D6 E6 Bndry Scan 86 89 92 95 98 101 104 107 110 113 116 119 122 125 128 131 134 137

I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O, TMS I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

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Spartan and Spartan-XL FPGA Families Data Sheet

XCS40 and XCS40XL Device Pinouts

XCS40/XL Pad Name GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK2(1), GCK2 (2) Not Connected(1) M1(2) GND MODE(1), M0(2) VCC Not Connected(1) PWRDWN(2) I/O, PGCK2(1), GCK3(2) PQ208 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 PQ240 P29 P30 P31 P32 P33 P34 P35 P36 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 BG256 CS280(2,5) GND(4) VCC(4) L2 L3 L4 M1 M2 M3 M4 N1 N2 VCC(4) P1 P2 R1 P3 GND(4) T1 R3 T2 U1 T3 U2 V1 T4 U3 V2 W1 V3 GND(4) VCC(4) K3 K4 K5 L1 L2 L3 L4 M1 M2 M3 VCC(4) N1 N2 N3 N4 GND(4) P1 P2 P3 P4 P5 R1 R2 R4 T1 T2 T3 U1 V1 U2 Bndry Scan 254 257 260 263 266 269 272 275 278 281 284 287 290 293 296 299 302 305 308 311 314 317 320 323 326 329 332 335

XCS40 and XCS40XL Device Pinouts

XCS40/XL Pad Name I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O PQ208 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 PQ240 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P99 P100 P101 P102 P103 P104 BG256 CS280(2,5) W4 V4 U5 Y3 Y4 V5 W5 Y5 V6 W6 Y6 GND(4) W7 Y7 V8 W8 VCC(4) Y8 U9 V9 W9 Y9 W10 V10 Y10 Y11 W11 VCC(4) GND(4) V11 U11 Y12 W12 V12 U12 Y13 W13 V13 Y14 VCC(4) Y15 V14 W15 W3 T4 U4 V4 W4 R5 U5 T5 W5 R6 U6 V6 T6 GND(4) W6 U7 V7 W7 VCC(4) W8 U8 V8 T8 W9 V9 U9 T9 W10 V10 VCC(4) GND(4) T10 R10 W11 V11 U11 T11 W12 V12 U12 T12 VCC(4) V13 U13 T13 Bndry Scan 346 (3) 349 (3) 352 (3) 355 (3) 358 (3) 361 (3) 364 (3) 367 (3) 370 (3) 373 (3) 376 (3) 379 (3) 382 (3) 385 (3) 388 (3) 391 (3) 394 (3) 397 (3) 400 (3) 403 (3) 406 (3) 409 (3) 412 (3) 415 (3) 418 (3) 421 (3) 424 (3) VCC(4) 427 (3) 430 (3) 433 (3) 436 (3) 439 (3) 442 (3) 445 (3) 448 (3) 451 (3) 454 (3) 457 (3) 460 (3) 463 (3)

P50

P58

W2

V2

338

P51 P52 P53 P54

P59 P60 P61 P62

GND(4) Y1 VCC(4) W3

GND(4) W1 VCC(4) V3

341 342(1)

P55

P63

Y2

W2

343 (3)

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Spartan and Spartan-XL FPGA Families Data Sheet

XCS40 and XCS40XL Device Pinouts

XCS40/XL Pad Name I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK3(1), GCK4(2) GND DONE VCC PROGRAM I/O (D7(2)) I/O, PGCK3(1), GCK5(2) I/O I/O I/O I/O I/O I/O I/O (D6(2)) I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O (D5(2)) PQ208 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 PQ240 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 BG256 CS280(2,5) Y16 GND(4) V15 W16 Y17 V16 W17 Y18 U16 V17 W18 Y19 V18 W19 W14 GND(4) V14 U14 T14 R14 W15 U15 T15 W16 V16 U16 W17 W18 V17 V18 Bndry Scan 466 (3) 469 (3) 472 478 484 490
(3)

XCS40 and XCS40XL Device Pinouts

XCS40/XL Pad Name I/O I/O I/O I/O I/O I/O I/O (D4(2)) I/O VCC GND I/O (D3(2)) I/O I/O I/O I/O I/O I/O I/O I/O (D2(2)) I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O (D1(2)) I/O I/O I/O I/O I/O I/O (D0(2), DIN) I/O, SGCK4(1), GCK6(2) (DOUT) CCLK VCC PQ208 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 PQ240 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 BG256 CS280(2,5) M19 M20 L19 L18 L20 K20 K19 VCC(4) GND(4) K18 K17 J20 J19 J18 J17 H20 H19 H18 VCC(4) G19 F20 G18 F19 GND(4) F18 E19 D20 E18 D19 C20 E17 D18 C19 B20 C18 B19 M18 M16 L19 L18 L17 L16 K19 K18 VCC(4) GND(4) K16 K15 J19 J18 J17 J16 H19 H18 H17 H16 VCC(4) G18 G17 G16 F19 GND(4) F18 F17 F16 F15 E19 E17 E16 D19 D18 D17 C19 B19 C18 B18 Bndry Scan 571 (3) 574 (3) 577 (3) 580 (3) 583 (3) 586 (3) 589 (3) 592 (3) 595 (3) 598 (3) 601 (3) 604 (3) 607 (3) 610 (3) 613 (3) 616 (3) 619 (3) 622 (3) 625 (3) 628 (3) 631 (3) 634 (3) 637 (3) 640 (3) 643 (3) 646 (3) 649 (3) 652 (3) 655 (3) 658 (3) 661 (3) 664 (3) 667 (3) 670 (3) 673 (3) 676 (3)

475 (3)
(3)

481 (3)
(3)

487 (3)
(3)

493 (3) 496 (3) 499 (3) 502 508

(3)

505 (3)
(3)

P103 P104 P105 P106 P107 P108

P119 P120 P121 P122 P123 P124

GND(4) Y20 VCC(4) V19 U19 U18

GND(4) W19 VCC(4) U18 V19 U19

511 (3) 514 (3)

P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123

P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142

T17 V20 U20 T18 T19 T20 R18 R19 R20 P18 GND(4) P20 N18 N19 N20 VCC(4) M17 M18

T16 T17 T18 T19 R15 R17 R16 R19 P15 P17 P18 P16 GND(4) P19 N17 N18 N19 VCC(4) M19 M17

517 (3) 520

(3)

523 (3) 526 (3) 529 (3) 523 (3) 535 (3) 538 (3) 541 (3) 544 (3) 547 (3) 550 (3) 553 (3) 556 (3) 559 (3) 562 (3) 565 (3) 568 (3)

P155 P156

P179 P180

A20 VCC(4)

A19 VCC(4)

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Spartan and Spartan-XL FPGA Families Data Sheet

XCS40 and XCS40XL Device Pinouts

XCS40/XL Pad Name O, TDO GND I/O I/O, PGCK4(1), GCK7(2) I/O I/O I/O (CS1(2)) I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND
2/8/00

Additional XCS40/XL Package Pins

Bndry Scan 0 2 5

PQ208 P157 P158 P159 P160

PQ240 P181 P182 P183 P184

BG256 CS280(2,5) A19 GND(4) B18 B17 B17 GND(4) A18 A17

PQ240

GND Pins P22 P204 P37 P219 P83 P98 P143 P158 -

Not Connected Pins

P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 P181 P182 P185 P186 P187 P188 P189 P190 P191 P192 P193 P194 P196 P197 P198 P199 P200 P201 P202 P203 P205 P206 P207 P208 P209 P210 P211 C17 D16 A18 A17 C16 B16 A16 C15 B15 A15 GND(4) B14 A14 C13 B13 VCC(4) A13 D12 C12 B12 A12 B11 C11 A11 A10 B10 GND(4) D16 C16 B16 A16 E15 C15 D15 A15 E14 C14 B14 D14 GND(4) A14 C13 B13 A13 VCC(4) A12 C12 B12 D12 A11 B11 C11 D11 A10 B10 GND(4) 8 11 14 17 20 23 26 29 32 35 38 41 44 47 50 53 56 59 62 65 68 71 74 77 80 83 -

P195
2/12/98

BG256

VCC Pins C14 E20 K4 R4 U15 D6 F1 L17 R17 V7 D7 F4 P4 U6 W20 D11 F17 P17 U7 D14 G4 P19 U10 D15 G17 R2 U14 -

GND Pins A1 G20 U4

6/17/97

B7 H4 U8

D4 H17 U13

D8 N3 U17

D13 N4 W14

D17 N17 -

CS280

VCC Pins A1 D13 K17 U3 E5 E13 J15 N15 R13

5/19/99

A7 E3 M4 U10 E7 G5 L5 R7 -

B5 E18 N16 U17 E8 G15 L15 R8 -

B15 G1 R3 V5 E9 H5 M5 R9 -

C10 G19 R18 V15 E11 H15 M15 R11 -

C17 K2 T7 W13 E12 J5 N5 R12 -

GND Pins

Notes: 1. 5V Spartan family only 2. 3V Spartan-XL family only 3. The PWRDWN on the XCS40XL is not part of the Boundary Scan chain. For the XCS40XL, subtract 1 from all Boundary Scan numbers from GCK3 on (343 and higher). 4. Pads labeled GND(4) or VCC(4) are internally bonded to Ground or VCC planes within the package. 5. CS280 package discontinued by PDN2004-01

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Product Availability
Table 19 shows the packages and speed grades for Spartan/XL devices. Table 20 shows the number of user I/Os available for each device/package combination. Table 19: Component Availability Chart for Spartan/XL FPGAs Pins Type Device XCS05 XCS10 XCS20 XCS30 XCS40 XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL
6/25/08

84 Plastic PLCC PC84(3) C(3) C(3) C(3) C(3) C(3) C(3) C(3) C(3) -

100 Plastic VQFP VQ100(3) C, I C C, I C C C C(3) C(3) C, I C C, I C C, I C C, I C -

144 Chip Scale CS144(3) C(3) C(3) C(3) C(3) -

144 Plastic TQFP TQ144 C C C, I C C, I C C C C, I C C, I C -

208 Plastic PQFP PQ208 C, I C C, I C C, I C C, I C C, I C C, I C

240 Plastic PQFP PQ240 C C C C C C C C

256 Plastic BGA BG256(3) C(3) C(3) C C C C C, I C

280 Chip Scale CS280(3) C(3) C(3) C(3) C(3)

Code -3 -4 -3 -4 -3 -4 -3 -4 -3 -4 -4 -5 -4 -5 -4 -5 -4 -5 -4 -5

Notes: 1. C = Commercial TJ = 0 to +85C 2. I = Industrial TJ = 40C to +100C 3. PC84, CS144, and CS280 packages, and VQ100 and BG256 packages for XCS30 only, discontinued by PDN2004-01 4. Some Spartan-XL devices are available in Pb-free package options. The Pb-free packages insert a "G" in the package code. Contact Xilinx for availability.

Package Specifications
Package drawings and material declaration data sheets for the Spartan/XL devices can be found on the Xilinx website at:
www.xilinx.com/support/documentation/spartan-xl.htm#19687

Thermal data for the Spartan/XL packages can be found using the thermal query tool on the Xilinx website at:
www.xilinx.com/cgi-bin/thermal/thermal.pl

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Spartan and Spartan-XL FPGA Families Data Sheet

Table 20: User I/O Chart for Spartan/XL FPGAs Device XCS05 XCS10 XCS20 XCS30 XCS40 XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL
6/25/08

Max I/O 80 112 160 192 224 80 112 160 192 224

Package Type PC84(1) 61(1) 61(1) 61(1) 61(1) VQ100(1) 77 77 77 77(1) 77(2) 77(2) 77(2) 77(2) CS144(1) 112(1) 113(1) TQ144 112 113 113 112(2) 113(2) 113(2) PQ208 160 169 169 160(2) 169(2) 169(2) PQ240 192 192 192(2) 192(2) BG256(1) 192(1) 205 192(2) 205(2) CS280(1) 192(1) 224(1)

Notes: 1. PC84, CS144, and CS280 packages, and VQ100 and BG256 packages for XCS30 only, discontinued by PDN2004-01 2. These Spartan-XL devices are available in Pb-free package options. The Pb-free packages insert a "G" in the package code. Contact Xilinx for availability.

Ordering Information
Example:
Device Type Speed Grade -3 -4 -5 BG = Ball Grid Array BGG = Ball Grid Array (Pb-free) PC = Plastic Lead Chip Carrier PQ = Plastic Quad Flat Pack PQG = Plastic Quad Flat Pack (Pb-free)

XCS20XL-4 PQ208C
Temperature Range C = Commercial (TJ = 0 to +85C) I = Industrial (TJ = 40C to +100C) Number of Pins Package Type VQ = Very Thin Quad Flat Pack VQG = Very Thin Quad Flat Pack (Pb-free) TQ = Thin Quad Flat Pack TQG = Thin Quad Flat Pack (Pb-free) CS = Chip Scale

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Revision History
The following table shows the revision history for this document. Date 11/20/98 01/06/99 03/02/00 09/19/01 Version 1.3 1.4 1.5 1.6 Description Added Spartan-XL specs and Power Down. All Spartan-XL -4 specs designated Preliminary with no changes. Added CS package, updated Spartan-XL specs to Final. Reformatted, updated power specs, clarified configuration information. Removed TSOL soldering information from Absolute Maximum Ratings table. Changed Figure 26: Slave Serial Mode Characteristics: TCCH, TCCL from 45 to 40 ns. Changed Master Mode Configuration Switching Characteristics: TCCLK min. from 80 to 100 ns. Added Total Dist. RAM Bits to Table 1; added Start-Up, page 36 characteristics. Clarified Express Mode pseudo daisy chain. Added new Industrial options. Clarified XCS30XL CS280 VCC pinout. Noted that PC84, CS144, and CS280 packages, and VQ100 and BG256 packages for XCS30 only, are discontinued by PDN2004-01. Extended description of recommended maximum delay of reconfiguration in Delaying Configuration After Power-Up, page 35. Added reference to Pb-free package options and provided link to Package Specifications, page 81. Updated links.

06/27/02 06/26/08

1.7 1.8

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