CHAPTER ONE

NUMBER SYSTEM, CODES AND CODES CONVERSION

Number Systems

Decimal System the Decimal system is what you use every day when you count/ Its name is derived from
the Latin word Decem, which means ten. This makes sense since the system uses ten digits: 0, 1, 2, 3, 4, 5,
6, 7, 8 and 9. These digits are what we call the symbols of the decimal system. Since we have ten symbols,
we can count from 0 to 9. Note that 0, even though it often means 'nothing', is a symbol that counts! After
all, you need a numeric way to say 'nothing'. When you want to count past what your simple symbols will
allow, you combine multiple digits. The table below shows this concept, which is demonstrated by adding
one for every step:

The table has 10 numbers across, which is the same number of symbols as the decimal system. As you look
at row 2, you notice that we added symbol 1 to the 0, making 10. In row 3, the one is replaced by a 2, giving
20. The further you go down the table, the higher the numbers get.

Binary Number System

Binary is a number system used by digital devices like computers, cd players, etc. Binary is Base 2 unlike
our counting system decimal which is Base 10 (denary). In other words, Binary has only 2 different
numerals (0 and 1), unlike Decimal which has 10 numerals (0,1,2,3,4,5,6,7,8 and 9). Here is an example of
a binary number: 10011100

As you can see it is simply a bunch of zeroes and ones, there are 8 numerals in all which make this an 8 bit
binary number, bit is short for Binary Digit, and each numeral is classed as a bit. The bit on the far right (in
this case a zero) is known as the Least significant bit (LSB), and the bit on the far left (in this case a 1) is
known as the Most significant bit (MSB) When writing binary numbers you will need to signify that the
number is binary (base 2), for example take the value 101, as it is written it would be hard to work out
whether it is a binary or decimal (denary) value, to get around this problem it is common to denote the base

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to which the number belongs by writing the base value with the number, for example: 1012 is a binary
number and 10110 is a decimal (denary) value.

Octal Number System

Although this was once a popular number base, especially in the Digital Equipment Corporation PDP/8 and
other old computer systems, it is rarely used today. The Octal system is based on the binary system with a
3-bit boundary. The Octal Number System: Uses base 8 Includes only the digits 0 through 7 (any other digit
would make the number an invalid octal number) the weighted values for each position are as follows:

Hexadecimal Number System

Binary is an effective number system for computers because it is easy to implement with digital electronics.
It is inefficient for humans to use binary, however, because it requires so many digits to represent a number.
The number 76, for example, takes only two digits to write in decimal, yet takes seven digits to write in
binary (1001100). To overcome this limitation, the hexadecimal number system was developed.
Hexadecimal is more compact than binary but is still based on the digital nature of computers. Hexadecimal
works in the same way as binary and decimal, but it uses sixteen digits instead of two or ten. Since the
western alphabet contains only ten digits, hexadecimal uses the letters A-F to represent the digits ten
through fifteen. Here are the digits used in hexadecimal and their equivalents in binary and decimal:

1. Binary to Decimal & Decimal to Binary

Binary to Decimal Conversion

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Decimal to Binary Conversion

To convert a decimal number to binary, first subtract the largest possible power of two, and keep subtracting
the next largest possible power form the remainder, marking 1st in each column where this is possible and
0s where it is not.

Example 1 - (Convert Decimal 44 to Binary)

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Convert the following Binary to Hex

1. 102
2. 10112

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 CHAPTER TWO

CODES SYSTEM

Binary Coded Decimal

Binary-coded decimal (BCD) is an encoding for decimal numbers in which each digit is represented by its
own binary sequence. Its main virtue is that it allows easy conversion to decimal digits for printing or
display and faster decimal calculations. Its drawbacks are the increased complexity of circuits needed to
implement mathematical operations and a relatively inefficient encoding—it occupies more space than a
pure binary representation. In BCD, a digit is usually represented by four bits which, in general, represent
the values/digits/characters 0-9. Other bit combinations are sometimes used for sign or other indications.

Excess-three Code

A number code in which the decimal digit n is represented by the four-bit binary equivalent of n + 3. Excess-
3 binary coded decimal (XS-3), also called biased representation or Excess-N, is a numeral system that uses
a pre-specified number N as a biasing value. It is a way to represent values with a balanced number of
positive and negative numbers. In XS-3, numbers are represented as decimal digits, and each digit is
represented by four bits as the BCD value plus 3 (the "excess" amount):

• The smallest binary number represents the smallest value. (i.e. 0 - Excess Value)

• The greatest binary number represents the largest value. (i.e. 2N - Excess Value - 1)

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To encode a number such as 127, then, one simply encodes each of the decimal digits as above, giving
(0100, 0101, 1010). The primary advantage of XS-3 coding over BCD coding is that a decimal number can
be nines' complemented (for subtraction) as easily as a binary number can be ones' complemented; just
invert all bits. Adding Excess-3 works on a different algorithm than BCD coding or regular binary numbers.
When you add two XS-3 numbers together, the result is not an XS-3 number. For instance, when you add
1 and 0 in XS-3 the answer seems to be 4 instead of 1. In order to correct this problem, when you are
finished adding each digit, you have to subtract 3 (binary 11) if the digit is less than decimal 10 and add
three if the number is greater than or equal to decimal 10.

Seven Segment Display Code

Binary numbers are necessary, but very hard to read or interpret. A seven-segment (LED) display is used
to display binary to decimal information. A seven-segment display may have 7, 8, or 9 leads on the chip.
Usually leads 8 and 9 are decimal points. The figure below is a typical component and pin layout for a
seven segment display

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The light emitting diodes in a seven-segment display are arranged in the figure below

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 CHAPTER THREE

BOOLEAN ALGEBRA

Boolean Postulates

Introduction: The most obvious way to simplify Boolean expressions is to manipulate them in the same
way as normal algebraic expressions are manipulated. With regards to logic relations in digital forms, a set
of rules for symbolic manipulation is needed in order to solve for the unknowns. A set of rules formulated
by the English mathematician George Boole describe certain propositions whose outcome would be either
true or false. With regard to digital logic, these rules are used to describe circuits whose state can be either,
1 (true) or 0 (false). In order to fully understand this, the relation between the AND gate, OR gate and NOT
gate operations should be appreciated. A number of rules can be derived from these relations as Table 1
demonstrates.

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Basic Digital Logic

There are three major functions in Digital Electronics. These functions are used to make more complicated
circuits, so an understanding of how these building blocks work is key to understanding how circuits work.
The "AND" function requires that multiple inputs are all true for the output to be true. For example, if you
turn your car's ignition key, and step on the gas, then your car will start. Simply turning the key or stepping
on the gas isn't enough, both must be done to get the correct output. Likewise, all the inputs into an AND
gate must be true for the output to be true. The "OR" function requires any input to be true for the output to
be true. For example, you can enter your home through either the back door or front door. Once you enter
either one, you are inside your home. Likewise, at least one of the inputs into an OR gate must be true for
the output to be true. If more then one input is true, the output is still true, since the minimum requirement
is one. The "INVERTER" function (also known as the "NOT") simply changes the condition. If it was true
it becomes false, and if it was false it becomes true. For example, it is never day and night at the same time.
If it is day, it is not night. Likewise, an INVERTER gate will logically change the input. For the output to
be true, the input must be false. In digital electronics, a false condition is 0 volts (called VSS), while a true
condition is the applied voltage (called VCC or VDD). Since the applied voltage can range from under 3
volts to 5 volts, the true condition is normally simply called a logical 1, and the false condition is called a
logical 0. Using this information, it is possible to create what is called a "truth table." A truth table lists
each possible input combination, and the resulting output for each combination. While the AND and the
OR functions can each have two or more inputs, the truth table given here will assume two inputs.

To read this table, read across. For example, look at the third line down. If input #1 is a logical 1 while
input #2 is a logical 0, the output of an AND gate is a logical 0. On the other hand, the same inputs into an
OR gate will generate a logical 1 output. Remember that for an AND gate all inputs must be true (input #1
AND input #2) to get a true output. However, for an OR gate only one must be true (input #1 OR input #2)
to get a true output.

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K-Map with Don’t care states

K-Map is constructed from a truth table, where all the combinations are given. Assuming sum of minterms
selection, a ‘1’ is inserted in the K-Map whenever a certain combination results in obtaining a ‘1’.

In certain circumstances, a few combinations may not happen or if it does one may not be so concerned
about its occurance and its subsequent result. These combinations are called DON’T CARE states and they
are represented an a K-Map by a ‘X’.

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 CHAPTER FOUR

LOGIC GATES

The individual memory cells used in computers are bistable in operation (pendulous between 1 and 0) and
capable of storing a single binary bit. Therefore, it is most practical to use the binary number system that
uses only two basic symbols 0 and 1 to represent numbers. Binary logic is used to describe, in mathematical
way, the manipulation and processing of binary information. Binary logic consists of binary variables and
logic operations. The binary variables are letters of the alphabet such as X, A, D . . . etc. Each variable has
two possible values, 0 or 1. The basic logic operations are the three operations OR, AND, and NOT.

Gates

A gate is simply an electronic circuit which operates on one or more input signals to perform the logic
operation and produce an output signal. There are many types of gates such as: OR, AND, NOT, NOR,
NAND gates. Each gate has its block diagram symbol. The lines connected to each symbol are the inputs
on the left and the output on the right of it.

Truth Tables

A truth table is a two-dimensional array where there is one column for each input and one column for each
output (a circuit may have more than one output). Since we are dealing with binary values, each input can
be either 0 or 1.The number of truth table possibilities are 2n , where n is the number of input variable. For
example, if n=3 the number of possibilities are 23 =8.

The values in the output column are determined from applying the corresponding input values to the
functional operator. For example, in the following truth table:

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There are 2 input variables, X and Y, and one output variable, F. So there are 22 =4 combinations. The
output F = 1 when either X and Y are both 1 or X=0 and Y =1, while the value of F is 0 for the other
possibilities. Using truth tables is one method to formally describe the operation of a circuit or function.

AND, OR, and NOT gates

AND gate: The AND-gate is a device whose output is logic (1) if both of the inputs are logic (1). It performs
logical multiplication. It composed of two or more inputs and single output. The logical AND function of
two variables is represented either by writing dot between the two variables or by writing the adjacent letters
without dot. For example, X . Y = Z or XY = Z is read "X AND Y is equal to Z". This AND gate symbol

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and its truth table are shown in figure (2-2-a) and (2-2-b) respectively, with two inputs marked A and B and
one output marked X.

OR gate :

It is one of the simplest and most common used. It is a device whose output is logic ‘1’ if either or both of
its inputs are ‘1’. The OR gate composed of two or more inputs and single output. It performs logical
addition. The OR operation is represented by a plus sign, +. For example, X + Y = Z is read " X OR Y is
equal to Z". The standard logic symbol for the OR gate is shown in fig (2-3-a) and the truth table of
combinations for the inputs and outputs for it's is shown in fig (2-3-b).

NOT gate (inverter)

The NOT gate (called inverter) perform a basic logic function called inversion or complementation. It has
a single input and one output. The purpose of the NOT gate is to change one logic level to the opposite
level. In term of bits, it change ‘1’ at its input to logic ‘0’ at the output , and a ‘0’ to a logic ‘1’. The NOT
operation is represented by a prime or bar. The standard logic symbol for the NOT and its truth table are
shown in fig (2-4-a) and fig (2-4-b) respectively.

From the three basic logic gates (AND, OR, and NOT gates), the most powerful computer circuit can be
made. Furthermore, these basic gates are built using transistors, the fundamental building blocks for all
digital logic circuits. Transistors are just electronic binary switches that can be turned on or off. The on and
off states of transistors are used to represent the two binary values 1 and 0.

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Example: Find the truth table for the following? Solution The number of inputs variables is 3, so the
number of combinations are . The sequence of perform the operation as follow

NAND, NOR, X-OR and XNOR gates

NAND gate: The NAND gate is an inverse (negative) of AND functions. Its output is logic (0) if both
inputs are logic (1). It is called NOT-AND gate but is abbreviated NAND gate. Symbolically the NAND

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gate is represented by the AND symbol followed by a small circle indicating an inversion of the output, as
shown in fig (2-7). Fig (2-8) shows the equivalent of NAND gate diagram using AND gate and NOT gate.

NOR gate: The NOR gate (NOT–OR) is equivalent of an inverted OR function and will yield a low output
(0) if either or both inputs are high (1). Symbolically the NOR gate is represented by the OR gate symbol
followed by a bubble to represent the complemented output signal. The NOR gate is a universal building
block of a digital logic because it may be used to implement any logic function. The NOR gate can be
represented by the symbol shown in fig (2-9-a). Its truth table is shown in fig (2-9-b). Fig (2-10) shows the
equivalent of NOR gate diagram using OR gate and NOT gate.

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Exclusive- OR gate: The Exclusive- OR gate is called the XOR gate. It gives logic (1) at the output when
both inputs are different and logic (0) when both inputs are the same. The XOR of two variables is written
by . The XOR gate symbol and its truth table are shown in fig (2-11).

Exclusive NOR gate: Exclusive NOR gate, is called XNOR, is just the inverse of the XOR gate. The
XNOR uses the symbol , and it performs the following logic operation :

The graphic symbols and truth table of XOR is shown in Fig (2-12). The result is 1 when either both X or
Y are 0’s or when both are 1’s.

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we have a full adder, then we can string eight of them together to create a byte-wide adder and cascade the
carry bit from one adder to the next.

By looking at this table you can see that you can implement Q with an XOR gate and CO (carry-out) with
an AND gate. What if you want to add two 8-bit bytes together? This becomes slightly harder. The easiest
solution is to modularize the problem into reusable components and then replicate components. In this case,
we need to create only one component: a full binary adder. The difference between a full adder and the
previous adder we looked at is that a full adder accepts an A and a B input plus a carry-in (CI) input. Once

In the next section, we'll look at how a full adder is implemented into a circuit.

Full Adders

The logic table for a full adder is slightly more complicated than the tables we have used before, because
now we have 3 input bits. It looks like this:

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 CHAPTER FIVE

INTEGRATED CIRCUITS

Terminologies used to characterize Integrated Circuits

Fan in: Is the number of inputs of a digital gate.

Fan out: Is the number of gates’ inputs connected to the output of a gate (the amount of loading).
Sometimes the other types of loads (wires, pads, etc.) are expressed as fan out equivalent.

Example: For the following gate the Fan in is 4 and the Fan out is 5.

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Transistor-Transistor Logic (TTL)

Technology Transistor–transistor logic (TTL) is a class of digital circuits built from bipolar junction
transistors (BJT), and resistors. It is called transistor–transistor logic because both the logic gating function
(e.g., AND) and the amplifying function are performed by transistors (contrast this with RTL and DTL).
TTL is notable for being a widespread integrated circuit (IC) family used in many applications such as
computers, industrial controls, test equipment and instrumentation, consumer electronics, synthesizers, etc.
The designation TTL is sometimes used to mean TTL-compatible logic levels, even when not associated
directly with TTL integrated circuits, for example as a label on the inputs and outputs of electronic
instruments. TTL contrasts with the preceding resistor–transistor logic (RTL) and diode–transistor logic
(DTL) generations by using transistors not only to amplify the output, but also to isolate the inputs. The p-
n junction of a diode has considerable capacitance, so changing the logic level of an input connected to a
diode, as in DTL, requires considerable time and energy. TTL is particularly well suited to integrated
circuits because the inputs of a gate may all be integrated into a single base region to form a multiple-
emitter transistor. Such a highly customized part might increase the cost of a circuit where each transistor
is in a separate package. However, by combining several small on-chip components into one larger device,
it reduces the cost of implementation on an IC. As with all bipolar logic, a small amount of current must be
drawn from a TTL input to ensure proper logic levels. The total current drawn must be within the capacities
of the preceding stage, which limits the number of nodes that can be connected (the fanout). All
standardized common TTL circuits operate with a 5-volt power supply. A TTL input signal is defined as
"low" when between 0 V and 0.8 V with respect to the ground terminal, and "high" when between 2.2 V
and 5 V (precise logic levels vary slightly between sub-types). Standardization of the TTL levels was so
ubiquitous that complex circuit boards often contained TTL chips made by many manufacturers, selected
for availability and cost and not just compatibility. Within usefully broad limits, logic gates could be treated
as ideal Boolean devices without concern for electrical limitations.

Comparison with other logic families

TTL devices consume substantially more power than an equivalent CMOS device at rest, but power
consumption does not increase with clock speed as rapidly as for CMOS devices. Compared to
contemporary ECL circuits, TTL uses less power and has easier design rules, but is substantially slower.
Designers could combine ECL and TTL devices in the same system to achieve best overall performance
and economy, but level-shifting devices were required between the two logic families. TTL was less
sensitive to damage from electrostatic discharge than early CMOS devices. Due to the output structure of
TTL devices, the output impedance is asymmetrical between the high and low state, making them unsuitable
for driving transmission lines. This is usually solved by buffering the outputs with special line driver devices

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where signals need to be sent through cables. ECL, by virtue of its symmetric low-impedance output
structure, does not have this drawback.

Applications of TTL

Before the advent of VLSI devices, TTL integrated circuits were a standard method of construction for the
processors of mini-computer and mainframe processors; such as the DEC VAX and Data General Eclipse,
and for equipment such as machine tool numerical controls, printers, and video display terminals. As
microprocessors became more functional, TTL devices became important for "glue logic" applications,
such as fast bus drivers on a motherboard, which tie together the function blocks realized in VLSI elements.

Diode–transistor logic

Diode–Transistor Logic (DTL) is a class of digital circuits built from bipolar junction transistors (BJT),
diodes and resistors; it is the direct ancestor of transistor–transistor logic. It is called diode–transistor logic
because the logic gating function (e.g., AND) is performed by a diode network and the amplifying function
is performed by a transistor .

Operation

With the simplified circuit shown in the picture the voltage at the base will be near 0.7 volts even when one
input is held at ground level, which results in unstable or invalid operation. Two diodes in series with R3
are commonly used to lower the base voltage and prevent any base current when one or more inputs are at
low logic level. The IBM 1401 used DTL circuits almost identical to this simplified circuit, but solved the
base bias level problem mentioned above by alternating NPN and PNP based gates operating on different
power supply voltages instead of adding extra diodes.

Speed disadvantage

A major advantage over the earlier resistor–transistor logic is the increased fan-in. However, the
propagation delay is still relatively large. When the transistor goes into saturation from all inputs being
high, charge is stored in the base region. When it comes out of saturation (one input goes low) this charge
has to be removed and will dominate the propagation time. One way to speed it up is to connect a resistor
to a negative voltage at the base of the transistor which aids the removal of the minority carriers from the
base. The above problem is solved in TTL by replacing the diodes of the DTL circuit with a multiple-
emitter transistor, which also slightly reduces the required area per gate in an integrated circuit
implementation.

Emitter-coupled logic

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In electronics, emitter-coupled logic, or ECL, is a logic family in which current is steered through bipolar
transistors to implement logic functions. ECL is sometimes called current-mode logic or current-switch
emitter-follower (CSEF) logic. The chief characteristic of ECL is that the transistors are never in the
saturation region and can thus change states at very high speed. Its major disadvantage is that the circuit
continuously draws current, which means it requires a lot of power.

History

ECL was invented in August 1956 at IBM by Hannon S. Yourke. Originally called current steering logic,
it was used in the Stretch, IBM 7090, and IBM 7094 computers. While ECL circuits in the mid-1960s
through the 1990s consisted of a differential amplifier input stage to perform logic, followed by an emitter
follower to drive outputs and shift the output voltages so they will be compatible with the inputs, Yourke's
current switch, also known as ECL, consisted only of differential amplifiers. To provide compatible input
and output levels, two complementary versions were used, an NPN version and a PNP version. The NPN
output could drive PNP inputs, and vice-versa. "The disadvantages are that more different power supply
voltages are needed, and both pnp and npn transistors are required." Motorola introduced their first digital
monolithic integrated circuit line, MECL I, in 1962.

Explanation

TTL and related families use transistors as digital switches where transistors are either cut off or saturated,
depending on the state of the circuit. ECL gates use differential amplifier configurations at the input stage.
A bias configuration supplies a constant voltage at the midrange of the low and high logic levels to the
differential amplifier, so that the appropriate logical function of the input voltages will control the amplifier
and the base of the output transistor (this output transistor is used in common collector configuration). The
propagation time for this arrangement can be less than a nanosecond, making it for many years the fastest
logic family.

Characteristics

Other noteworthy characteristics of the ECL family include the fact that the large current requirement is
approximately constant, and does not depend significantly on the state of the circuit. This means that ECL
circuits generate relatively little power noise, unlike many other logic types which typically draw far more
current when switching than quiescent, for which power noise can become problematic. In an ALU - where
a lot of switching occurs - ECL can draw lower mean current than CMOS.

Usage

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The drawbacks associated with ECL have meant that it has been used mainly when high performance is a
vital requirement. Other families (particularly advanced CMOS variants) have replaced ECL in many
applications, even mainframe computers. However, some experts predict increasing use of ECL in the
future, particularly in conjunction with more widespread adoption of advanced semiconductors such as
gallium arsenide, which has always been seen as the semiconductor of the future, but cannot be produced
as cheaply or cleanly as silicon. Older high-end mainframe computers, such as the Enterprise System/9000
members of IBM's ESA/390 computer family, used ECL; current IBM mainframes use CMOS. The
equivalent of emitter-coupled logic made out of FETs is called source-coupled FET logic (SCFL).

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The J-K Flip-Flop

A very common form of flip-flop is the J-K flip-flop. It is unclear, historically, where the name "J-K" came
from, but it is generally represented in a black box like this:

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 CHAPTER SIX

COUNTER AND DATA TRANSFER

Digital Counters

A digital counter, or simply counter, is a semiconductor device that is used for counting the number of times
that a digital event has occurred. The counter's output is indexed by one LSB every time the counter is
clocked. A simple implementation of a 4-bit counter is shown in Figure 1, which consists of 4 stages of
cascaded J-K flip-flops. This is a binary counter, since the output is in binary system format, i.e., only two
digits are used to represent the count, i.e., '1' and '0'. With only 4 bits, it can only count up to '1111', or
decimal number 15. As one can see from Figure 1, the J and K inputs of all the flip-flops are tied to '1', so
that they will toggle between states every time they are clocked. Also, the output of each flip-flop in the
counter is used to clock the next flip-flop. As a result, the succeeding flip-flop toggles between '1' and '0' at
only half the frequency as the flip-flop before it.

Thus, in Figure 1's 4-bit example, the last flip-flop will only toggle after the first flip-flop has already
toggled 8 times. This type of binary counter is known as a 'serial', 'ripple', or 'asynchronous' counter. The
name 'asynchronous' comes from the fact that this counter's flipflops are not being clocked at the same time.
A 4-bit counter, which has 16 unique states that it can count through, is also called a modulo-16 counter,
or mod-16 counter. By definition, a modulo-k or base-k counter is one that returns to its initial state after k
cycles of the input waveform. A counter that has N flip-flops is a modulo 2N counter. An asynchronous
counter has a serious drawback - its speed is limited by the cumulative propagation times of the cascaded
flip-flops. A counter that has N flip-flops, each of which has a propagation time t, must therefore wait for
a duration equal to N x t before it can undergo another transition clocking. A better counter, therefore, is
one whose flip-flops are clocked at the same time. Such a counter is known as a synchronous counter. A
simple 4-bit synchronous counter is shown in Figure 2. Not all counters with N flip-flops are designed to
go through all its 2N possible states of count. In fact, digital counters can be used to output decimal numbers

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by using logic gates to force them to reset when the output becomes equal to decimal 10. Counters used in
this manner are said to be in binary-coded decimal (BCD).

Synchronous Counters

Basically, any sequential circuit that goes through a prescribed sequence of states upon the application of
input pulses is called a counter. The input pulses, called count pulses, may be clock pulses or they may
originate from an external source and may occur at prescribed intervals of time or at random. The sequence
of states in a counter may follow a binary count or any other sequence.

Why do we need counters?

In a digital circuit, counters are used to do 3 main functions: timing, sequencing and counting. A timing
problem might require that a high-frequency pulse train, such as the output of a 10-MHz crystal oscillator,
be divided to produce a pulse train of a much lower frequency, say 1 Hz. This application is required in a
precision digital clock, where it is not possible to build a crystal oscillator whose natural frequency is 1 Hz.
Measuring the flow of auto traffic on roadway is an application in which an event (the passage of a vehicle)
must increment a tally. This can be done automatically with an electronic counter triggered by a photocell
or road sensor. In this way, the total number of vehicles passing a certain point can be counted.

How are counters made?

Counters are generally made up of flip-flops and logic gates. Like flip-flops, counters can retain an output
state after the input condition which brought about that state has been removed. Consequently, digital
counters are classified as sequential circuits. While a flipflop can occupy one of only two possible states, a
counter can have many more than two states. In the case of a counter, the value of a state is expressed as a
multi-digit binary number, whose `1's and `0's are usually derived from the outputs of internal flip-flops
that make up the counter. The number of states a counter may have is limited only by the amount of

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electronic hardware that is available. The main types of flip-flops used are J-K flip-flops or T flip-flops,
which are J-K flip-flops with both J and K inputs tied together. Before that, here's a quick reminder of how
a J-K flip-flop works:

T flip-flops are used because set/reset ([1,0] [0,1]) functions are seldom used. Only the "do nothing" and
toggle ([0,0] [1,1]) functions are used. Logic gates are used to decide when to toggle which outputs. Below
is an example of a synchronous binary counter, implemented using J-K flip-flops and AND gates.

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SHIFT REGISTERS

A shift register is a register in which the contents may be shifted one or more places to the left or right. This
type of register is capable of performing a variety of functions. It may be used for serial-to-parallel
conversion and for scaling binary numbers. Before we get into the operation of the shift register, let's discuss
serial-to-parallel conversion, parallel-to-serial conversion, and scaling.

Serial and Parallel Transfers and Conversion

Serial and parallel are terms used to describe the method in which data or information is moved from one
place to another. SERIAL TRANSFER means that the data is moved along a single line one bit at a time.
A control pulse is required to move each bit. PARALLEL TRANSFER means that each bit of data is moved
on its own line and that all bits transfer simultaneously as they did in the parallel register. A single control
pulse is required to move all bits. Figure 1 shows how both of these transfers occur. In each case, the four-
bit word 1101 is being transferred to a storage device. In view A, the data moves along a single line. Each
bit of the data will be stored by an individual control pulse. In view B, each bit has a separate input line.
One control pulse will cause the entire word to be stored. Figure 1. - Data transfer methods: A. Serial
transfer; B. Parallel transfer.

Serial-to-parallel conversion or parallel-to-serial conversion describes the manner in which data is stored
in a storage device and the manner in which that data is removed from the storage device. Serial-to-parallel

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conversion means that data is transferred into the storage device or register in serial fashion and removed
in parallel fashion, as in figure 3-30, view A. Parallel-to-serial conversion means the data is transferred into
the storage device in parallel and removed as serial data, as shown in view B. Figure 2. - Data conversion
methods: A. Serial-to-parallel; B. Parallel-to-serial.

Serial transfer takes time. The longer the word length, the longer the transfer will take. Although parallel
transfer is much faster, it requires more circuitry to transfer the data.

Scaling
SCALING means to change the magnitude of a number. Shifting binary numbers to the left increases their
value, and shifting to the right decreases their value. The increase or decrease in value is based on powers
of 2. A shift of one place to the left increases the value by a power of 2, which in effect is multiplying the
number by 2. To demonstrate this, let's assume that the following block diagram is a 5-bit shift register
containing the binary number 01100.
01100
Shifting the entire number one place to the left will put the register in the following condition:
11000
The binary number 01100 has a decimal equivalent of 12. If we convert 110002 to decimal, we find it has
a value of 2410. By shifting the number one place to the left, we have multiplied it by 2. A shift of two
places to the left would be the equivalent of multiplying the number by 22 , or 4; three places by 23 , or 8;
and so forth.
Shifting a binary number to the right decreases the value of the number by a power of 2 for each place. Let's
look at the same 5-bit register containing 011002 and shift the number to the right.
01100
A shift of one place to the right will result in the register being in the following condition:
00110

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By comparing decimal equivalents you can see that we have decreased the value from 1210 to 610. We have
effectively divided the number by 2. A shift of two places to the right is the equivalent of dividing the
number by 22 , or 4; three places by 23 ; or 8; and so forth.
Shift Register Operations
Figure 3-31 shows a typical 4-bit shift register. This particular register is capable of left shifts only. There
are provisions for serial and parallel input and serial and parallel output. Additional circuitry would be
required to make right shifts possible. Figure 3. - Shift register.

Before any operation takes place, a CLEAR pulse is applied to the RESET terminal of each FF to ensure
that the Q output is LOW. The simplest modes of operation for this register are the parallel inputs and
outputs. Parallel data is applied to the SET inputs of the FFs and results in either a 1 or 0 output, depending
on the input. The outputs of the FFs may be sampled for parallel output. In this mode, the register functions
just like the parallel register covered earlier in this section. Parallel-to-Serial Conversion Now let's look at
parallel-to-serial conversion. We will use the 4-bit shift register in figure 3 and the timing sequence in figure
4 to aid you in understanding the operations.

At CP1, a CLEAR pulse is applied to all the FFs, resetting the register to a count of 0. The number 01012
is applied to the parallel inputs at CP2, causing FF1 and FF3 to set. At this point, the J inputs of FF2 and
FF4 are HIGH. AND gate 2 has a LOW output since the FF4 output is LOW. This LOW output represents
the first digit of the number 01012 to be output in serial form. At the same time we have HIGHs on the K

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inputs of FF1 and FF3. (Notice the NOT symbol on FF1 at input K. With no serial input to AND gate 1,
the output is LOW; therefore, the K input to FF1 is held HIGH). With these conditions CP3 causes FF1 and
FF3 to reset and FF2 and FF4 to set. The HIGH output of FF4, along with CP3, causes AND gate 2 to
output a HIGH. This represents the second digit of the number 01012. At CP4, FF2 and FF4 reset, and FF3
sets. FF1 remains reset because of the HIGH at the K input. The output of AND gate 2 goes LOW because
the output of FF4 is LOW and the third digit of the number is output on the serial line. CP5 causes FF4 to
set and FF3 to reset. CP5 and the HIGH from FF4 cause AND gate 2 to output the last digit of the number
on the serial line. It took a total of four CLK pulses to input the number in parallel and output it in serial.
CP6 causes FF4 to reset and effectively clears the register for the next parallel input. Between CP7 and
CP10, the number 11102 is input as parallel data and output as serial data.
Serial-to-Parallel Conversion
Serial input is accomplished much in the same manner as serial output. Instead of shifting the data out one
bit at a time, we shift the data in one bit at a time. To understand this conversion, you should again use

figure 3 and also the timing diagram shown in figure 5. In this example we will convert the number 10112
from serial data to parallel data.

A CLEAR pulse resets all the FFs at CP1. At CP2, the most significant bit of the data is input to AND gate
1. This HIGH along with the clock pulse causes AND gate 1 to output a HIGH. The HIGH from the AND
gate and the clock pulse applied to FF1 cause the FF to set. FFs 2, 3, and 4 are held reset. At this point, the
MSD of the data has been shifted into the register. The next bit of data is a 0. The output of AND gate 1 is
LOW. Because of the inverter on the K input of FF1, the FF senses a HIGH at that input and resets. At the
same time this is occurring, the HIGH on the J input of FF2 (from FF1) and the CLK cause FF2 to set. The
two MSDs, 1 and 0, are now in the register. CP4 causes FF3 to set and FF2 to reset. FF1 is set by the CLK
pulse and the third bit of the number. The register now contains 01012, as a result of shifting the first three
bits of data. The remaining bit is shifted into the register by CP5. FF1 remains set, FF2 sets, FF3 resets, and
FF4 sets. At this point, the serial transfer is complete. The binary word can be sampled on the parallel output
lines. Once the parallel data is transferred, a CLEAR pulse resets the FFs (CP6), and the register is ready
to input the next word.

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