EET 493

Design for Reliability and

Testability of Digital Systems

Instructor: Dr. Mihaela Radu

Impairments to dependability(review)

Fault:
Is a physical defect, imperfection, flaw
in hardware or software.
Examples:- short between wires
-dielectric breakdown
-”bugs” in software- coding faults, infinite
program loop, improper stack sizing, …
-human induced faults

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 Impairments to dependability
Error:
Is the manifestation of the fault.
Represents deviation from correctness or
accuracy.
Errors are usually associated with incorrect
values in the system state.

Examples: affect units of information such as

data words, parity errors, message errors.

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 Impairments to dependability

Failure:
Is the non-performance of some action that is
due or expected.
“A failure occurs when the delivered service
deviates from fulfilling the system function.”
Examples:
A failure is the result of an error, which in turn is
caused by a fault.
There is cause and effect relationship between
these three elements.
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 Fault Modeling
What is a model?
 A model is an abstraction that captures the
behavior of the original system.

 Models are not 100% accurate in all cases, we use

them to make problems tractable and because their
use often introduces little error.

 A fault model is an abstraction describing the

functional effect of a physical defect.
 The model must be simple.
 The model must lead to accurate conclusions.

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 Fault Modeling
Why use a fault model?
 It is very difficult to analyze a system without assuming
some fault models.
 It is hard to design test procedures.
 It is hard to simulate faults.

 Fault Modeling it is a non-destructive method to study

faults. It is a low cost alternative method to fault
injection techniques. Injecting fault at the physical level
is either stressing the hardware with environmental
parameters or by modification of the pin-level values.

 To make the problem manageable, we may need to

reduce the study space (types and models of faults
that can occur). Real defects are too numerous and
often are not analyzable.
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 Fault Modeling

 There are different fault models at different

levels of abstractions.
Hardware (one possible classification)
-Process level (layout)
-Transistor level
-Gate level (logic level)
-Function (or functional) level
-System level (usually called failure models)

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 Fault Modeling
Process level
There are possible defects/fault models. They
are analyzed by manufacturing engineering at
the level of the wafer.
 tested using optical and parametric tests
 effect of defect:
 chip fails to perform its function
 unacceptable parameters - large capacitance, large
delay, slow speed, high current
 used to predict the process yield.

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 Fault Modeling
Some Real Defects in Chips
 Processing defects
 Missing contact windows
 Parasitic transistors
 Oxide breakdown
 ...
 Material defects
 Bulk defects (cracks, crystal imperfections)
 Surface impurities (ion migration)
 ...
 Time-dependent failures
 Dielectric breakdown
 Electromigration
 ...
 Packaging failures
 Contact degradation
 Seal leaks
 . . . etc…
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Semiconductor faults

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 Fault Modeling

Transistor level
Stuck-open and Stuck-on faults

-prevalent fault models for CMOS and TTL logic

The large number of possible faults makes it
difficult to handle these faults (this is true at other
levels also).
 Increasing computing power implies that we can handle
large number of faults and complex models for them.
 These models are used for test generation (and not for
fault tolerance).
 Current testing IDDQ is employed in testing.
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 Fault Modeling
Gate level (Logic level)-
Logic stuck-at- Value Fault Model
Stuck-at-0 (s-a-0) or Stuck-at-1 (s-a-1)

 A line in the circuit stays at the same value, regardless of

the signal applied to the line. Basic assumptions of the
model are:
 The fault is permanent.
 The basic functionality of the circuit is not altered by
the fault. Example: an AND gate will remain an AND
gate, but it will not produce the correct result.
 A fault results in a module responding as if one of its
inputs or outputs is physically stuck at a logic 1 or a
logic 0.

Note: Most applications of the stuck fault model restricts the

number of faults that can occur at any time. Typically we assume
that a circuit will never have more than one stuck-at fault model.
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 Fault Model

Fault detection coverage-is a measure of system’s

ability to detect faults. It is the number of faults
detected, divided by the total number of faults.

A test for a given fault is an assignment of values for

input variables, detecting the fault.
A complete test set is a set of tests detecting all faults
in the circuit.
A minimal complete test set is a complete test set with
a minimal number of tests.

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 Fault Modeling
 The effectiveness of a fault model can often be
quantified by a coverage parameter .

 A fault model is said to cover a fault if and only if the

actual physical defect is accurately represented by the
chosen fault model.

 Ideally, one hopes that a fault model covers 100% of

the physical faults, but this is seldom the case.

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 Simple Hardware Fault Models
another possible classification
Module level Functional level System level
Stuck-at
decoders, PLA memories, ALUs, processors, links
network switches
•Assume lines in gate
level circuit stuck Example: nMOS Example: Memories Example: a parallel
at 0 or 1 decoder •One or more cells are processor topology
•Faults are located at •No output lines stuck at 0 or 1 •View machine as a
inputs and outputs of activated •One or more cells graph
gates •An incorrect line fail to undergo 0→1 • nodes correspond to
•Assume basic activated instead of or 1→0 transition processors
functionality of gates desired line •Two or more cells are •edges correspond to
remains unchanged •An incorrect line coupled links
activated in addition •A 1→0 transition in one Fault Model:
to desired line cell changes contents A processor (node) or
in another cell link (edge) faulty
s-a-0
•More than one cell is
accessed during READ
or WRITE
•A wrong cell is
accessed
during READ or WRITE

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