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Fangming Ye · Zhaobo Zhang
Krishnendu Chakrabarty · Xinli Gu

Knowledge-
Driven
Board-Level
Functional
Fault Diagnosis
Knowledge-Driven Board-Level Functional
Fault Diagnosis
Fangming Ye Zhaobo Zhang
•

Krishnendu Chakrabarty Xinli Gu

•

Knowledge-Driven
Board-Level Functional
Fault Diagnosis

123
Fangming Ye Krishnendu Chakrabarty
Huawei Technologies Department of Electrical and Computer
Santa Clara, CA Engineering
USA Duke University
Durham, NC
Zhaobo Zhang USA
Huawei Technologies
Santa Clara, CA Xinli Gu
USA Huawei Technologies
Santa Clara, CA
USA

ISBN 978-3-319-40209-3 ISBN 978-3-319-40210-9 (eBook)

DOI 10.1007/978-3-319-40210-9

Library of Congress Control Number: 2016942023

© Springer International Publishing Switzerland 2017

This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part
of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations,
recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission
or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar
methodology now known or hereafter developed.
The use of general descriptive names, registered names, trademarks, service marks, etc. in this
publication does not imply, even in the absence of a specific statement, that such names are exempt from
the relevant protective laws and regulations and therefore free for general use.
The publisher, the authors and the editors are safe to assume that the advice and information in this
book are believed to be true and accurate at the date of publication. Neither the publisher nor the
authors or the editors give a warranty, express or implied, with respect to the material contained herein or
for any errors or omissions that may have been made.

Printed on acid-free paper

This Springer imprint is published by Springer Nature

The registered company is Springer International Publishing AG Switzerland
To my beloved family for their boundless
support.
Fangming Ye

To those days and nights at graduate school.

Zhaobo Zhang
Preface

The semiconductor industry continues to relentlessly advance silicon technology

scaling into the deep-submicron (DSM) era. High integration levels and structured
design methods enable complex systems that can be manufactured in high volume.
However, due to increasing integration densities and high operating speeds, subtle
manifestation of defects leads to functional failures at the board level. Functional
fault diagnosis is, therefore, necessary for board-level product qualification.
However, ambiguous diagnosis results can lead to long debug times and wrong
repair actions, which significantly increase repair cost and adversely impact yield.
A state-of-the-art diagnosis system involves several key components: (1) design
of functional test programs, (2) collection of functional-failure syndromes,
(3) building of the diagnosis engine, (4) isolation of root causes, and (5) evaluation
of the diagnosis engine. Advances in each of these components can pave the way
for a more effective diagnosis system, thus improving diagnosis accuracy and
reducing diagnosis time. Machine-learning techniques offer an unprecedented
opportunity to develop an automated and adaptive diagnosis system to increase
diagnosis accuracy and speed.
This book provides a comprehensive set of characterization, prediction, opti-
mization, evaluation, and evolution techniques for a diagnosis system. Readers with
a background in electronics design or system engineering can use this book as a
reference to derive insightful knowledge from data analysis and use this knowledge
as guidance for designing reasoning-based diagnosis systems. Meanwhile, readers
with a background in statistics or data analytics can use this book as a case study for
adapting data mining and machine-learning techniques to electronic system design
and diagnosis.
This book identifies the key challenges in reasoning-based board-level diagnosis
system design, and presents machine-learning-based solutions and corresponding
results that have emerged from cutting edge research in this domain. It broadly
explores a series of topics ranging from high-accuracy fault isolation, adaptive fault
isolation, diagnosis system robustness design, system performance analysis and
evaluation, knowledge discovery, and knowledge transfer.

vii
viii Preface

This book first describes a diagnosis system based on support-vector machine

(SVM), multi-kernel SVM (MK-SVM), and incremental learning. The MK-SVM
method leverages a linear combination of single kernels to achieve accurate
root-cause isolation. The MK-SVMs thus generated also can be updated based on
incremental learning. Furthermore, a data-fusion technique, namely majority-
weighted voting, is used to leverage multiple learning techniques for diagnosis.
The diagnosis time is considerable for complex boards due to the large number
of syndromes that must be used to ensure diagnostic accuracy. Syndrome collection
and analysis are major bottlenecks in state-of-the-art diagnosis procedures.
Therefore, this book describes an adaptive diagnosis method based on decision
trees (DT). The number of syndromes required for diagnosis can be significantly
reduced compared to the number of syndromes used for system training.
Furthermore, an incremental version of DTs is used to facilitate online learning, so
as to bridge the knowledge obtained at test-design stage with the knowledge gained
during volume production.
This book also includes an evaluation and enhancement framework based on
information theory for guiding diagnosis systems using syndrome and root-cause
analysis. Syndrome analysis based on subset selection provides a representative set
of syndromes. Root-cause analysis measures the discriminative ability of differ-
entiating a given root cause from others. The metrics obtained from the proposed
framework can provide guidelines for test redesign to enhance diagnosis. In addi-
tion, traditional diagnosis systems fail to provide appropriate repair suggestions
when the diagnostic logs are fragmented and some syndromes are not available.
The feature of handling missing syndromes based on imputation methods has
therefore been added to the diagnosis system.
Finally, to tackle the bottleneck of data acquisition during the initial product
ramp-up phase, a knowledge-discovery method and a knowledge-transfer method
are proposed for enriching the training data set, thus facilitating board-level func-
tional fault diagnosis.
In summary, this book targets the realization of an automated diagnosis system
that offers the benefits of high accuracy, low diagnosis time, self-evaluation,
self-learning, and ability of selective learning from other diagnosis systems.
Although the goal of this work was to advance board-level diagnosis, the core
techniques developed in this book can also be leveraged for electronic systems
beyond the board level.

Santa Clara Fangming Ye

Santa Clara Zhaobo Zhang
Durham Krishnendu Chakrabarty
Santa Clara Xinli Gu
Acknowledgments

The authors acknowledge the support received from Huawei Technologies. The
authors also appreciate the contribution of Shi Jin to the work on handling missing
syndromes, described in Chap. 6.

ix
Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Introduction to Manufacturing Test . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 System and Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.2 Testing in the Manufacturing Line . . . . . . . . . . . . . . . . 3
1.2 Introduction to Board-Level Diagnosis . . . . . . . . . . . . . . . . . . 6
1.2.1 Review of State-of-the-Art . . . . . . . . . . . . . . . . . . . . . . 7
1.2.2 Automation in Diagnosis System . . . . . . . . . . . . . . . . . 10
1.2.3 New Directions Enabled by Machine Learning . . . . . . . . 13
1.2.4 Challenges and Opportunities . . . . . . . . . . . . . . . . . . . . 15
1.3 Outline of Book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2 Diagnosis Using Support Vector Machines (SVM) . . . . . . . . . . . . 23
2.1 Background and Chapter Highlights . . . . . . . . . . . . . . . . . . . . 24
2.2 Diagnosis Using Support Vector Machines . . . . . . . . . . . . . . . 25
2.2.1 Support Vector Machines . . . . . . . . . . . . . . . . . . . . . . 25
2.2.2 SVM Diagnosis Flow . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.3 Multi-kernel Support Vector Machines and Incremental
Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3.1 Multi-kernel Support Vector Machines . . . . . . . . . . . . . 29
2.3.2 Incremental Learning . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.4 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.4.1 Evaluation of MK-SVM-Based Diagnosis System . . . . . 36
2.4.2 Evaluation of Incremental SVM-Based Diagnosis
System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... 37
2.4.3 Evaluation of Incremental MK-SVM-Based
Diagnosis System . . . . . . . . . . . . . . . . . . . . . . ...... 39
2.5 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... 41
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... 42

xi
xii Contents

3 Diagnosis Using Multiple Classifiers and Majority-Weighted

Voting (WMV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.1 Background and Chapter Highlights . . . . . . . . . . . . . . . . . . . . 44
3.2 Artificial Neural Networks (ANN) . . . . . . . . . . . . . . . . . . . . . 45
3.2.1 Architecture of ANNs . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.2.2 Demonstration of ANN-Based Diagnosis System . . . . . . 48
3.3 Comparison Between ANNs and SVMs . . . . . . . . . . . . . . . . . 49
3.4 Diagnosis Using Weighted-Majority Voting . . . . . . . . . . . . . . . 49
3.4.1 Weighted-Majority Voting . . . . . . . . . . . . . . . . . . . . . . 49
3.4.2 Demonstration of WMV-Based Diagnosis System . . . . . 51
3.5 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.5.1 Evaluation of ANNs-Based Diagnosis System . . . . . . . . 52
3.5.2 Evaluation of SVMs-Based Diagnosis System . . . . . . . . 55
3.5.3 Evaluation of WMV-Based Diagnosis System . . . . . . . . 56
3.6 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4 Adaptive Diagnosis Using Decision Trees (DT) . . . . . . . . . . . . . . . 61
4.1 Background and Chapter Highlights . . . . . . . . . . . . . . . . . . . . 62
4.2 Decision Trees . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.2.1 Training of Decision Trees . . . . . . . . . . . . . . . . . . . . . 63
4.2.2 Example of DT-Based Training and Diagnosis . . . . . . . . 65
4.3 Diagnosis Using Incremental Decision Trees . . . . . . . . . . . . . . 67
4.3.1 Incremental Tree Node . . . . . . . . . . . . . . . . . . . . . . . . 67
4.3.2 Addition of a Case . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.3.3 Ensuring the Best Splitting . . . . . . . . . . . . . . . . . . . . . 70
4.3.4 Tree Transposition . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.4 Diagnosis Flow Based on Incremental Decision Trees . . . . . . . . 72
4.5 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.5.1 Evaluation of DT-Based Diagnosis System . . . . . . . . . . 75
4.5.2 Evaluation of Incremental DT-Based
Diagnosis System . . . . . . . . . . . . . . . . . . . . ........ 77
4.6 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . ........ 78
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 78
5 Information-Theoretic Syndrome and Root-Cause Evaluation . . . . 79
5.1 Background and Chapter Highlights . . . . . . . . . . . . . . . . . . . . 80
5.2 Evaluation Methods for Diagnosis Systems . . . . . . . . . . . . . . . 82
5.2.1 Subset Selection for Syndromes Analysis . . . . . . . . . . . 82
5.2.2 Class-Relevance Statistics . . . . . . . . . . . . . . . . . . . . . . 84
5.3 Evaluation and Enhancement Framework . . . . . . . . . . . . . . . . . 85
5.3.1 Evaluation and Enhancement Procedure . . . . . . . . . . . . 85
5.3.2 An Example of the Proposed Framework . . . . . . . . . . . 86
Contents xiii

5.4 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
5.4.1 Demonstration of Syndrome Analysis . . . . . . . . . . . . . . 89
5.4.2 Demonstration of Root-Cause Analysis . . . . . . . . . . . . . 89
5.5 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6 Handling Missing Syndromes . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.1 Background and Chapter Highlights . . . . . . . . . . . . . . . . . . . . 95
6.2 Methods to Handle Missing Syndromes . . . . . . . . . . . . . . . . . . 97
6.2.1 Missing-Syndrome-Tolerant Fault Diagnosis Flow . . . . . 98
6.2.2 Missing-Syndrome-Preprocessing Methods . . . . . . . . . . 98
6.2.3 Feature Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.3 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.3.1 Evaluation of Label Imputation . . . . . . . . . . . . . . . . . . 107
6.3.2 Evaluation of Feature Selection in Handling Missing
Syndromes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.3.3 Comparison of Different Missing-Syndrome Handling
Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.3.4 Evaluation of Training Time . . . . . . . . . . . . . . . . . . . . 114
6.4 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
7 Knowledge Discovery and Knowledge Transfer . . . . . . . . . . . . . . 121
7.1 Background and Chapter Highlights . . . . . . . . . . . . . . . . . . . . 121
7.2 Overview of Knowledge Discovery and
Transfer Framework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
7.3 Knowledge-Discovery Method . . . . . . . . . . . . . . . . . . . . . . . . 124
7.4 Knowledge-Transfer Method . . . . . . . . . . . . . . . . . . . . . . . . . 128
7.5 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
7.5.1 Evaluation of Knowledge-Discover Method . . . . . . . . . . 138
7.5.2 Evaluation of Knowledge-Transfer Method . . . . . . . . . . 138
7.5.3 Evaluation of Hybrid Method . . . . . . . . . . . . . . . . . . . 139
7.6 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
8 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Chapter 1
Introduction

Relentless technology scaling has increased the performance and complexity of

electronic products by orders of magnitude in the past few decades. A complex
system today consists of several chassis, and each of them contains a number of
printed circuit boards (PCBs). A typical board consists of many application-specific
integrated circuits (ASICs) and memory devices. Each ASIC in turn consists of hun-
dreds of inputs/outputs (I/Os), millions of logic gates, and several tens of millions
of bits of embedded memory. Moreover, the operating frequencies of high-speed
ASICs are above 1 GHz, and the data rates of high-speed I/Os are up to 6 Gbps [1, 2].
With increasing complexity and higher speeds, defective-parts-per-million (DPPM)
rates continue to increase and subtle functional failures are becoming increasingly
difficult to detect and diagnose for root-cause identification [3, 4].
In this chapter, we provide motivation for the book and introduce basic concepts
and terminology. Section 1.1 presents an overview of manufacturing tests and diag-
nosis. Section 1.2 discusses the state-of-the-art in board-level diagnosis. Section 1.2.4
presents the challenges of board-level diagnosis and motivation for this book. Finally,
an outline of this book is provided in Sect. 1.3.

1.1 Introduction to Manufacturing Test

1.1.1 System and Tests

This section presents some basic definitions that are used in system test and diagnosis
[5, 6].

• Definition 1. A system S is defined as a heterogeneous collection of cooperating

entities, designed to realize a specified group of functionalities.

© Springer International Publishing Switzerland 2017 1

F. Ye et al., Knowledge-Driven Board-Level Functional Fault Diagnosis,
DOI 10.1007/978-3-319-40210-9_1
2 1 Introduction

Definition 1 is quite general and it can be adopted to cover a set of different types of
systems in different fields of engineering, from digital systems to computer networks,
nuclear facilities, and chemical plants [5, 6].

• Definition 2. A fault f is defined as a source of misbehavior of a system. The

presence of a fault puts the system in a state where the execution of one or more
of its functionalities is different from the expected execution.

In the reliability literature [7], there is a distinction between defects, which corre-
spond to locations of a system instance containing a difference between specification
and implementation, faults, defined as the actual causes of a system misbehavior, and
failures, representing the external observable effects of a fault, producing a deviation
of functionality from specifications.

• Definition 3. Diagnosis refers to the process of determining the causes of system

failure.

In order to describe the diagnosis process, some additional definitions are needed,
covering both the targets of this process (components) and the information required
to be collected to execute diagnosis (tests). These concepts will be introduced later.

• Definition 4. A component c represents a part of system.

Let CS = {c1 , c2 , c3 . . .cn } be the set of all components that constitute system S.
A component containing (at least) one fault is referred to as a root-cause component;
every other component is fault-free.
Definition 4 requires that each component must be identified unambiguously
within the system. An extension of Definition 2 is that a fault can affect only one
component, and two components of a system cannot overlap.
According to the above definitions, a component can correspond to a physical
device in the system (e.g., a memory chip in a digital system). However, this condition
is not strictly required. A component can also refer to a group of physically connected
elements within the system, or even a set of noninterconnected entities contained in
a system (virtual component).

• Definition 5. A subcomponent sc represents a part within a component c

of system S.

Note that the relationship between components and subcomponents is similar to

the relationship between system and components, since it introduces a partition of
the fault set of each component.

• Definition 6. A (diagnostic) test t represents a measurement of a property of system

S, targeting the identification of the syndromes corresponding to the presence of
a fault.

Let TS = {t1 , t2 , t3 . . . tn } denote the set of all tests used for system S, also
referred to as Test Suite. In general, testing a system can be described as the operation
1.1 Introduction to Manufacturing Test 3

of performing a set of tests [5]. In a diagnostic environment, tests are designed

specifically to identify a potential syndrome of a failure, in order to make the defect
observable within the system.

• Definition 7. A syndrome s characterizes the measurement of a test t.

Syndromes can provide detailed information about the output values of a circuit
[8] or system parameters (e.g., the value of a sensor measurement [9]). In some
cases, the information can be compacted in some form in order to keep only its
most significant part, e.g., the correspondence between the observed value of the
parameter and its expected one. When maximally compacted, a test outcome is a
binary variable that takes the value pass or fail.

• Definition 8. A root cause is the faulty component that leads to the failure of
system S.

The isolation of a root cause is achieved on the basis of the syndromes observed
for some or for all tests TS . These syndromes contain the information that can be
used to reveal the cause of misbehavior in system S.
A common assumption adopted in diagnosis is the so-called single fault hypoth-
esis. This assumption is necessary in order to reduce the complexity of considering
an exponential number of fault combinations to describe all possible system failures.
According to this assumption, any instance of a system can contain at most one
root-cause component.

1.1.2 Testing in the Manufacturing Line

Manufacturing test ensures that electronic products have no defects before they are
shipped to customers. Each fabricated product is subject to manufacturing test. The
process of manufacturing test is described as the explanation or interpretation of a set
of failure symptom [10], where a sequence of diagnostic tests is selected efficiently
to locate the root causes of failures. A diagnosis strategy has to tackle the following
fundamental issues [11]:
• Detection, i.e., the capability of a combination of tests to identify the presence of
a fault in a system.
• Isolation, i.e., the capability of a diagnostic strategy to achieve fine-grained local-
ization in order to allow the repair of a single component.
Compared to detection, isolation is a more difficult task in manufacturing test and
it is the main focus of this book. We use the term Diagnosis to refer to root-cause
isolation.
Diagnosis strategies vary across the different stages of system assembly. In order
to better understand the problems and challenges at the board level, let us first examine
chip-level testing. At the chip level, scan test is commonly used. In order to shift test
4 1 Introduction

patterns and response in and out of the chip, respectively, all the flip-flops are stitched
to one or multiple scan chains. Test patterns are generated by automatic test-pattern
generation (ATPG) tools and scanned into the circuit under test (CUT). The response
of the circuit is compared with the expected response. The circuit is deemed to be
fault-free if the test response matches the expected response. This testing process
can be performed on automatic test equipment (ATE).
A modern ATE is a complex equipment operating at GHz frequency and with
high throughput. The test cost on a high-end ATE can be up to thousands of dollars
per pin [6]. Therefore, test-data compression techniques have been widely explored
in the literature, in order to reduce the volume of test patterns and testing time. To
reduce dependence of an expensive ATE, built-in-self-test (BIST) techniques have
also been used [6]. In BIST, pseudo-random patterns are generated on-chip using a
pattern generation circuit, e.g., a linear-feedback shift register (LFSR). The on-chip
pattern generation approach eliminates the need for expensive external testers, and
makes high-speed test possible. However, the reliance on pseudorandom patterns to
achieve adequate fault coverage leads to a large volume of test data, compared to the
use of deterministic patterns generated by ATPG tools.
Chip-level test has been well studied in the past. The testing goal is straightforward
and quantifiable, i.e., to detect a high percentage of defects that are introduced during
manufacturing. The test environment (ATE) is well-understood and a given number
of pins are available for probing. Sophisticated tools and methodologies are available
for inserting effective design-for-testability (DFT) structures and for automatically
generating test patterns to get the desired fault coverage. This book focuses on the
testing and diagnostic problems at higher integration levels. Much less attention has
been devoted in the literature to these problems.
Circuit boards consist of previously tested components. An important objective
of board testing is to verify the printed wiring and the contacts between wires and
components. Moreover, the at-speed interactions between the components must also
be tested. A typical manufacturing test line of electronic systems is shown in Fig. 1.1.
Testing starts on the left-hand side of the figure. On the right-hand side, completely
tested products are placed in inventory or shipped to customers. The testing process
is separated into multiple stages to provide better failure isolation and feedback to
the manufacturing process.

AOI AXI ICT Functional Test Burn-in Test

Fig. 1.1 A typical manufacturing test line for electronic systems

1.1 Introduction to Manufacturing Test 5

Process test, such as automated optical inspection (AOI) and automated X-ray
inspection (AXI), is first applied to immediately catch process flaws, e.g., solder
shorts and unreliable solder joints. In-circuit test (ICT) is used to verify the perfor-
mance of individual components using a bed-of-nails fixture. The bed-of-nails fix-
ture is used to gain access to the board. ICT is useful to guarantee that a component
receives the correct value, since many board failures are caused by open/short circuits
or wrong components. Functional test, which targets the functional correctness of
components and the whole system, is typically run after process tests. Sometimes,
system test is performed as the final test, which is also a type of functional test. Each
test technique has its advantages. For example, the solder reliability can be easily
checked by AXI. The reversed or inoperative components can be detected by ICT.
No single test can, however, cover all possible defects.
With the development of high-density assembly on PCBs, the number of access
points for in-circuit test keeps decreasing. An interconnection test method, namely
boundary-scan test, has been widely adopted by manufacturers. The boundary-
scan architecture is defined in the IEEE 1149.1 and 1149.6 standards [12, 13] to
ensure connectivity between components. Simple boards and complex multiboard
systems can effectively be tested using the IEEE 1149.6 standard-compliant equip-
ment from the product design phase to mainstream manufacturing. At present, there
is an increased focus in the electronics industry on using the concept of remote
test and diagnosis in order to provide a mechanism that allows continued support
of a product [14]. The boundary-scan test architecture is illustrated in Fig. 1.2. A
boundary-scan cell, which includes a multiplexer and latches, is added to each pin
on the chip. Boundary-scan cells can capture data from pins or core logic signals, and
force data to pins. The test data is serially shifted into the boundary-scan cells. Then,
the captured data is serially shifted out and externally compared with the expected

Shift out

Parallel in Parallel out

Boundary
scan cell

Shift in

Core
Shift DR Shift out Mode
Logic
Parallel in
Capture scan 0 Parallel out
Update hold
0
D Q D Q 1
1

>CLK >CLK

TAP Clock DR Update DR

Boundary‐scan cell

Fig. 1.2 Illustration of the boundary-scan test architecture

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