SyncMOS Technologies Inc.

SM89516
May 2001 8 - Bit Micro-controller
with 64KB flash & 1KB RAM embedded

Product List
SM89516L25, 25 MHz 64KB internal memory MCU Features
SM89516C25, 25 MHz 64KB internal memory MCU
Working voltage: 3.0V ~ 3.6V For L Version
4.5V ~ 5.5V For C Version

Description General 8052 family compatible

12 clocks per machine cycle
64 KB internal flash memory
The SM89516 series product is an 8 - bit single chip
micro controller with 64KB flash & 1KB RAM embed- 1024 bytes data RAM
ded. It is a derivative of the 8052 micro controller family. Three 16 bit timers/counters
With its hardware features and powerful instruction set, Four 8-bit I/O ports for PDIP package
it’s straight forward to make it a versatile and cost effec-
Four 8-bit I/O ports + one 4-bit I/O ports
tive controller for those applications which demand up
to 32 I/O pins for PDIP package or up to 36 I/O pins for for PLCC or QFP package
PLCC/QFP package, or applications which need up to Full duplex serial channel
64KB memory either for program or for data or mixed. Bit operation instruction
To program the on-chip flash memory, a commercial
Page free jumps
writer is available to do it in parallel programming
method. 8-bit unsigned division
8-bit unsigned multiply
BCD arithmetic operations
Ordering Information Direct addressing
Indirect addressing
yywwv Nested interrupts
SM89516ihhk Two priority level interrupts
yy: year, ww:week A serial I/O port
v: version identifier {, A, B,...} Power save modes:
i: process identifier {L=3.0V ~ 3.6V, C=4.5V ~ 5.5V} Idle mode and power down mode
hh: working clock in MHz {25}
Code protection function
k: package type postfix {as below table}
One watch dog timer (WDT)
Low EMI (inhibit ALE)
Pin/Pad
Postfix Package Configuration Dimension
P 40L PDIP page 2 page 16
J 44L PLCC page 2 page 17
Q 44L QFP page 2 page 18

Taiwan
4F, No. 1 Creation Road 1,
Science-based Industrial Park,
Hsinchu, Taiwan 30077

TEL: 886-3-578-3344
FAX: 886-3-579-2960
886-3-578-0493

Specifications subject to change without notice,contact your sales representatives for the most recent information.

1/19 Ver 1.3 PID 89516 05/01

 SyncMOS Technologies Inc. SM89516
May 2001

Pin Configurations P1.1/T2EX

P0.0/AD0

P0.5/AD5
P0.3/AD3

P0.4/AD4

P0.6/AD6
P0.7/AD7
P0.2/AD2
P0.1/AD1

P2.7/A15
P2.6/A14
P2.5/A13
P1.0/T2

#PSEN
VDD
P4.2

P4.1
P1.2

#EA
P1.3
P1.4

ALE
6 5 4 3 2 1 44 43 42 41 40
39 P0.4/AD4 33 32 31 30 29 28 27 26 25 24 23
P1.5 7 AD3/P0.3 34 22 P2.4/A12
38 P0.5/AD5
P1.6 8 AD2/P0.2 35
37 P0.6/AD6 21 P2.3/A11
P1.7 9 36
36 P0.7/AD7 AD1/P0.1 20 P2.2A10
RES 10
RXD/P3.0 11
SM89516 ihhJv 35 #EA AD0/P0.0 37
SM89516 ihhQv
19
18
P2.1A9
P2.0/A8
VDD 38
P4.3 12 34 P4.1 17
P4.2 39 P4.0
TXD/P3.1 13 (Top View, 44L PLCC) 33 ALE 16 VSS
32
T2/P1.0 40 (Top View, 44L QFP)
#INT0/P3.2 14 #PSEN 41 15 XTAL1
31
T2EX/P1.1
#INT1/P3.3 15 P2.7/A15 42 14
P1.2 XTAL2
T0/P3.4 16 30 P2.6/A14 43
P1.3 13 P3.7/#RD
T1/P3.5 17 29
18 19 20 21 22 23 24 25 26 27 28 P2.5/A13 P1.4 44 12 P3.6/#WR
1 2 3 4 5 6 7 8 9 10 11
#RD/P3.7

XTAL1
#WR/P3.6

XTAL2

VSS
P4.0

A12/P2.4
A8/P2.0
A9/P2.1
A10/P2.2
A11/P2.3

RXD/P3.0

#INT0/P3.2
RES

P4.3

T0/P3.4
P1.5

#INT1/P3.3
TXD/P3.1
P1.6

T1/P3.5
P1.7

T2/P1.0 1 VDD
40
T2EX/P1.1 2 39 P0.0/AD0
P1.2 3 38 P0.1/AD1

4
37 P0.2/AD2
P1.3
5 36 P0.3/AD3
P1.4
35 P0.4/AD4
P1.5/ 6
34 P0.5/AD5
(Top View, 40L PDIP)

P1.6 7
P0.6/AD6
SM89516 ihhPv

33
P1.7 8
32 P0.7/AD7
RES 9
31 #EA
RXD/P3.0 10
30 ALE
TXD/P3.1 11
29 #PSEN
#INT0/P3.2 12
28 P2.7/A15
#INT1/P3.3 13
27 P2.6/A14
T0/P3.4 14
15 26 P2.5/A13
T1/P3.5
16 25 P2.4/A12
#WR/P3.6
#RD/P3.7 17 24 P2.3/A11
XTAL2 18 23 P2.2/A10
XTAL1 19 22 P2.1/A9
VSS 20 21 P2.0/A8

Specifications subject to change without notice,contact your sales representatives for the most recent information.

2/19 Ver 1.3 PID 89516 05/01

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May 2001

Block Diagram

Stack Decoder & 1024 bytes

Timer 2 Timer 1 Timer 0 Pointer Register RAM

Buffer
WDT

RES Reset to pertinent blocks

DPTR
Circuit Acc

Vdd to whole chip PC

Power Incrementer
Vss Circuit
Buffer2 Buffer1

to pertinent blocks Program

Interrupt ALU Counter
Circuit

Register
XTAL2 PSW

XTAL1 Timing
#EA to whole system
Generator
ALE
#PSEN Instruction
Register

64K
bytes
Flash
Port 2 Port 3 Port 4 Memory
Port 0 Port 1
Latch Latch Latch Latch Latch

Port 0 Port 1 Port 2 Port 3 Port 4

Driver & Mux Driver & Mux Driver & Mux Driver & Mux Driver & Mux

8 8 8 8 4

Specifications subject to change without notice,contact your sales representatives for the most recent information.

3/19 Ver 1.3 PID 89516 05/01

 SyncMOS Technologies Inc. SM89516
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Pin Descriptions
40L 44L 44L
PDIP QFP PLCC Symbol Active I/O Names
Pin# Pin# Pin#
1 40 2 T2/P1.0 i/o timer 2 clock out & bit 0 of port 1
2 41 3 T2EX/P1.1 i/o timer 2 control & bit 1 of port 1
3 42 4 P1.2 i/o bit 2 of port 1
4 43 5 P1.3 i/o bit 3 of port 1
5 44 6 P1.4 i/o bit 4 of port 1
6 1 7 P1.5 i/o bit 5 of port 1
7 2 8 P1.6 i/o bit 6 of port 1
8 3 9 P1.7 i/o bit 7 of port 1
9 4 10 RES H i Reset
10 5 11 RXD/P3.0 i/o Receive data & bit 0 of port 3
11 7 13 TXD/P3.1 i/o Transmit data & bit 1 of port 3
12 8 14 #INT0/P3.2 L/ - i/o low true interrupt 0 & bit 2 of port 3
13 9 15 #INT1/P3.3 L/ - i/o low true interrupt 1 & bit 3 of port 3
14 10 16 T0/P3.4 i/o Timer 0 & bit 4 of port 3
15 11 17 T1/P3.5 i/o Timer 1 & bit 5 of port 3
16 12 18 #WR/P3.6 L/ - i/o external memory write & bit 6 of port 3
17 13 19 #RD/P3.7 L/ - i/o external memory read & bit 7 of port 3
18 14 20 XTAL2 o Crystal out
19 15 21 XTAL1 i Crystal in
20 16 22 VSS Sink Voltage, Ground
21 18 24 P2.0/A8 i/o bit 0 of port 2 & bit 8 of external memory address
22 19 25 P2.1/A9 i/o bit 1 of port 2 & bit 9 of external memory address
23 20 26 P2.2/A10 i/o bit 2 of port 2 & bit 10 of external memory address
24 21 27 P2.3/A11 i/o bit 3 of port 2 & bit 11 of external memory address
25 22 28 P2.4/A12 i/o bit 4 of port 2 & bit 12 of external memory address
26 23 29 P2.5/A13 i/o bit 5 of port 2 & bit 13 of external memory address
27 24 30 P2.6/A14 i/o bit 6 of port 2 & bit 14 of external memory address
28 25 31 P2.7/A15 i/o bit 7 of port 2 & bit 15 of external memory address
29 26 32 #PSEN L o program storage enable
30 27 33 ALE - o address latch enable
31 29 35 #EA L i external access
32 30 36 P0.7/AD7 i/o bit 7 of port 0 & data/address bit 7 of external memory
33 31 37 P0.6/AD6 i/o bit 6 of port 0 & data/address bit 6 of external memory
34 32 38 P0.5/AD5 i/o bit 5 of port 0 & data/address bit 5 of external memory
35 33 39 P0.4/AD4 i/o bit 4 of port 0 & data/address bit 4 of external memory
36 34 40 P0.3/AD3 i/o bit 3 of port 0 & data/address bit 3 of external memory
37 35 41 P0.2/AD2 i/o bit 2 of port 0 & data/address bit 2 of external memory
38 36 42 P0.1/AD1 i/o bit 1 of port 0 & data/address bit 1 of external memory
39 37 43 P0.0/AD0 i/o bit 0 of port 0 & data/address bit 0 of external memory
40 38 44 VDD Drive Voltage, +5 Vcc
17 23 P4.0 i/o bit 0 of Port 4
28 34 P4.1 i/o bit 1 of Port 4
39 1 P4.2 i/o bit 2 of Port 4
6 12 P4.3 i/o bit 3 of Port 4
Specifications subject to change without notice,contact your sales representatives for the most recent information.

4/19 Ver 1.3 PID 89516 05/01

 SyncMOS Technologies Inc. SM89516
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Special Function Register (SFR) Memory MAP

$F8 $FF
$F0 B $F7
$E8 $EF
ACC $E7
$E0
$D8 P4 $DF
$D0 PSW $D7
$C8 T2CON RC2L RC2H TL2 TH2 $CF
$C0 $C7
$B8 IP SCONF $BF
$B0 P3 $B7
$A8 IE $AF
$A0 P2 $A7
$98 SCON SBUF WDTC $9F
$90 P1 $97
$88 TCON TMOD TL0 TL1 TH0 TH1 $8F
$80 P0 SP DPL DPH (Reserved) RCON PCON $87
Note: The text of SFRs with bold type characters are Extension Special Function Registers for SM89516

Extension Function Description

Memory Structure
The SM89516 is the general 8052 hardware core to integrate the expanded 768B data RAM
and 64KB flash program memory as a single chip micro controller. Its memory structure follows
general 8052 structure.

Program Memory
The SM89516 has 64K bytes on-chip flash memory which can be used as general program memory.

FFFF

64K Program
memory space

0000
Specifications subject to change without notice,contact your sales representatives for the most recent information.

5/19 Ver 1.3 PID 89516 05/01

 SyncMOS Technologies Inc. SM89516
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Data Memory
The SM89516 has 1K bytes on-chip RAM, 256 bytes of it are the same as general 8052 internal memory
structure while the expanded 768 bytes on-chip RAM can be accessed by external memory addressing method.
(by instruction MOVX)
02FF

Expanded 768 bytes (Accessed

by direct external addressing
mode, by instruction MOVX)

FF
(OME = 1)
FF Higher 128 bytes (Access by SFR (Accessed by direct
80 indirect addressing mode only) addressing mode only)
7F
Lower 128 bytes (Accessed by 80
00
direct & indirect addressing mode) 0000

Data Memory - Lower 128 byte

Data memory $00 to $FF is the same as 8052
The address $00 to $7F can be accessed by direct and indirect addressing modes.
Address $00 to $1F is register area.
Address $20 to $2F is memory bit area.
Address $30 to $7F is for general memory area.

Data memory - Higher 128 byte

The address $80 to $FF can be accessed by indirect addressing mode only.
Addressing $80 to $FF is data area.

Data Memory - Expanded 768 bytes

From external address $0000 to $02FF is the on-chip expanded RAM area, total 768 bytes. This area can be
accessed by external direct addressing mode only (by instruction MOVX).

Internal RAM Control Register (RCON, $85)

bit-7 bit-0
Read :
Unused Unused Unused Unused Unused Unused RAMS1 RAMS0
Write :
Reset value : * * * * * * 0 0

Specifications subject to change without notice,contact your sales representatives for the most recent information.

6/19 Ver 1.3 PID 89516 05/01

 SyncMOS Technologies Inc. SM89516
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SM89516 has 768 byte on-chip RAM which can be accessed by external memory addressing method only. (By
instruction MOVX). The address space of instruction MOVX @Rn is determined by bit 1 and bit 0 (RAMS1,
RAMS0) of RCON. The default setting of RAMS1, RAMS0 bits is 00 (page0).

RAMS1 RAMS0 MOVX @Ri i=0,1 mapping to expended RAM address

0 0 $0000 ~ $00FF
0 1 $0100 ~ $01FF
1 0 $0200 ~ $02FF

Port 4 for PLCC or QFP package:

The bit addressable port 4 is available with PLCC or QFP package. The port 4 has only 4 pins and its port
address is located at 0D8H. The function of port 4 is the same as the function of port 1, port 2 and port 3.

port4 (P4, $D8)

Unused Unused Unused Unused P4.3 P4.2 P4.1 P4.0
* * * * 1 1 1 1
Reset
value MSB LSB
The bit 3, bit 2, bit 1, bit 0 output the setting to pin P4.3, P4.2, P4.1, P4.0 respectively.

Extension Function Description

Watch Dog Timer

The Watch Dog Timer (WDT) is a 16-bit free-running counter that generate reset signal if the counter overflows. The WDT
is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software dead
loop or runaway. The WDT function can help user software recover form abnormal software condition. The WDT is different
from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by software periodically clearing
the WDT counter.

The SM89516 WDT has selectable divider input for the time base source clock. To select the divider input, the setting of
bit2~bit0 (PS2~PS0) OF Watch Dog Timer Control Register (WDTC) should be set accordingly.

The WDT is enable by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bit counter starts to count with
the selected time base source clock which set by PS2~PS0. It will generate a reset signal when overflows. The WDTE bit
will be cleared to 0 automatically when SM89516 been reset, either hardware reset or WDT reset.

To reset the WDT is done by setting 1 to the bit 5 (CLEAR) of WDTC. This will clear the content of the 16-bit counter and let
the counter re-start to count from the beginning.

Specifications subject to change without notice,contact your sales representatives for the most recent information.

7/19 Ver 1.3 PID 89516 05/01

 SyncMOS Technologies Inc. SM89516
May 2001

Watch Dog Timer Registers - WDT Control Register (WDTC, $9F)

WDTE Unused CLEAR Unused Unused PS2 PS1 PS0

Reset 0 * 0 * * 0 0 0
value
MSB LSB
WDTE: Watch Dog Timer enable bit
CLEAR: Watch Dog Timer reset bit
PS2 ~ PS0: clock source divider selection bit

PS [2:0] Divider (OSC in) Time Period (ms) @40MHz

000 8 13.1
001 16 26.21
010 32 52.42
011 64 104.8
100 128 209.71
101 256 419.43
110 512 838.86
111 1024 1677.72

System Control Register (SCONF, $BF)

WDR Unused Unused Unused Unused Unused OME ALEI

Reset 0 * * * * * 1 0
value
MSB LSB

WDR: Watch Dog Timer Reset. When system reset by Watch Dog Timer overflow, WDR will be set to 1
OME: 768 bytes on-chip RAM enable bit
ALEI: ALE output inhibit bit, to reduce EMI

The bit 7(WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated
by WDT overflow. User should check WDR bit whenever un-predicted reset happened.

Reduce EMI Function

The SM89516 allows user to reduce the EMI emission by setting 1 to the bit 0 (ALEI) of SCONF register. This
function will inhibit the clock signal in Fosc/6Hz output to the ALE pin. This function is available when there is
no external program memory or no external data RAM in the system.

Specifications subject to change without notice,contact your sales representatives for the most recent information.

8/19 Ver 1.3 PID 89516 05/01

 SyncMOS Technologies Inc. SM89516
May 2001

Operating Conditions

Symbol Description Min. Typ. Max. Unit. Remarks

TA Operating temperature 0 25 70 oC Ambient temperature under bias
TS Storage temperature -55 25 155 oC

VCC5 Supply voltage 4.5 5.0 5.5 V For C Version

VCC3 Supply voltage 3 3.3 3.6 V For L Version
Fosc 16 Oscillator Frequency 3.0 16 16 MHz For 5V, 3.3V application
Fosc 25 Oscillator Frequency 3.0 25 25 MHz For 5V, 3.3V application

DC Characteristics
(12MHz, typical operating conditions, valid for SM89516 series)
Symbol Parameter Valid Min. Max. Unit Test Conditions
VIL1 Input Low Voltage port 0,1,2,3,4,#EA -0.5 0.8 V
VIL2 Input Low Voltage RES, XTAL1 0 0.8 V
VIH1 Input High Voltage port 0,1,2,3,4,#EA 2.0 Vcc+0.5 V
VIH2 Input High Voltage RES, XTAL1 70%Vcc Vcc+0.5 V
VOL1 Output Low Voltage port 0, ALE, #PSEN 0.45 V IOL=3.2mA
VOL2 Output Low Voltage port 1,2,3,4 0.45 V IOL=1.6mA
VOH1 Output High Voltage port 0 2.4 V IOH=-800uA (only for VCC=5V)
90%Vcc V IOH=-80uA
VOH2 Output High Voltage port 1,2,3,4,ALE,#PSEN 2.4 V IOH=-60uA (only for VCC=5V)
90%Vcc V IOH=-10uA
IIL Logical 0 Input Current port 1,2,3,4 -75 uA Vin=0.45V
ITL Logical Transition Current port 1,2,3,4 -650 uA Vin=2.0V
ILI Input Leakage Current port 0, #EA + 10 uA 0.45V<Vin<Vcc
R RES Reset Pulldown Resistance RES 50 300 Kohm
C IO Pin Capacitance 10 pF Freq=1MHz, Ta=25 C
I CC Power Supply Current Vdd 20 mA Active mode, 16MHz
6.5 mA Idle mode, 16MHz
50 uA Power down mode

Specifications subject to change without notice,contact your sales representatives for the most recent information.

9/19 Ver 1.3 PID 89516 05/01

 SyncMOS Technologies Inc. SM89516
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AC Characteristics
(16/25MHz, operating conditions; CL for Port 0, ALE and PSEN Outputs=100pF; CL for all Other Output=80pF)
Valid fosc=16MHz Variable fosc Unit Remarks
Symbol Parameter Cycle Min. Typ. Max Min. Typ. Max
T LHLL ALE pulse width RD/WRT 115 2xT - 10 nS
T AVLL Address Valid to ALE low RD/WRT 43 T - 20 nS
T LLAX Address Hold after ALE low RD/WRT 53 T - 10 nS
T LLIV ALE low to Valid Instruction In RD 240 4xT - 10 nS
T LLPL ALE low to #PSEN low RD 53 T - 10 nS
T PLPH #PSEN pulse width RD 173 3xT - 15 nS
T PLIV #PSEN low to Valid Instruction In RD 177 3xT - 10 nS
T PXIX Instruction Hold after #PSEN RD 0 0 nS
T PXIZ Instruction Float after #PSEN RD 87 T + 25 nS
T AVIV Address to Valid Instruction In RD 292 5xT - 20 nS
T PLAZ #PSEN low to Address Float RD 10 10 nS
T RLRH #RD pulse width RD 365 6xT - 10 nS
T WLWH #WR pulse width WRT 365 6xT - 10 nS
T RLDV #RD low to Valid Data In RD 302 5xT - 10 nS
T RHDX Data Hold after #RD RD 0 0 nS
T RHDZ Data Float after #RD RD 145 2xT + 20 nS
T LLDV ALE low to Valid Data In RD 590 8xT - 10 nS
T AVDV Address to Valid Data In RD 542 9xT - 20 nS
T LLYL ALE low to #WR High or #RD low RD/WRT 178 197 3xT - 10 3xT + 10 nS
T AVYL Address Valid to #WR or #RD low RD/WRT 230 4xT - 20 nS
T QVWH Data Valid to #WR High WRT 403 7xT - 35 nS
T QVWX Data Valid to #WR transition WRT 38 T - 25 nS
T WHQX Data hold after #WR WRT 73 T + 10 nS
T RLAZ #RD low to Address Float RD 5 nS
T YALH #WR or #RD high to ALE high RD/WRT 53 72 T -10 T + 10 nS
T CHCL clock fall time nS
T CLCX clock low time nS
T CLCH clock rise time nS
T CHCX clock high time nS
T, TCLCL clock period 63 1/fosc nS

ICC Active mode test circuit ICC Idle mode test circuit
ICC Vcc ICC Vcc
Vcc
VCC VCC
8 RST 8
RST PO PO
EA EA
SM89516 SM89516

(NC) XTAL2 (NC) XTAL2

Clock Signal XTAL1 Clock Signal XTAL1
VSS VSS

Specifications subject to change without notice,contact your sales representatives for the most recent information.

10/19 Ver 1.3 PID 89516 05/01

 SyncMOS Technologies Inc. SM89516
May 2001

Application Reference

Valid for SM89516

XI
X'tal 3MHz 6MHz 9MHz 12MHz
C1 30 p 30 p 30 p 30 p
X'tal
C2 30 p 30 p 30 p 30 p SM89516
R open open open open
R
X'tal 16MHz 25MHz 33MHz X2
C1 30 pF 15 pF 10 pF
C1 C2
C2 30 pF 15 pF 10 pF
R open 62KΩ 6.8KΩ

NOTE: Oscillation circuit may differs with different crystal or ceramic

resonator in higher oscillation frequency which was due to each
crystal or ceramic resonator has its own characteristics.
User should check with the crystal or ceramic resonator manufacturer
for appropriate value of external components.

Data Memory Read Cycle Timing

T12 T1 T3 T5 T6 T7 T8 T9 T10 T11 T12 T1 T2 T3
T2 T4

OSC
1 2

ALE

#PSEN

#RD 5
7

PORT2 ADDRESS A15 - A8

3 4 6 8

PORT0 INST in Float A7 - A0 Float DATA in Float

ADDRESS
or Float

Specifications subject to change without notice,contact your sales representatives for the most recent information.

11/19 Ver 1.3 PID 89516 05/01

 SyncMOS Technologies Inc. SM89516
May 2001

Program Memory Read Cycle Timing

T12 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T1 T2

OSC

ALE 1 2

5
#PSEN 7

#RD,#WR

3
PORT2 ADDRESS A15 - A8 ADDRESS A15 - A8

3 4 6 8
PORT0
Float A7 - A0 Float INST in Float A7 - A0 Float INST in Float

Data Memory Write Cycle Timing

T4 T5 T6 T7 T8 T9 T10 T11 T12 T1 T2 T3
T12 T1 T2 T3

OSC
1

ALE

#PSEN

#WR 5
6

ADDRESS A15 - A8
PORT2

2 4
3
INST Float A7 - A0 DATA OUT ADDRESS
PORT0 or Float

Specifications subject to change without notice,contact your sales representatives for the most recent information.

12/19 Ver 1.3 PID 89516 05/01

 SyncMOS Technologies Inc. SM89516
May 2001

I/O Ports Timing

T4 T5 T6 T7 T8
T12 T1 T2 T3
T6 T7 T8 T9 T10 T11

X1 sampled

inputs P0,P1
sampled

inputs P2,P3

Output by current data next data

Mov Px,Src
RxD at Serial Port
Shift Clock sampled
(Mode 0)

Timing Critical, Requirement of External Clock (Vss=0.0V is assumed)

TCLCL
Vdd-0.5V 70%Vdd

20%Vdd-0.1V
0.45V
TCHCL TCLCX TCHCX
TCLCH

Tm.I External Program Memory Read Cycle

TPLPH

#PSEN

TLHLL TLLPL TPXIZ

ALE TPLAZ
TAVLL TLLAX TPLIV TPXIX

A0 - A7 Instruction. IN A0 - A7
PORT 0
TAVIV

PORT 2 A8 - A15 A8 - A15

Specifications subject to change without notice,contact your sales representatives for the most recent information.

13/19 Ver 1.3 PID 89516 05/01

 SyncMOS Technologies Inc. SM89516
May 2001

Tm.II External Data Memory Read Cycle

#PSEN

TYHLH

ALE

TLLDV
TLLYL TRLRH

#RD
TAVLL
TLLAX TRLDV TRHDZ
TRLAZ
TRHDX
A0 - A7 A0 - A7 INSTRL
PORT 0 from Ri or DPL DATA IN
from PCL IN

TAVYL
TAVDV

PORT 2 P2.0 - P2.7 or A8 - A15 from DPH A8 - A15 from PCH

Tm.III External Data Memory Write Cycle

#PSEN TYHLH

TLHLL
ALE

TLLYL TWLWH

#WR TAVLL
TQVWX
TLLAX TWHQX
TQVWH

A0-A7 A0-A7 INSTRL

DATA OUT
PORT 0 from Ri or DPL From PCL IN

TAVYL

P2.0-P2.7 or A8-A15 from DPH A8-A15 from PCH

PORT 2

Specifications subject to change without notice,contact your sales representatives for the most recent information.

14/19 Ver 1.3 PID 89516 05/01

 SyncMOS Technologies Inc. SM89516
May 2001

40L 600mil PDIP Information

E
D
S E1

A2
A1 C
A

e1
B1
B eA

Note:
1. Dimension D Max & include mold flash or tie bar Dimension in inch Dimension in mm
burrs. Symbol minimal/maximal minimal/maximal
2. Dimension E1 does not include inter lead flash. A - / 0.210 - / 5.33
3. Dimension D & E1 include mold mismatch and are A1 0.010 / - 0.25 / -
determined at the mold parting line. A2 0.150 / 0.160 3.81 / 4.06
4. Dimension B1 does not include dam bar protrusion/ B 0.016 / 0.022 0.41 / 0.56
infusion. B1 0.048 / 0.054 1.22 / 1.37
5. Controlling dimension is inch. C 0.008 / 0.014 0.20 / 0.36
6. General appearance spec. should base on final visual D - / 2.070 - / 52.58
inspection spec. E 0.590 / 0.610 14.99 / 15.49
E1 0.540 / 0.552 13.72 / 14.02
e1 0.090 / 0.110 2.29 / 2.79
L 0.120 / 0.140 3.05 / 3.56
a 0 / 15 0 / 15
eA 0.630 / 0.670 16.00 / 17.02
S - / 0.090 - / 2.29

Specifications subject to change without notice,contact your sales representatives for the most recent information.

15/19 Ver 1.3 PID 89516 05/01

 SyncMOS Technologies Inc. SM89516
May 2001

44L Plastic Chip Carrier (PLCC) L

E HE GE

D
A2
HD
A1

A
C

θ b1 b Dimension in inch Dimension in mm

e Symbol minimal/maximal minimal/maximal
A - / 0.185 - / 4.70
GD A1 0.020 / - 0.51 / -
A2 0.145 / 0.155 3.68 / 3.94
b1 0.026 / 0.032 0.66 / 0.81
Note: b 0.016 / 0.022 0.41 / 0.56
1. Dimension D & E does not include inter lead flash. C 0.008 / 0.014 0.20 / 0.36
2. Dimension b1 does not include dam bar protrusion/ D 0.648 / 0.658 16.46 / 16.71
intrusion. E 0.648 / 0.658 16.46 / 16.71
e 0.050 BSC 1.27 BSC
3. Controlling dimension: Inch
GD 0.590 / 0.630 14.99 / 16.00
4. General appearance spec. should base on final visual GE 0.590 / 0.630 14.99 / 16.00
inspection spec. HD 0.680 / 0.700 17.27 / 17.78
HE 0.680 / 0.700 17.27 / 17.78
L 0.090 / 0.110 2.29 / 2.79
θ - / 0.004 - / 0.10
y / /

Specifications subject to change without notice,contact your sales representatives for the most recent information.

16/19 Ver 1.3 PID 89516 05/01

 SyncMOS Technologies Inc. SM89516
May 2001

44L Plastic Quad Flat Package

C

L
L1
S
θ2
e
R1

D2 D1 D

Gage Plane
b 0.25 mm
θ3
A2
R2

A1
E2
E1 A
E

e1 Dimension in Inch Dimension in mm

seating plane C Symbol minimal/maximal minimal/maximal
A - / 0.100 - / 2.55
e A1 0.006 / 0.014 0.15 / 0.35
A2 0.071 / 0.087 1.80 / 2.20
b 0.012 / 0.018 0.30 / 0.45
Note:
c 0.004 / 0.009 0.09 / 0.20
Dimension D1 and E1 do not include mold protrusion. D 0.520 BSC 13.20 BSC
Allowance protrusion is 0.25mm per side. D1 0.394 BSC 10.00 BSC
Dimension D1 and E1 do include mold mismatch D2 0.315 8.00
E 0.520 BSC 13.20 BSC
and are determined datum plane.
E1 0.394 BSC 10.00 BSC
Dimension b does not include dam bar protrusion. E2 0.315 8.00
Allowance dam bar protrusion shall be 0.08 mm total e 0.031 BSC 0.80 BSC
in excess of the b dimension at maximum material L 0.029 / 0.041 0.73 / 1.03
condition. Dam bar cannot be located on the lower L1 0.063 1.60
R1 0.005 / - 0.13 / -
radius or the lead foot.
R2 0.005 / 0.012 0.13 / 0.30
S 0.008 / - 0.20 / -
θ 0° / 7° as left
θ1 0° / - as left
θ2 10° REF as left
θ3 7° REF as left
C 0.004 0.10

Specifications subject to change without notice,contact your sales representatives for the most recent information.

17/19 Ver 1.3 PID 89516 05/01

 SyncMOS Technologies Inc. SM89516
May 2001

eMCU writer list

Company Contact info Programmer Model Number
Advantech Tel:02-22182325 LabTool - 48 (1 * 1)
7F, No.98, Ming-Chung Rd., Fax:02-22182435 LabTool - 848 (1*8)
Shin-Tien City, Taipei, Taiwan, E-mail:
ROC [email protected]
Web site:
http://www.aec.com.tw

Caprilion Tel:07-3865061 UNIV2000

P.O. Box 461 KaoHsiung, Taiwan, Fax:07-3865421
ROC E-mail:
Web site: [email protected]
http://www.market.net.tw/ ~ cap/

Hi-Lo Tel:02-87923301 All - 11 (1*1)

4F, No. 20, 22, LN, 76, Fax:02-87923285 Gang - 08 (1*8)
Rui Guang Rd., Nei Hu, Taipei, E-mail:
Taiwan, ROC. [email protected]
Web site:
http://www.hilosystems.com.tw

Leap Tel:02-29991860 ChipStation (1*1)

6th F1-4, Lane 609, Fax:02-29990015 SU - 2000 (1*8)
Chunghsin Rd., Sec. 5, Sanchung, E-mail:
Taipei Hsien, Taiwan, ROC [email protected]
Web site:
http://www.leap.com.tw

Xeltek Electronic Co., Ltd Tel:+86-25-4408399, 4543153-206 Superpro/2000 (1*1)

338 Hongwu Road, Nanjing, China E-mail: Superpro/680 (1*1)
210002 [email protected], Superpro/280 (1*1)
Web site: [email protected] Superpro/L+(1*1)
http://www.xeltek-cn.com

Specifications subject to change without notice,contact your sales representatives for the most recent information.

18/19 Ver 1.3 PID 89516 05/01

 SyncMOS Technologies Inc. SM89516
May 2001

Feedback / Inquiry:

To :SyncMOS Technologies, Inc. From :

Attn :MKT / Customer Service Dept. Company :
Fax :886-3-579-2960
:886-3-578-0493
Dept, Section :
Tel :886-3-579-2988
:886-3-579-2926
Position Title :

Inquiry Date :

Ref No :

: Request customer logo as below:

Specifications subject to change without notice,contact your sales representatives for the most recent information.

19/19 Ver 1.3 PID 89516 05/01