CRT 9028

CRT 9128
PRELIMINARY

VTLC
Video Terminal Logic Controller
FEATURES PIN CONFIGURATION
o BUilt-in High Frequency (4-14 MHz) Oscillator
o Built-in Video Shift Register DA8 '-' 40 DA7
o Built-in Character Generator DA9 2 39 DA6
OBi-Directional Smooth Scroll Capability DA10 38 DA5
o Visual Attributes Include Reverse Video, Intensity GND
XTAL2
4
5
37
36
DA4
DA3
Control, Underline and Character Blank XTALl 35 bA2
o Separate HSYNC, VSYNC and VIDEO Outputs VIDEO 34 DAl
o Composite Sync (RS 170 Compatible) Output INTOUT 8 33 DAO
o Absolute (RAM address) Cursor Addressing DWR
32
DB7

o MASK Programmable Video Parameters: 000

001
10
90
11
31
30
DB6
DB5
Dots Per Character Block (6-8) 002 12 29 DB4
Raster Scans Per Daia Row (8-12) 003 13 28 DB3
Characters Per Data Row (32, 48, 64, 80) 004 14 27 DB2
005 15 26 DBl
Data Rows Per Page (8,10,12,16,20,24 or 25)
25 DBO

I
006 ( 16
Horizontal Blanking (8- 64 Characters)
Horizontal Sync Front Porch (0-7 Characters)
007
HSYNC
(
(
17
18
24
23 ..
AID

..
Horizontal Sync Duration (1-64 Characters) VSYNC ( 19 22
Horizontal Sync Polarity CSYN [ 20 21 vcc
Two Values of Vertical Blanking
CAT 9028 CAT 9128
Two Values of Vertical Sync Front Porch (0-63 Scan
Pin 23 AD Pin23 DS
Lines)
Pin 22 WR Pin22 A/W
Two Values of Vertical Sync Duration (1-16 Scan
Lines)
Vertical Sync Polarity
Internal 128 Character 5x8 Dot Font Problems
Character/Cursor Underline Position o Fill (Erase) Screen Capability
Scan Rowand Column for Thin Graphics Entity o Standard 8-bit Data Bus Microprocessor Interface
Segments o Wide Graphics with Six Independently Addressable
Scan Rows and Columns for Wide Graphics Entity Segments Per Character Space
Elements o Thin Graphics with Four Independently Addressable
o Software Enabled Non-Scrolling 25th Data Row Avail- Segments Per Character Space
able with 25 Data .Row /Page Display o Single + 5V Supply
o Non-Interlace Display Format o COPLAMOS® n-Channel Silicon Gate Technology
o Separate Display Memory Bus Eliminates Contention o TTL Compatible
GENERAL DESCRIPTION
The CRT 9028 VTLC and CRT 9128 VTLC are mask pro- similar microprocessors or microcomputers. The CRT 9128
grammable 40 pin COPLAMOS® n-channel MOS/LSI Video regulates the data flow with a data strobe (OS) and read/
Display Controller Chips that combine video timing, video write (R/W) enable signals for use with the 6500, Z8'", 68000
attributes, alphanumeric and graphics generation, smooth and similar microprocessors or microcomputers.
scroll and screen buffer interface functions.
The VTLC provides two independent data buses; one bus
The VTLC incorporates many of the features (previously
that interfaces to the processor and one that interfaces to
requiring a number of external components) required in
the display memory. Data is transferred to the display mem-
building a low cost yet versatile display interface. An inter-
ory from the processor through the VTLC eliminating con-
nal mask programmable 128 character font provides for a
tention problems and the need for a separate row buffer.
full ASCII character set. Wide graphics allow plotting and
graphing capabilities while thin graphics and visual attri-
The VTLC has an internal crystal oscillator requiring only
butes can make the display of forms straight-forward.
an external crystal to operate. Masked constants for critical
Two pinout configurations enhance the versatility of the video timing simplify programming, operation and improve
VTLC. The CRT 9028 controls data flow over the processor reliability. A separate non-scrolling status line (enabled or
system data bus through separate read (RD) and write (WR) disabled by the processor) is available for displaying sys-
strobes for use with the 8085, 8051, Z80®, 8086, and tem status.
'Z80 is a registered trademark of Zilog Corporation. 401
Z8 is a trademark of Zilog Corporation.
 CHARACTER
CLOCK

om
CLOCK

W
DISPLAY
MEMORY

_·sv
- GND

FIGURE 1. VTLC FUNCTIONAL BLOCK DIAGRAM

DESCRIPTION OF PIN FUNCTIONS
PIN NO. SYMBOL I/O NAME DESCRIPTION
3-1,40-33 DA10-0 0 Display 11 bit address bus to display memory
Address
4 GND Ground Ground Connection
5,6 XTAL2,1 I Crystal 2,1 External Crystal
An external TTL level clock may be used to drive XTAL 1 (in
which case XTAL2 is left floating).
7 VIDEO 0 Video Output This output is a digital TTL waveform used to develop the
VIDEO and composite VIDEO signals to the monitor. The
polarity of this signal is: HIGH = BLACK
LOW = WHITE
8 INTOUT 0 Intensity This pin is the intensity level modification attribute bit (synchro-
Output nized with the video data output).
9 DWR 0 Display Write strobe to display memory
Write
17-10 007-0 I/O Display 8-bit bidirectional data bus to display memory
Data
18 HSYNC 0 Horizontal Horizontal sync signal to monitor
Sync
19 VSYNC 0 Vertical Vertical sync signal to monitor
Sync
20 CSYNC 0 Composite This output is used to generate an RS170 compatible compos-
Sync ite VIDEO signal for output to a composite VIDEO monitor.
21 V" Power 5.0 V power connection
CRT 9028
22 WR I Write Strobe Causes data on the microprocessor data bus to be strobed into
theVTLC
23 RD I Read Strobe Causes data from the VTLC to be strobed onto the micropro-
cessor data bus
CRT9128
22 R/W I Read/Write Determines whether the processor is reading data from or writ-
Select ing data into the VTLC (high for read, low for write)
23 OS I Data Strobe Causes data to be strobed into or out of the VTLC from the
microprocessor data bus depending on the state of the R/W
signal
24 A/D I Register The state. of this input pin will determine whether the data is
Select being read from, or written to, the address or status register, or
a data register.
32-25 DB7-0 I/O Processor 8-bit bi-directional processor data bus
Data Bus

402
 DESCRIPTION OF OPERATION*
THE VTLC INTERNAL REGISTERS CHARACTER register. This bit is used to synchronize data
CRT 9028 transfers between the processor and the VTLC. The VTLC
will set the DONE bit to a logic one after completing a byte
Addressing of the internal VTLC data registers of the
transfer command or a FILL operation. The DONE bit is set
CRT 9028 is accomplished through the use of the AID
to a logic zero by reading from, or writing to, the CHAR-
select input qualified by the RD and WR strobes.
ACTER register. The processor must wait until the DONE
AID RD WR REGISTER OPERATION bit is 1 before attempting to change the CURSOR
0 1 0 WRITE TO DATA REGISTER ADDRESS, in order to write a character to, or read a char-
acter from, the CHARACTER register.
0 0 1 READ DATA REGISTER
0 WRITE TO ADDRESS REGISTER STATUS REGISTER
0 READ STATUS REGISTER DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO
CRT 9128 DONE X X X X X X X
Addressing of the internal VTLC data regJ?ters of!b.e CRT DONE = 1 signifies that external processor is allowed to
9128 is accomplished through use of the AID and RIW select access cursor ADDRESS andlor
inputs qualified by the OS strobe. CHARACTER registers.
AID OS R/W REGISTER OPERATION DONE = (i) signifies that external processor must wait
until VTLC completes transfer of data
o o o WRITE TO DATA REGISTER between display memory and CHARACTER
o o READ DATA REGISTER register.
o o WRITE TO ADDRESS REGISTER
o READ STATUS REGISTER DATA REGISTERS
FILADD (Fill Address) This register contains the RAM

I
The contents of the seven processor programmable reg- address of the character following the last
isters located in the upper left hand side of the Functional address to be filled. Writing to this register will
Block Diagram of figure 1 indicate the memory locations enable the VTLC "fill" circuitry. The FILL oper-
from which screen data is to be fetched and displayed as ation will then be triggered by the next processor
well as the selected modes of display operation. These reg- write to the CHARACTER register. The FILL
isters are addressed indirectly via the Address Register. operation will write the character in the CHAR-
To access one of the seven eight-bit registers, the pro- ACTER register to every location in display
cessor must first load the Address Register with the three- memory starting with the address specified in
bit address of the selected data register. The next read or the CURLO and CURHI registers through the
write to a data register will then cause the data register location preceeding the address specified in the
po.lDted to by the Address Register to be accessed. The Line FILADD register. The cursor position is not
AID controls whether writing is occurring to the Address changed after a FILL operation. Note that the
Register or to a data register. When a read operation is per- address bits DA3-DAO are internally forced to 0
formed, AID controls access to either the Status Register forcing the FILADD address to be 00, 16, 32, etc.
or to the data register selected by the Address Register. to 1920. The CURLO and CURHI registers will
REGISTER DESCRIPTION not be changed by this operation. Writing to the
CHARACTER register will cause the VTLC to
ADDRESS REGISTER reset DB? of the STATUS register to "0". Bit 7
Writing a byte to the ADDRESS register will select the will be set to 1 after the VTLC has filled the last
specified register the next time the processor writes to or memory location specified.
reads the VTLC data registers. The data register addresses
are as follows: FILADD REGISTER
STATUS REGISTER DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO
When reading the STATUS register, the DONE bit (DB7 X DA 10 DA9 DAB DA 7 DA6 DA5 DA4
of STATUS Register) will represent the current status of the

ADDRESS TYPE REGISTER

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO
X X X X 0 1 1 0 Write CHIP RESET
X X X X 1 0 0 0 Write TOSADD
X X X X 1 0 0 1 Write CURLO
X X X X 1 0 1 0 Write CURHI
X X X X 1 0 1 1 Write FILADD
X X X X 1 1 0 0 Write ATTDAT
X X X X 1 1 0 1 RDIWR CHARACTER
X X X X 1 1 1 0 Write MODE REGISTER

(X = don't care)
'NOTE: Chip Reset is required before starting operation. 403
TOSADD (Top of Screen Address) This register contains Changing the Attribute register will change the
the RAM address of the first character displayed attribute of every "tagged" character on the
at the top of the video monitor screen. In addi- screen. The functions of the remaining bits in the
tion, this register controls selection of either of ATTDAT register are not affected by the display
two mask programmable vertical scan rates. character's TAG bit.

TOSADD REGISTER There are two display modes, "alphanumerics" and

DB? DB6 DB5 DB4 DB3 DB2 DB1 DBO "graphics". In the alphanumeric mode, visual attributes may
be selected by the TAG bit. In the graphics mode, a tagged
TIM DA10 DA9 DAB DA? DA6 DA5 DA4 character will be a normal alphanumeric character. This
allows a screen to display a mix of graphic and alphanu-
Note that address bits DA3-DAO are internally meric characters or visually attributed alphanumeric char-
forced to 0 forcing the first address at the begin- acters. The display variations of the alphanumerics and
ning of each row to be 00, 16,32, etc. to 1920. graphics modes are summarized by the following:
The most significant bit of this register (TIM)
is used to select between the two mask pro-
grammed sets of vertical retrace parameters ATTDAT REGISTER
(scan A and scan B). This allows software DB? DB6 DB5 DB4 DB3 DB2 DB1 DBO
selection of, for example, 50/60 HZ.
TIM = 0 enable raster scan A (60 Hz) DB? MODE DB? = 1 enables graphics
TIM = 1 enable raster scan B (50 Hz) SELECT mode display (No
attributes allowed)
CURLO (Cursor Low) This register contains the eight DB? = 0 enables alpha
lower order address bits of the RAM cursor mode display
address. All FILL screen and character transfer
operations begin at the memory location pointed DB6 CURSOR DB6 = 1 inhibits VIDEO dis-
to by this address. SUPPRESS play at cursor time
by forcing the
CURLO REGISTER VIDEO output to
DB? DB6 DB5 DB4 DB3 DB2 DB1 DBO background level
during cursor dis-
DA? DA6 DA5 DA4 DA3 DA2 DA 1 DAO
playtime
DB6 = 0 enables VIDEO
CURHI (Cursor High) This register contains the three
display at cursor
higher address bits of the RAM cursor address
time
(DA10, DA9, DAB). All FILL screen and char-
Note: a blinking
acter transfer operations begin at the memory
cursor display can
location pointed to by this address. In addition,
be achieved by
this register contains the Smooth Scroll Offset
toggling this bit
Values SS3-SS0 which determine the number
under processor
of scan lines that the data is shifted on the
control.
screen. The MSB of this register (SLE-status line
enable) is the enable for the non-scrolling status
DB5 CURSOR DB5 = 1 enables underline
line (this feature is available only on a part pro-
DISPLAY cursor display
grammed for 25 data rows).
DB5 = 0 enables block cur-
sordisplay
CURHI REGISTER Note: An underline
DB? DB6 DB5 DB4 DB3 DB2 DB1 DBO cursor in an under-
line character
SLE SS3 SS2 SS1 SSO DA10 DA9 DAB
attribute field will
be dashed.
SLE = 1 enables non-scrolling 25th
status line
DB4 SCREEN DB4 = 1 for white screen
SLE = 0 disables and blanks non-
and black
scrolling status line
characters
DB4 = 0 for black screen
SS3-SS0 Smooth Scroll Offset Value
and white
characters
ATTDAT (Attribute Data) This register specifies the vis- Note: this is a
ual attributes of the video data and the cursor screen attribute
presentation. The visual attributes specified in (versus character
the ATTDAT register (DB3-DBO) are enabled or attribute) bit and
disabled by a TAG bit that is appended to the sets the default
ASCII character written to the CHARACTER Video background
register. Every character on the screen with its level.
TAG bit set is displayed with the same attribute.
404
 DB3 CHARACTER DB3 = 1 to enable Video register. The VTLC takes that character
SUPPRESS suppress and stores it in the display memory in the
DB3 = 0 to inhibit Video location specified by the CURLO and
suppress CURHI registers. In Byte Transfer Read
I- This bit allows Mode, the processor reads this register
iD character blinking causing the VTLC to fetch the character
(!J and blanking under whose address is specified in the CURLO
~ processor control and CURHI registers from the display
fn INTENSITY DB2 = 1 allows the INTOUT
memory and place it in the CHARACTER
register. The processor then reads the
£:) DB2
UJ
..J output pin to go character and initiates another fetch from
co high for the char- memory cycle. In FILL mode, writing a byte
<l:
en actertime to this register will initiate a FILL operation.
is DB2 = 0 inhibits the All VTLC/memory data transfers take place
II: INTOUT output pin during horizontal and vertical video retrace
o from going high blank time.
£:)
UJ
al<l: DB1 UNDERLINE DB1 = 1 will cause the char- CHARACTER REGISTER
z acterto be DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO
UJ underlined
DB1 = 0 will inhibit the TAG BIT + 7 BIT ASCII CHARACTER
underline
CHARACTER SET
DBO REVERSE DBO = 1 will cause the Using the DB7-DBO data bus 1/0 pins and the MOD SEL
VIDEO standard fore- bit in the ATTDAT register, the user can address 128 char-
ground and back- acters, a six segment "wide graphics" and a four segment
ground Video "thin graphics" entity. Included in the 128 mask program-
levels (selected mable characters can be the 96 standard ASCII characters
with DB4) to be and 32 special characters.
reversed for the
character time A. (MODE SEL = 1) GRAPHICS MODE
DBO = 0 will inhibit reverse
video This mode allows an intermix of alpha-numeric and
graphics characters. No attributes are permitted in this
mode. If TAG BIT = 1, the character will be an alpha-
MODE The AUTO INCREMENT bit in this register
numeric. If TAG BIT = 0, the character will be a graph-
specifies whether or not the display memory
ics character.
character address is automatically incre-
mented by the VTLC after every readlwrite of
CHARACTER REGISTER
the CHARACTER register. Note: The visible
cursor position is not affected. ALPHANUMERIC: TAG BIT = 1
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO
MODE REGISTER
TAG = 1 t-- ALPHA-NUMERIC CHARACTER ~
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO
AUTO x X X X X X X DB6-DBO Specify character
INC

DB7 AUTO DB7 1 to enable CHARACTER REGISTER

INCREMENT automatic character GRAPHICS: TAG BIT = 0
address
The RAM address is DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO
incremented after the TAG=O WIT SEG6 SEG5 SEG4 SEG3 SEG2 SEG1
VTLC completes a dis-
play memory access DB6 WIT = 1 specifies a wide graphics
initiated by a processor character
to RAM or RAM to WIT = 0 specifies a thin graphics
processor character character
transfer.
WIDE GRAPHICS ONLY:
DB7 = 0 to disable DB5-4 SEG6-5 = 1 to turn on graphics
automatic increment entity segment
SEG6-5 = 0 to turn off graphics
CHARACTER This register allows access to the display entity segment
memory for both byte transfers and FILL
operations. In BYTE Transfer Write Mode, Note that DB5 and DB4 have no meaning in the
the processor first writes a character to this thin graphics entity.
405
 WIDE AND THIN GRAPHICS: the DD?-DDO data bus as shown in the Display Memory
Timing of figure 2. Because the system data bus is isolated
DB3-0 SEG4-1 if any bit = 1, corresponding from the display data bus, the VTLC maintains complete
graphics entity segment ON control over access to display memory. All data flow between
display RAM and the processor or the VTLC takes place
It any bit = 0, corresponding through the VTLC. Refer to the VTLC Display Memory
graphics entity segment OFF Access Timing of figure?

DISPLAY MEMORY ACCESS

B. (MOD SEL = 0) ALPHA-NUMERICS MODE
Processor/display memory access is accomplished
through the CHARACTER register of the VTLC. All proces-
This mode allows display of alpha-numeric characters sor transfers to or from the CHARACTER register take place
with attributes. If DB? is set to a logical one, the attri-
only when the DONE bit is high. The DONE bit is used to
bute(s) specified in the ATTDAT register will be ena- synchronize data transfers between the VTLC and the pro-
bled for that character. ifTAG BIT is cleared, attributes cessor as shown in the Typical Processor To Display Mem-
will not be enabled for that character.
ory Transfer of figure 6. When the processor needs to store
a byte of data in the display memory, it will write the byte to
CHARACTER REGISTER the CHARACTER register of the VTLC. The VTLC will
immediately reset the DONE bit indicating that the transfer
DB? DB6 DB5 DB4 DB3 DB2 DB1 DBO hardware is busy. At the next blanked Video time, the VTLC
will store the byte in the display memory, increment the
TAG t-- ALPHA-NUMERIC CHARACTER--l character address, (if auto increment is enabled) and set
the DONE bit. When the processor needs to read a byte of
DB? = 1 to enable attribute(s) for character. data from the display memory, it will read the CHARACTER
DB? = 0 to disable attribute(s) for character. register. The VTLC will fetch the desired byte from the dis-
play memory during the next blanked VIDEO time, incre-
DB6-DBO Specify character ment the character address (if enabled), and set the DONE
bit. When the processor detects that the DONE bit is set, it
will read the CHARACTER register to get the data byte from
SEGMENT SEGMENT the VTLC. This read will reset the DONE bit and cause the
6 3 VTLC to fetch the next byte of data from the memory.

SEGMENT SEGMENT If auto increment is not enabled, the processor must set
5 2 the cursor address in the CU RLO and CURHI register to the
address of the memory location being read from, or written
SEGMENT SEGMENT into, before every access to the CHARACTER register.
4 1
It should be noted that Auto Increment does not affect the
WIDE GRAPHICS ENTITY visible cursor location. If auto-increment is enabled, the
NOTE: scan line and column of segment current character location will equal the cursor position only
locations are mask programmable. for the first character transfered following an update of the
CURLO and CURHI registers. Note that the DONE bit must
be high before attempting to update the cursor registers
because the loading of the cursor registers will reset the
character position counters to the cursor position.
SEGMENT 3

SMOOTH SCROLL

SEGMENT4 SEGMENT2 The VTLC may be programmed to do either "jump" or

"smooth" scrolling. Jump scrolling moves the data up or
SEGMENT 1 down the monitor screen one data row at a time. Smooth
scrolling moves the data up the monitor screen one scan
line at a time. The number of scan lines and the rate they
THIN GRAPHICS ENTITY move up the screen is under processor control.

NOTE: scan line and column of segment Smooth scroll is controlled through manipulation of the
locations are mask programmable. SS3-SS0 bits of the CURHI register. These bits represent
the binary address of the first scan line of the first data row
displayed on the monitor screen (the data row whose
DESCRIPTION OF SYSTEM OPERATION beginning address is in the TOSADD register). When the
value represented by these bits is incremented, the video
The VTLC circuitry provides two control functions. One data on the monitor screen moves up by the same number
function interprets and controls data from the system pro- of scan lines. After the address of the last scan line of the
cessor interface through the data bus DB?-DBO as shown data row is loaded into the CURHI register and the VIDEO
in the Processor Timing of figure 3. The other function gen- data has moved up the last scan line of the data row, the
erates and refreshes the video image on the screen through processor resets the SS3-SS0 address to point to scan line
406
o and does a jump scroll. Jump scroll is accomplished by will remain stationary at the bottom of the screen and will
incrementing the RAM address in the TOSADD register by not move up the screen when the remainder of the display
a data row length (so that it points to the address of the first data is scrolled. Otherwise, VIDEO data on the status line
character of the new top data row on the monitor). may be manipulated as though it were normal display data.
The smooth scroll offset will not function properly when the
When programmed for a data row of 80 characters/data
status line is enabled. The memory address of the charac-
row display (1920 data words), for example, the display RAM
ters on the status line are always characters 1920-1999.
contains 25 actual rows of data (2000 RAM locations). If the NOTE: If the part is programmed for 25 data rows an addi-
smooth scroll offset equals zero, the VTLC will display the
tional mask option must be specified which makes the 25th
1919 RAM locations following the top of screen address
data row either fixed (always displayed) or a status row
when displaying data. The first data row is partially scrolled (enabled/disabled by the SLE bit).
off the screen and the 25th data row is scrolled onto the
screen when the smooth scroll offset is incremented. The
VTLC will now display the 1999 RAM locations following the
top of screen address (wrapping to 0 after address 1999). CHIP RESET
After the VTLC does a jump scroll, the processor will pro-
gram it to erase the line just scrolled off the screen (prepar- The CRT 9028 and CRT 9128 Chip Reset requires two
ing itto be scrolled onto the screen). This line now becomes steps. The system processor firstwrites the reset address
the non-displayed 25th data row. to the address register of the VTLC. The system processor
then writes a dummy character to the VTLC Data register.
NON-SCROLLING STATUS LINE Writing to the Data register resets the chip. The only state
The non-scrolling status line is only functional on a VTLC affected by the reset function is the setting of the DONE bit
that has been programmed for 25 data rows. This data row in the STATUS register.

ROM CHARACTER BLOCK FORMAT

COLUMN DOT -> C7 C6 CS C4 C3 C2 C1 co
SCAN LINE 0 -> 0 o o o o o o o
SCAN LINE 1 -> 0 o 0
SCAN LINE 2 -> 0 o 0

SCAN LINE 3 -> 0 MASK PROGRAMMABLE o o

CHARACTER BLOCK
SCAN LINE 4 -> 0 (FONT) o o
SX8
SCAN LINES -> 0 o 0
SCAN LINE 6 -> 0 o 0
SCAN LINE 7 -> 0 o 0
SCAN LINE 8 -> 0 o 0
SCAN LINE 9 -> 0 o o o o o o o
SCAN LINE 10 -> 0 o o o o o o o
SCAN LINE 11 -> 0 o o o o o o o
Mask programmable options-The ROM character block format above shows the SX8 mask programmable character font
within the character cell as defined by dots C7 through CO and scan lines 0 through 11.
Dots/Character: 6 dots/character cell = > C7 - C2 displayed
7 dots/character cell = > C7 - C1 displayed
8 dots'character cell = > C7 - CO displayed
Column dots CO and C1 will be the same as column dot C7 when more than 6 dots 'character cell are specified
when generating alpha-numerics.
NOTE: The maximum dot clock crystal frequency is dependent on the dots character programmed:
DOTS/CHARACTER MAX XTAL FREQ
6 dots 1O.S MHz max'
7 dots 12.2S MHz max'
8 dots 14.0 MHz max'
*These values are preliminary
Scan Lines per Character: 8 scan lines character = Co SLO - SL7 displayed
9 scan lines character = :' SLO - SL8 displayed
10 scan lines character = " SLO SL9 displayed
11 scan lines character ='- SLO· SL 10 displayed
12 scan lines character = '. SLO . SL 11 displayed
Thin and Wide Graphics: Dots mask programmed for vertical column C2 will be the same as backfill Columns 0 and 1
when generating wide and thin graphics.

407
MAXIMUM GUARANTEED RATINGS*
Operating Temperature Range .......................................... '" .......................... O°C to + 70°C
Storage Temperature Range ..................................... , ................................... - 55°C to + 150°C
Lead Temperature (soldering, 10 sec.) ............................................................... + 325°C
posiiive Voltage on any Pin, with respect to ground ................................................. + B.OV
Negative Voltage on any Pin, with respect to ground ............ ; ................................... ~ O.3V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the devic~ at these or at any other condition above those indicated in the operational sections of ihis
specification is not implied.
NOTE: When powering this device from laboratory or sysiem power supplies, it is important that the Absolute Maxi-
mum Ratings not be .exceeded or device failure can result. Some power supplies exhibit vOltage spikes or "glitches"
on their outputs when the AC power is switched on and off. In addition, voltage transients on the AC power line may
appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used.
ELECTRIC~L CHARACTERISTICS (TA =O°C to 70°C, Vee = + 5V ± 5%, unless otherwise noted.)
PARAMETER MIN TYP MAX UNIT COMMENTS
Address.Hold Time
tAHT 25 ns
Output Hold From Address Change
tOH 15 ns
Address Access Time
tAA 250 ns
PROCESSOR TIMING
Address Read/Write Set-up
tARWS ' 160 ns
Write Pulse Width
twpw 160 ns
Write Hold Time
tWHT 15 ns
Read Set-up Time
t RST 200 ns
R~ad Data Valid
T Rov 0 ns
Read Pulse Width
t~pw 2qO ns
Data Write Falling Set-up
10wFs 120 ns
Data Write Rising Set-up
i owRs 160 ns

Crystal specification (Applies for 4-14 MHz):

Series Resonant
50 ohms max series resistance
1.5 pflyp parallel capacitance
Operation below 4 MHz requires external crystal oscillator

DA10·0 ADDRESS ADDRESS

DWR

READ DATA READ DATA

007·000
FROM RAM FROM RAM
VTLCINPUT
FROM RAM

NOTE: DISPLAY ADDRESS BUS DA10·DAO MUST NOT CHANGE WHILE DWR IS LOW

FIGURE 2. DISPLAY MEMORY TIMING

DB7·0

PROCESSOR WRITES
TOVTLC
(1) If set·up time is not met, screen may glitch when cursor or attribute
registers are changed during active video time.
(2) Minimum set·up time toensure valid data into VTLC internal registers.

FIGURE 3. P~OCESSOR TIMING.,;!

409
 VERTICAL TIMING VERTICAL
SYNC
I DURATION I
I 1< >1 I
VSYNC~ I+-- I I

VSYNC
DELAY i (-----\\.. __I'--__--IIf-I_______,
I I I 1/
I I
V BLANKING _ _ _ _ _...11 \ /1 r--
I+- NUMBER OF BLANKED -+I I~I
I SCAN LINES 14-- ~Ys"I.~~~~; ~
DATA ROWS

HORIZONTAL TIMING HORIZONTAL

SYNC
DURATION
~ I
HSYNC _ I+- I I
DELAY I I I I
HSYNC _ _ _ _--'I'----'t---....f-_ _--'-I _ _ _--IIf-I _______'
I I I II
I
H BLANKING II--~----------\ II r--
-------'~ NUMBER OF ----.j Ir---I
cJk~ZC"f~RS I+- ~y~P~~~~; ----.;
CHARACTERS
NOTE: Video parameters above are mask programmable

FIGURE 4. VERTICAL AND HORIZONTAL SYNC TIMING

HSYNC~ n
I I
n n
I
n
I
n
I I I I

VSYNC I I
I
I
I I
I I I I
I I
-i- H-----I
I I
I--HI2-o.l I I I
CSYNC

NCJTE: Delays between pulse edges and pulse width values may vary due to mask programmable features.
'H represents horizontal interval

HSYNC ~ HSYNC
______~rl~_____
-1j d t<--- ~~d~r_--------
_______
CSYNC
Ji'---_ __ CSYNC U
d = HSYN Delay -CSYN Delay

WITHIN VERTICAL SYNC OUTSIDE OF VERTICAL

PULSE TIME SYNC PULSE TIME

FIGURE 5. VIDEO SIGNAL TIMING

ro"7-0 XXXXXXXXX
PROCESSOR
BUS
ASCII CHARACTER
xxxxxxxxxxxxxxxx
~----------------~ PROCESSOR WRITES CHARACTER
VTLC CHARACTER REGISTER
(CAUSES DONE BIT RESET)

'DONE
(DB7 OF STATUS
REGISTER)
\'--____----'1
DISPLAY DISPLAY ASCII CHARACTER
JDD7-0 CHARACTER CHARACTER
DISPLAY _ _ _- / '--------1
BUS
~WR----------------------------; VTLCWRITES
CHARACTER REGISTER
DONE = 1 SIGNIFIES THAT PROCESSOR MAY ACCESS CHARACTER REGISTER TO DISPLAY MEMORY
DONE = 0 SIGNIFIES THAT PROCESSOR MAY NOT ACCESS CHARACTER REGISTER

FIGURE 6. TYPICAL PROCESSOR TO DISPLAY MEMORY TRANSFER

410
 TYPICAL DISPLAY TIMING
TIME:

DA10-0

DWR .!II DISPLAY MEMORY READ

READ AND WRITE DISPLAY MEMORY TIMING

TIME:

DA10-0

DWR ll/
----------------~\

\
~
______ _'
/
HIGH FOR READ~ I
,~-------I

PROCESSOR WRITES/READS TO/FROM

CHARACTER REGISTER LL
VTLC WRITES/READS
TO/FROM DISPLAY MEMORY LOW FOR WRITE II!!I 17
,---------------------------~ CHARACTER
.j:>.
..... ;ANKING --I hi:' DI~P~AY Ih -: I

FILL DISPLAY MEMORY COMMAND

TIME:

DA10-0

(LAST LOCATION
DWR
,-----h~ , H FILLED)
PROCESSOR WRITES TO FILADD REGISTER
FOLLOWED BY WRITE TO CHARACTER REGISTER ~TO
LAST LOCATION
(
DONE
(DB7 OF STATUS
REGISTER)
~ ~7 ~1 m
DD7-0

NOTE: "N CHARACTERSIDATA ROW

FIGURE 7. VTLC DISPLAY MEMORY ACCESS TIMING

 APPENDIX-STANDARD PARTS-CRT 9028-000/CRT 9128-000

I. ROM CHARACTER BLOCK FORMAT:

COLUMN DOT - . C7 C6 C5 C4 C3 C2 C1

SCAN LINE a a a a a a a a
SCAN LINE 1 a a
SCAN LINE 2 a a
SCAN LINE 3 a CHARACTER BLOCK a
x
5 8 CELL
SCAN LINE 4 a a
SCAN LINE 5 a a
SCAN LINE 6 a a
SCAN LINE 7 -,' a a
SCAN LINE 8 a a
SCAN LINE 9 - .. ' a a a a a a a

DOTS PER CHARACTER: 7

DOT CLOCK XTAL FREQUENCY (MHz): 10.92
II. HORIZONTAL TIMING (IN CHARACTER TIMES):
CHARACTERS PER DATA ROW: 80
HORIZONTAL BLANKING: 20
HORIZONTAL SYNC DELAY: 4
HORIZONTAL SYNC PULSE WIDTH: 8
HORIZONTAL SYNC POLARITY: NEGATIVE ACTIVE
I+----HORIZ BLANKING---..J
ACTIVE VIDEO , . I ACTIVE VIDEO
VIDEO ---------1 L.I_______-_
HSYNC

HORIZ SYNC DELAY -I. .1 .. HORIZ SYNC--.l

PULSE WIDTH

III. VERTICAL TIMING:

CHARACTER ROWS: 24
SCAN LINES PER CHARACTER: x10
TOTAL VISIBLE SCAN LINES: 240
VERTICAL SYNC POLARITY: NEGATIVE ACTIVE

IV. VERTICAL SYNC TIMING (IN SCAN LINES):

60 Hz VERTICAL BLANKING: 20
60 Hz VERTICAL SYNC DELAY: 4
60 Hz VERTICAL SYNC PULSE WIDTH: 8
ALTERNATE (50 Hz) VERTICAL BLANKING: 72
ALTERNATE (50 Hz) VERTICAL SYNC DELAY: 30
ALTERNATE (50 Hz) VERTICAL SYNC PULSE WIDTH: 10

L...- VERTICAL BLANKING --.I

ACTIVE VIDEO ,- I ACTIVE VIDEO
VIDEO --------1 ,--I_____-__-_-_
VSYNC
--\V~S;YNNCr.nD~E~LA~Y~=414;:~·~1~4--VERTSYNC~
PULSE WIDTH
412
V. COMPOSITE SYNC OUTPUT (IN CHARACTER TIMES):
COMPOSITE SYNC DELAY: 2
COMPOSITE SYNC PULSE WIDTH: 8

ACTIVE VIDEO ACTIVE VIDEO

VIDEO --------, ,--------
CSYN

CSYN DELAY - ~f--_

... .....
, .. I-----J.-tl CSYN PULSE WIDTH

VI. UNDERLINE ATTRIBUTE AND CURSOR LINE: SCAN LINE 9

VII. WIDE GRAPHICS FIGURE DEFINITION:

COLUMN -> C7 C6 C5 C4 C3 C2 C1

SCAN LINE 0 ->

SCAN LINE 1 -> SEGMENT 6 SEGMENT 3

SCAN LINE 2 ->

SCAN LINE 3 ->

SCAN LINE 4 -> SEGMENT 5 SEGMENT 2

SCAN LINE 5 ->

SCAN LINE 6 ->

SCAN LINE 7 ->

SCAN LINE 8 -> SEGMENT 4 SEGMENT 1

SCAN LINE 9 ->

VIII. THIN GRAPHICS FIGURE DEFINITION:

COLUMN DOT -> C7 C6 C5 C4 C3 C2 C1

SCAN LINE 0 ->

-
S
SCAN LINE 1 -> E
G
M
SCAN LlNE2 -> E
N
SCAN LlNE3 -> T

SCAN LlNE4 -> 3

SCAN LINE 5 -> I SEGMENT 4 SEGMENT 2 I

S
SCAN LlNE6 -> E
G
SCAN LINE 7 -> M
E
SCAN LINE 8 -> N
T
SCAN LINE 9 -> 1
-
SEGMENT 4 = SCAN LINE 5; C7, C6, C5, C4
SEGMENT 3 = C4; SCAN LINES 0, 1, 2, 3, 4, 5
SEGMENT 2 = SCAN LINE 5; C4, C3, C2, C1
SEGMENT 1 = C4; SCAN LINES 5, 6, 7, 8, 9

413
 KEYBOARD
CONN

;;;f D~I'! OPTIONAL

SERIAL
EEROM XTAL 1 XTAL2
XTAL 1 XTAL2
P2.3 CS
INTO LS24G'
P2.2 SK VERTICAL SYNC }
VSYNCP~.~--------~ ~
P2.1 DI
P2.0 DO 'HORIZONTAL SYNC TO MONITOR
...---aINT1 HSYNC b-------j'-----j
I P25 680 VIDEO
COMM ~Io I~
VIDEO 3900
CONN
INTOUTI I~

f------il TxD
PO.l-PO.O K. )j DB7-DB.B'
~ 8051
DWRP~------------,
-l>- OR
EQUIVALENT
CRT 9028
::> T - I P'6
DISPLAY MEMORY
:> • I IRxD
K. ADDRESS BUS .Il A1,ff-AG
PRINTER 1488 2KX8
CONN ~ STATIC RAM
'Q--I----OI P'5

:~t £: \. DATA BUS ~ D7-DG'

CRT 9028
TYPICAL APPLICATION
 LS241t
,VERTICAL SYNC) }
VSYNC p-1It-'- - - - - - I
HORIZONTAL SYNC
HSYNC b'""'.~--+----1 TO MONITOR

VIDEO 10 I~
INTOUTI I~

DB7-DBl!'
=
DWR

CRT 9128

DISPLAY MEMORY

DA HI'-DAll' ADDRESS BUS A tff-M

2KX8
STATIC RAM

DD7-DD0~
AID
DS
DATA BUS :i D7-Dl!'

R/iN

CRT 9128
TYPICAL APPLICATION
 .00.0000 • • • • • 000 08000000 0 • • 00000 a ••••• Co 00000080 000 • • • 00 . 0 . 0 . 0 . 0
N 08008000 0000.000 00800000 80080000 .00000.0 00000080 00.000.0 oaoaoaoo
~ <b 00800800 00.0.0.0 000.0000 80008080 .00000.0 000000.0 00.000.0 . 0 . 0 . 0 . 0
~
U 0.00.000 000 • • • 00 00008000 80000000 800000.0 000000.0 00.000.0 0.0.0.00
80080000 00008000 Doooo.on 0.000000 0 • • • • • 00 00000080 000 • • • 00 . 0 . 0 . 0 . 0
00800800 00000.00 00000000 DODoooon •••••••0 00800000 000 • • • • 0
00.00000
~ N 0.00.000 08008000 00000000 OOO.LJOOD 000.0000 0.000000 00.00000
000.0000
<b .00.0000 oa080000 00000080 0080aooo 00.00000 .0000000 00.00000
000.0000
;: U 0800.000 0 • • 00000 00000000 08000800 0.000000 0.000000 000.0000
000.0000
oo.opaoo 0 • • • • 000 00000000 80000080 ••••••• 0 001100000 oO ••• l:Iao 00008000
-r---
• • • • • • • 0 000000.0 000.0000 00808000 ••••••• 0 00000000 000 • • • • 0 00000000
N aoa08080 • • • • • 0.0 000.0000 00.0.000 08000000 00000000 00.00000 00080000
0 <b • • 000 • • 0 .000.0.0 000.0000 00808000 00 • • 0000 ••••••• 0 000 • • 000 0 • • 0 • • 00
u • • • 0 • • • 0 .000.0.0 000.0000 00.0.000 08000000 !!IooooO!!lo 001000000 aoooooao
• • • • • • • 0 000000.0 00080000 Do.aBODD • • • • • • • 0 oooooopo OOllllllllao 00000000
000.0000 0000.0.0 00000000 00000000 000000.0 00000.00 00000000 00000000
0 N 000.00.0
00 • • • 000 00000000 .00000110 000000.0
0 0000.000 000000.0 00000000
<b 0.0.0.00 00.000.0 00000 • • 0 0.000.00 000000.0 000.0000 •••••••0 ••• 0 ••• 0
u 000.0000 0.0000.0 00000008 00808000 000000.0 00800000 .00000.0 00000000
ODoBDODO 800000.0 00000000 000.0000 • • • • • • • 0 a.GooOoO 00000000 00000000
00.00000 • • • • • • • 0 000.0000 00000000 .00000.0 00000000 00.000.0 00000000
N 0.000000 . 0 . 0 . 0 . 0 00080000 00000000 0.000.00 .0000080 000.0.00 .00000.0
0 <b • • • • • • • 0 80.0.0.0 0 • • • • • 00 00.00 • • 0 00.0.000 • • • • • • • 0 0000.000 0 • • 0 • • 00
U 0.[300000 .00000.0 000.0000 0000000. 000.0000 oooooboo 0000.000 000.0000
00.00000 • • • • • • • 0 000.0000 00000000 ••••••• 0 ooooqooo • • • • • • • 0 00000000
f---- - CiDOOiaooo .000.0.0 0.0.0800 00000000 • • 0000.0 00000000
• • • • • • 00 00.000.0
0 N 00000.00 • • 00.0.0 00 • • • 000 00000000 00000080 .0.000.0 . 0• • • • • 0 00 • • 00.0
0 <b ••••••• 0 .0.0.0.0 ••••••• 0 00.00.00 000000.0 .00.00.0 0000000. 00.0.0.0
u 00000.00 .00 • • 0.0 00 • • • 000 00000000 000000.0 .000.0.0 0000000. 00.00 • • 0
opoo.ooo .000.0.0 0.0.0.00 OOOOOOo[] 0000 • • 00 .0000 • • 0 000000.0 00.000.0
000000.0 .00000.0 00 • • • 000 0 • • • • 000 00000000 • • 000000 00000000 00 • • • • • 0
N 000000.0 0.0000.0 0.000.00 .00.0I!lClo .00000.0 00.00000 000000.0 00000.0.
0 <b 000.00.0 00 • • • 0.0 .00000.0 • 00.00.0 • • • • • • • 0 000 • • • • 0 .0 • • • • • 0 00000.0 •
~ u 000000.0 0.0000.0 00000000 • 00.0000 .00000.0 00.00000 00.000.0 00000.0 •
000000.0 .00000.0 00000000 0 • • 00000 00000000 • • 000000 00000000 00 • • • 000
000.0000 .000.0.0 00000000 0 • • 0 • • 00 •••••••0 • • 000 • • 0 000 • • • • 0 00.000.0
0
0
N 000.0000 oao.oo.o 00000000 .00.00.0 000.0000 00.0.000 00.00000 000.0.00
<b 0.0.0.00 00.000.0 .0000080 BOO.0080 00080000 000.0000 00.00000 0000.000
~ u 00 • • • 000 0.0.00.0 0.000.00 .00.00.0 000.0000 00.0.000 000.0000 000.0.00
o 000.0000 .000.0.0 00 • • • 000 0 • • 0 • • 00 ••••••• 0 • • 000 • • 0 • • • • • • • 0 00.000.0
o
o 000.00.0 • • • • 00.0 00000000 • • 000000 0.00 • • • 0 • • • • • • 00 000 • • • • 0 00 • • • • 00
0 • • • 00.0 0000.0.0 00000000 .0.00000
cO ;: N
<b .000.0.0 00 • • 00.0 • • 000000 .0'] • • • • 0
• 000.0.0
.00000.0
000000.0
000 • • • 00
00.00.0 •
00.00.0.
000000.0
0000 • • 00
,....
N 0 u 0 • • • 00.0
000.00.0
0000.0.0
• • • • 00.0
00.00000
00000000
.0000000
.0000000
• 00000.0
0 • • • • • 00
000000.0
• • • • • • 00
00.00.0 •
000 • • 00.
000000.0
00 • • • • 00
m -_.
03 N
.00000.0
.0.000.0
• • • 000.0
000.00.0
0000.0.0
00000.00
.000 • • 00
.00.00.0
.0000000
.00.0000
• • • • • 000
00000.00
0.000000
.00.0000
00 • •0000
0000 • • 00
N ~
o 0
<b
u
.0.000.0 0000.0.0 0 • • 0.0.0 .00.00.0 .00.0000 000000.0 .00.0000 000000.0
m • • • • • 0.0
000000.0
000.00.0
• • • 000.0
.00.00.0
o • • o~.oo
0.0.00.0
00.11 • • 00
.00.0000
••••••• 0
00000.00
• • • • • 000
0 •••••• 0
000.0000
0000 • • 00
00 • • 0000
I- 1-- ~~
------------
a: N
.000.0.0
.0.0.0.0
• • • • 00.0
0000.0.0
oaooo • • o
00.00 • • 0
.00 • • • 00
.0.000.0
.00000.0
.00.00.0
• • • • • • 00
000000.0
000 • • 000
00.0.0.0
00 • • • • • 0
00000.00
U 0 <b .0.0.0.0 0000.0.0 000.0000 .0.000.0 .00.00.0 000000.0 00.0.0.0 000000.0
0 u • • • • • 0.0 • • • • 00.0 • • 00.000 .0.000.0 .00.00.0 000000.0 00.0.0.0 000000.0
Clooooo.o 000000.0 • • 000.00 • • • 00.00 ••••••• 0 • • • • • • 00 000 • • • 00 00 • • • • 00
0 • • • 00.0 000.00.0 0.00.000 0000.000 0 • • • • • 00 .0000000 ••••••• 0 00000000
0 N .000.0.0 • • • • • 0.0 0.0.0.00 •••••••0 .00000.0 .0000000 000.00.0 00.000.0
0 • • • • • • 00
<b .000.0.0 0.0.00.0 •••••••0 0.00.000 .00000.0 •••••••0 00.000.0
0 u • • • • • 0.0 00 • • 00.0 0.0.0.00 00110.000 .00000.0 110000000 00.000.0 00.00000
000000.0 000000.0 00.00.00 000 • • 000 ••••••• 0 .0000000 000 • • • 00 00000000
00000000 000000.0 00.0.000 • • 00 • • 00 0.000.00 0.00 • • 00 00.000.0 00.00.00
N •••••••0 0.11.00.0 ••••••• 0 . 0 • • 00.0 .00000.0 .00.00.0 00.00080 00.0.0.0
00 <b 0 • • • • • 00 .0.0.080 00.0.000 .00.00.0 .0000080 .00.00.0 00.000.0 00.0.0.0
u 00 • • • 000 .0.0.0.0 ••••••• 0 .00000.0 .00000.0 .00.0080 00.000.0 00.0.0.0
000.0000 000000.0 oo.o~ooo 80000.00 0 • • • • • 00 o • • oo.on 000 • • • 00 000.00.0
000.0000 000000.0 ·00000000 0 • • 000.0 0 • • 0 • • 00 0 • • 000.0 000 • • • 00 000.0000
0 N 00 • • • 000 0.00.0.0 • • 800000 .00.00.0 .00.00.0 .00.0.00 00.000.0 00.00000
00 <b 0 • • • • • 00 .0.0.0.0 00000000 .00.0080 .00800.0 .00 • • 000 00.000.0 00.00000
u •••••••0 .00 • • 0.0 • • • 00000 .000.0.0 .00.00.0 .00.oDoo 000.00.0 000.0000
00000000 000000.0 00000000 O.OoO •• ll • • • • • • • 0 ••••••• 0 ••••••• 0 00 • • • • • 0
0 • • • • 0.0 000000.0 00000000 00000000 0 • • • • • • 0 0 • • • • 0.0 000000.0 00 • • • • • •
N .0.000.0 0000.0.0 00000000 000000.0 .00.0000 .0000.00 000 • • • • 0 00.00.00
0
0 <b .0.000.0 • • • • • 0.0 • • • • • 0.0 • • • • • • • 0 .00.0000 .000.0.'0 00.0.0.0 00.00800
0 U 0 • • • • 0.0 0.00.0.0 00000000 0.0000.0 .0080000 .00000.0 00.0.0.0 00.00.00
000000.0 000000.0 00000000 OOODOOl!n o • • • • • • n 0 • • • • • 00 00000800 000 • • 000
08000080 0 • • • 0080 00000000 0 • • • • • 00 oa • • oo.o 0 • • 00000 00000000 000 • • 000
0
0
N .0000080 • • 00.0.0 00000000 .0.000.0 . 0 . 0 . 0 . 0 800.0000 00.00000 00.00.00
0 <b .00.00.0 .0.0.0.0 00000000 .oo.ooao . 0 • • • 0.0 .00.0000 0.000000 00.00.00
0 u 0 •••••• 0 .00 • • 0.0 00000000 .000.0.0 .00000.0 .00.0000 .0tJooooo 00.00.00
poo.oo.o 0 • • • 00.0 OOOOOOOLJ o • • • • • nn ~ •• ~ •• on • • • • • • • n OOoOooQO 00 • • • • • •
-.J -.J -.J -.J -.J -.J -.J -.J
(f) (f) (f) (f) (f) (f) (f) (f)

1;1
o 0
0
<D
0
0
0
0
0

l
00 0
0
~

0
0
0
~
0
0
~

~ ~

STANDARD MICROSYSTEMS Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applica-
tions; consequently complete information sufficient for constructi.on purposes is not necessarily giv,en. The
CORPORATION information has been carefully checked and is believed to be entirely reliable. However. no responsibility is
assumed for inaccuracies. Furthermore. such information does not convey to the purchaserofthe semiconductor
35M<roJs~~NVT1788
(516]2733100 TWX·5102U61196 devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time to order to improve design and supply the best product possible.

416