Memory Model
C++11 – C++23
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Important Question
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Does the processor executes the
program as you wrote it?
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The Answer
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Short Version
• Usually Not
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Longer Version
• It will run what you have intended but:
• Compilers reorder and change
operations
• CPU’s use threading and OOO
execution
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Compiler Optimisations
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If you were the compiler, what would you do?
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If you were the compiler, what would you do?
• Compiler detects that get_pivot yields the
same value
• It's better to call get_pivot once and call the
value from register again and again
• data[p] has the same value, it will be stored
in a register
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Compiler can do even better
• Modern (X86) CPUs have vectorization
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Compiler can do even better
• If everything can be know in compile time
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Algebraic Simplifications
(v + 1) + 3 ->
v + (1+3) ->
v+4
Strength Reduction
Loop unrolling
• Compiler may unroll your loops
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Loop unrolling
• Compiler may unroll your loops
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Dead Code Removal
• If there is unnecessary code, it will probably
be removed
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Dead Code Removal
• If there is unnecessary code, it will probably
be removed
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inlining
• inlines function calls
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inlining
• inlines function calls
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inlining recursion
• Tail recursion can be inlined
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inlining recursion
• Tail recursion can be inlined
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CPU Optimisations
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INO Execution
Source: https://en.wikipedia.org/wiki/Central_processing_unit
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INO Execution
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INO Execution
• instruction fetch
• if operands available execute it if not fetch them
• The instruction is executed by the functional unit
• The functional unit writers the result back to the
register or memory
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INO vs OOO Execution
Source::
https://www.semanticscholar.org/paper/RISC-V-Reward:-Building-Out-of-Order-Processo
rs-in-Zekany-Tan/f7f6d27f334604c3c85f0b8d21d2a9b4df22a983
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OOO Execution
From F. Yazdanpanah, C.
Alvarez-Martinez, D.
Jimenez-Gonzalez and Y. Etsion,
"Hybrid Dataflow/von-Neumann
Architectures," in IEEE
Transactions on Parallel and
Distributed Systems
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OOO Execution : Dynamic Scheduling
• instruction fetched
• instruction dispatched to instruction queue
• the instruction waits in the queue untils its input
operand are available
• if operands available instruction is allowed to
leave the queue before other instructions
• the instruction is issued to a functional unit
• only if all older instructions have completed the
operation the result is written to register file
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Dynamic Scheduling
• Check for structural hazards
• an instruction can be issued if a functional unit
is available
• an instruction stalls if no appropriate
functional unit available
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Dynamic Scheduling
• Check for data hazards
• an instruction can be executed when its
operands have been calculated or loaded
from memory
• an instruction stalls if operands are not
available
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Dynamic Scheduling
• instruction can be executed out of order if there
is no dependency on previous instructions
• ready instructions can execute before earlier
instructions that are stalled
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Cache $
• Cache can accelerate reads and make writes
longer and more complex
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Reordering and C++
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Reordering Types
• Data dependencies must be honored
• C++ compiler may reorder any memory access
under the as-if rule
• Different processors have different reordering
guaranties
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AS-IF Rule
● Accesses (reads and writes) to volatile objects
occur strictly according to the semantics of the
expressions in which they occur. In particular, they
are not reordered with respect to other volatile
accesses on the same thread.
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AS-IF Rule
● At program termination, data written to files is
exactly as if the program was executed as written
● Prompting text which is sent to interactive devices
will be shown before the program waits for input
● Executing function from external libraries
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AS-IF Rule - Not Always
● programs with undefined behaviour
● copy elision, the compiler may remove calls to
move and copy-constructor and destructors of
temporary objects even if those calls have side
effects
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Multi Threading and Reordering
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Reordering between two threads
Thread 1 Thread 2
flag1 = 1; flag2 = 1;
if (flag2 == 0){ if (flag1 == 0){
critical section} critical section}
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Sequential Consistency
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Sequential Consistency
● Result of any execution is the same as if the
operations of all the processors were executed in
some sequential order
● Operations of each individual processor appear in
the sequence in the order specified by the program
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SQC: Do we Have It?
● SQC is very expensive
● Modern compilers do not offer it (for free)
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What Does C++ and Modern CPU guarantee?
SC-DRF:
● A system guaranteeing DRF-SC must define specific
instructions called synchronizing instructions, which provide a
way to coordinate different processors (equivalently, threads)
● Programs use those instructions to create a “happens before”
relationship between code running on one processor and
code running on another.
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Example:
Thread 1 Thread 2
Foo(Flag)
S(a) S(a)
Bar(Flag) Bar(Flag)
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Pop Quiz: can this happen?
Thread 1 Thread 2 Thread 3 Thread 4
x=1 x=2 y1 = x y3 = x
y2 = x y4 = x
y1=1,y2=2,y3=2,y4=1?
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Pop Quiz: can this happen?
y1=1,y2=2,y3=2,y4=1?
Thread 1 Thread 2 Thread 3 Thread 4
1: x = 1 4: x = 2 2: y1 = x 3: y4 = x
5: y2 = x 6: y3 = x
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Synchronization
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Volatile
● Volatile is not a synchronization tool
● Volatile doesn’t affect threading
● It's not an atomic value
● It doesn’t add barriers
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Volatile: what is it good for?
● Tells the compiler it shouldn’t optimize the
memory reads and writes order.
● Alas the CPU can still reorder
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Volatile: Bad Example
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Volatile: Most uses deprecated with C++20
• Is += a single/atomic instruction? How
about ++?
• How many reads/writes are needed
for compare_exchange? What if it fails
• foo(int volatile n) int volatile foo() are
meaningless.
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Volatile: Most uses deprecated with C++20
• For more information watch JF’s talk about it
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Synchronization cont
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Compiler Code Barriers
Prevent compiler from moving reads or writes
across the barrier
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Compiler Code Barriers
Prevent compiler from moving reads or writes
across the barrier
Thread 1 Thread 2
value = very_long_calc() while (not done){}
asm volatile(“mfence” ::: “memory”) asm volatile(“mfence” ::: “memory”)
done = true //do something
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Locks and Atomics
Most Locks and atomic operation will act like
barriers
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Understanding Memory Barriers /
Memory Ordering
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Acquire Semantics
• property that can only apply to operations
that read from shared memory, whether they
are read-modify-write operations or plain
loads. The operation is then considered
a read-acquire. Acquire semantics prevent
memory reordering of the read-acquire with
any read or write operation that follows it in
program order.
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Acquire Semantics
Read-Acquire
All memory operations
stay below the line
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Release Semantics
• property that can only apply to operations
that write to shared memory, whether they are
read-modify-write operations or plain stores.
The operation is then considered
a write-release. Release semantics prevent
memory reordering of the write-release with
any read or write operation that precedes it in
program order.
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Release Semantics
All memory operations
stay above the line
Write-Release
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Memory Barrier / Acquire Release Order
Read-Acquire
All memory operations
stay between the borders
Write-Release
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Sequential Consistency
• This is the default and the most strict mode. Enforcing
that all operations are seen in a globally consistent
order across all threads, as if they were executing in a
single sequential thread. This means that any read or
write operation that uses this memory order will be
sequenced before or after all other operations in the
program, providing a globally consistent view of
memory.
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Sequential Consistency
SQC
All operations will be in
the same order
SQC
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What's The Difference?
Thread 1 Thread 2 Thread 3 Thread 4
x = sr(1) y = sr(2) y1 = la(x) y3 = la(y)
y2 = la(y) y4 = la(x)
sr = store_release
la = load_acquire
T3: y1 = 1 y2 = 0
T4: y3 = 2 y4 = 0
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What's The Difference?
Thread 1 Thread 2 Thread 3 Thread 4
x = ss(1) y = ss(2) y1 = ls(x) y3 = ls(y)
y2 = ls(y) y4 = ls(x)
ss = store_seq_cst
ls = load_seq_cst
T3: y1 = 1 y2 = 2
T4: y1 = 1 y2 = 2
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Relaxed Semantics
• This semantics offers the weakest guarantees
among memory ordering constraints. There are
no guarantees about the relative order of
memory accesses as observed by different
threads. This means that operations performed
by one thread might not be immediately visible
to other threads, and the order in which
operations appear to occur might not reflect the
actual order in which they were executed.
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Relaxed Semantics
Relaxed
Everything is possible
Relaxed
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Consume Semantics
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Consume Semantics
designed to exploit data dependencies between
threads to provide synchronization guarantees.
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Data Dependency Ordering
● Some CPU have to emit barriers to order between
memory instructions (armv7, risc v)
● Data dependencies make the order defined
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Data Dependency Ordering
● Data dependencies can be on memory and
chained
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Consume Semantics : How does it works
● The compiler exploit the data dependency chains
● Instructions have to carry-a-dependency (lucky it's
defined in the standard)
● to summarize: one evaluation carry-a-dependency if
value of the first is defined in the second evaluation as
an operand
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Example
a = atomic_bool_value{flase},
x=0
Thread 1 Thread 2
x=1
a.sr(true)
z = a.lc()
if (z) y = x
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Good Example
a = atomic_int*_value{null}
Thread 1 Thread 2
x=1
a.sr(&x)
z = a.lc()
if (z) y = *z
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Consume Semantics
Good news consume is almost like acquire, acquire
promises same things and its stronger.
Most compilers do not support consume and will
emit release-acquire
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What may happen here ?
A1.store(4, release)
Y = A2.load(acquire)
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What may happen here ?
Y = A2.load(acquire)
A1.store(4, release)
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Why is it possible ?
A1.store(4, release)
Y = A2.load(acquire)
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What may happen here ?
Y = A2.load(acquire)
A1.store(4, release)
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C++ Concurrency tools
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std::thread
● Cross platform thread class
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thread_local
●storge of the variable is defined by the thread
● helps with data races, each thread has its own copy
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thread_local
● Please don't abuse it
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thread_local
● Please don't abuse it
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std::atomic
● Provides a portable way to perform low level
atomic operations
● No torn reads and no torn writes
● Provides read-acquire, write-release and full
memory barriers
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Atomic Memory Order
● memory_order_relaxed – there are no sync or
ordering constraints, only this operation is
guaranteed to be atomic
● memory_order_acquire
● memory_order_release
● memory_order_seq_cst – this will give us
sequential consistency, and this is the default
mode
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Atomic Memory Fence
Int a = 0
Thread 1 Thread 2
a = 42;
atomic_thread_fence(memory_order_release) atomic_thread_fence(memory_order_acquire)
int r2 = a ? a : -1;
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std::atomic Without a Fence
Int a = 0
std::atomic<int> ready(0)
Thread 1 Thread 2
a = 42; int r1 = ready.load(memory_order_acquire)
ready.store(1, memory_order_release) int r2 = a ? a : -1;
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std::atomic: Default
Int a = 0
std::atomic<int> ready(0)
Thread 1 Thread 2
a = 42; int r1 = ready
ready.store(1)
int r2 = a ? a : -1;
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std::atomic Performance: Loads
● On X86 atomic loads are just loads
(primitive types)
● Can be more expansive and cause locking on
other systems
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std::atomic Performance: Stores
● On X86 atomic stores use xchg, and it is a full
barrier
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std::atomic Spinlock Example
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std::atomic Spinlock Example Cont
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std::atomic Spinlock Example
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std::atomic<std::shared_ptr>
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Atomic Builtins
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Atomic Builtins
●Most Compilers have implementations for
C++11 compatible atomic operations
● GCC and Clang use the __atomic prefix
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Volatile vs Atomics
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Volatile vs Atomics
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X86-64 disassembly
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X86-64 32 bits disassembly
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X86-64 32 bits disassembly
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RISC V-64 disassembly
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RISC V-32 disassembly
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Fence Example
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Relaxed
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Relaxed
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Relaxed
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Relaxed
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Relaxed
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Relaxed surprise
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Acquire
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Acquire
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Acquire No Surprises
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RISC V Disassembly
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RISC V Disassembly
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Other STL Concurrency Features
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std::future and std::promise
● std::future<T> - value for which you may wait
● Std::promise<T> - produces a future
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Futures and Promises
● Can help communication between threads
● Help build task-oriented utilities for executing
work on different threads
● Future and promise are one shoot
operation
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Jthread
● Same as std::thread but is joinable by default
● Jthread is stoppable with std::stop_source
● Provides easier implementation where user don’t
have to think about joins
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Synchronization Tools
● std::mutex, std::conditional_variable
● std::lock_guard – RAII helper for locking
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Synchronization Tools
● std::unique_lock – same as lock guard but
unique and can be deferred.
● std::scoped_lock – takes ownership of multiple
locks at once with RAII with deadlock avoidance
algorithm
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Synchronization Tools
● std::counting_semaphore – semaphore that can
be set to an arbitrary number.
● Std::binary_semaphore – same as
counting_semaphore but it's set to 1.
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Synchronization Tools
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Synchronization Tools : stop_source
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Synchronization Tools : stop_source
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Std::threads : Micro Benchmark
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Synchronization Tools - cont
● Std::latch– threads may block on latch until its
value is zero, latch is one shoot.
● std::barrier– very similar to latch but can be
used multiple times .
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Synchronization Tools – Latch Example
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Synchronization Tools – Latch Example
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Synchronization Tools – Barrier Example
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Synchronization Tools – Barrier Example
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Synchronization Tools
● std::shared_mutex– may be used by couple of
threads or be exclusive.
● std::timed_mutex – same as mutex but has a
claim time out.
● std::shared_timed_mutex – combination of
shared and timed mutexes.
● std::shared_lock – RAII wrapper for timed and
shared mutexes
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Synchronization Tools
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Synchronization Tools
● Static: from C++11 static variables initialization
is magic
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Synchronization Tools
● std::call_once and std::once_flag – help to do
something just once.
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Synchronization Tools
● Std::packaged_task – wraps a callable into a
thread and returns a future
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QUESTIONS
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THANK YOU FOR LISTENING
ALEX DATSKOVSKY
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