Department of Electronics and Communication Engineering

DIGITAL SYSTEM DESIGN USING VERILOG (BEC302)

Module-1
1. Simplify the following using K-map, (On 3 variables and 4 variables)
i. f(w, x, y, z)= Σ(1, 3, 4, 6, 9, 11, 12, 14), and
ii. F(a, b, c, d)=(0, 2, 5, 7, 8, 10, 13, 15).
2. Identify all the prime implicants and essential prime implicants of the following function
using K-map: f(a, b, c, d) = ∑(6,7,9,10,13) + dc (1,4,5,11,15).
3. Find the minimal sum of the following Boolean function using Quine-Mc Clusky method f(a,
b, c, d) = ∑(7,9,12,13,14,15) + dc(4,11).
4. Simplify the following using tabulation method, ∑m(1,2,3,5,9,12,14,15) + Σd(4,8,11).

Module-2
1. With the truth table and neat diagram explain full adder and parallel adder.
2. Explain 4 bit carry look ahead adder with necessary diagram and relevant expression.
3. Design a two-bit magnitude comparator with relevant expressions and truth table.
4. What is a decoder? Explain 3:8 Decoder.
5. Explain 8: 3 encoders with Priority/without priority using truth table and logic circuit.
6. Design
a. 4:16 decoder using 2:4 decoder, and
b. 3:8 decoder using 2:4 decoder.
7. Explain 4:1 MUX realize 16:1 MUX using 4:1 mux.
8. Realize the following function using 4:1 Mux and 8:1 Mux.
F(x,y,z)= ∑m(0,2,3,5)

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9. Write a note on Programmable Logic Devices (PLDs) and Programmable Read Only
Memories (PROM).
10. Realize the following expression using PROM
f1 (x2, x1, x0) = ∑m (0, 1, 2, 5, 7) and f2 (x2, x1, x0)=∑m (1, 2, 4, 6).

Module-3
1. With neat diagrams describe the working of master slave SR flipflop.
2. What is a characteristic equation, write the characteristic equation of SR flipflop, JK flipflop,
D flipflop and T flipflop.
3. Write a note on SISO and SIPO shift register.
4. With a neat diagram write a note on Universal Shift Register.
5. With a neat diagram write a note on binary ripple counter using T-flipflop.
6. Design a mod 11 counter using 4-bit counter.
7. Write a note on
i. Ring Counter, and
ii. Johnson Counter.
8. Design a synchronous counter having the following sequence (000, 010, 011, 110, 101, 001).

Module-4
1. Explain the structure of Verilog module with an example.
2. Why HDL? Write the importance of HDL.
3. Write a note on different logical, relational operators available in Verilog HDL.
4. List the various data types available in Verilog HDL and explain any four of them in brief.
5. Write a Verilog code for 2:1 Mux, 4:1 Mux in dataflow description with active low enable.
6. Explain the signal declaration and assignment statements in HDL.

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Module-5
1. List the various sequential statements in Verilog HDL.
2. Write a Verilog code for 4:1 Mux in behavioral description.
Write behavioral description of a 2:1 Mux with tristate output.
3. Write the behavioral description of positive edge triggered SR / JK flipflop using case
statement.
4. Write a Verilog code for 3-bit binary counter using case statement.
5. Explain if, else if, nested if with example.
6. Explain the various loop statements available in Verilog HDL with example.
7. Write a Verilog behavioral description for calculating factorial of the positive integer.
8. What is structural description? List the importance/facts of structural description
9. Write a Verilog code for ripple carry adder in structural description.

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Additional Questions for Practice

1 Determine the prime implicants of the function using Quine McClusky's method.
Y=f(w, x, y, z)=∏Μ(1, 4, 6, 7, 8, 9, 10, 11, 15)
2 Use a K-map to simplify the following functions:
i. f(A, B, C, D) = A’B’C + AD + BD’ + CD’ + AC’ + A’B’
ii. f(A, B, C, D) = (A+B+C’)(B’+D’)(A’+C)(B+C)
3 Find the Prime implicants for the given function using K-map simplification.
f(w, x, y, z)=∑m(0, 4, 5, 9)+d(1, 7, 13)
4 Place the following equations into proper canonical form.
i) f(A, B, C)=AB+AC+BC
ii) f(A, B, C)= B(A+C) (B+C)
5 Implement the following function using 8:1 mux.
6 Design a two 2-bit comparator and realize using logic gates.
7 Explain with truth table the 8:3 encoder with priority and without priority.
8 Explain the general structure of the PLDs with a block diagram /Implement function using
PLD.
9 Derive the characteristic equations for SR, JK, D, and T flip-flops by obtaining minimal sums.
10 Explain with timing diagram the operation of Master slave JK flip flops.
11 What is a shift register? Explain the basic operations of the shift register with a block
diagram.
12 Design a 3-bit synchronous up counter using JK flip flop.
13 Explain the structure of Verilog module with an example code.
14 What are the different types of operators available in Verilog, explain the logical bitwise
operator with examples.
15 Write Verilog code for a 3-bit carry look ahead adder using data flow description.

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16 Analyze the importance of the initial statement and always statement in Verilog HDL using
examples.
17 Using gates level, write a circuit and Verilog code for 4:1 mux.
18 Explain the different types of looping statements in Verilog with an example.
19 Implement 2:4 decoder using the case statement.

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