Verilog 15 Marks
1. Writean RTL code for the below equation using behavioral modelling style? -- (3 Marks)
Y =! a & (b | c)
2. Find out the bug in the code & the hardware inferred by the following code -- (3 Marks)
modle XYZ (Data out, Data in, clock, reset) ;
input Data in, clock, reset;
Output Data out;
wire [4:0] Data reg;
assign Data out = Data reg [O1
always G (negedge reset Or posedge clock)
begin
if (reset == 1'b0)
Data reg E b0;
else
Data reg {Data in, Data reg[4:1] };
end
endmodule
3. Write asynthesizable Verilog RTL for 4:16
decoder using Verilog tasks. - (3 Marks)
4. What is the difference in the execution
statements:
approach for the following snippets of the display
-(3 Marks)
initial initial
begin begin
i£def TYPE 1 if ($test$plusargs ( "TYPE 1"))
$display (" TYPE 1 message "); $display (" TYPE 1 message ") ;
else else
ifdef TYPE 2 if ($
$display(" TYPE 2 message ") ; test$plusargs ( "TYPE 2") )
endif
$display (" TYPE 2 message ") :
end
endif
endmodule
end
endmodule
AVE
SIL IC O N
S. Draw the waveform for the following code for first four
clock cycles. -- (3 Marks)
module t e s t ( ) ;
reg clk, a;
initial
begin
clk = 0;
£orever
#5 clk = ~clk;
end
always@ (posedge clk)
begin
a = 0;
#5 a <= !a;
end
endnodule
Verilog 15 Marks
1. Predict the output of the following snippet.
-- (3 Marks)
reg I : ] a,b;
integer i;
initial
begin
Smonitor ("nonitor a:th b:h 0t", à, b, $time):
for (i=; i<i; i=i+.)
begin
$strobe ("st.robe a:Bh b:%h %t", a, b, $time);
sdisplay ("isplay a:%h b:h 0t", a, b, $tine):
case (i)
: a 4;
1:b ;
2: begin end // do nothing
3: (a,b) = 9;
endcase
Soisplay ("display a:th b:th 0t", a, b, tine):
end
end
2. Write RTL code to design asequence detector MOORE non-overlapping to detect 10110 with
MSB first. -- (5Marks)
3. Differentiate
between Conditional compiler directive
syntax and examples. &
AAVEr
conditional simulator directive with
--(3 Marks)
4. Explain the difference in the below execution with valid
points: (2 Marks)
A.
initial
begiin
a <= # 0 3'd5:
b <= #20 3dé:
c <= #303'd7;
end
B.
initial
£ork
= #1dE;
b= i;
C=
#7;
join
5. From the below Verilog snippet, display the output and
check if it's a race condition.
module practise; -- (2 Marks)
task tl (input a);
begin
$aisplay("vaiLie f a=",a) :
end
endtask
endmodule
zRAdule top;
practise DUT1{ );
practise DUT2 ( ):
initial
fork
DUT|.ti{');
DUT2.ti(i ' ) ;
join
endmodule
3) 2) Writethe I)Verilog
What The Write Sequence
pulse the Section
type
Verilog l10111Verilog
of width
Hardware isRTL (MSB RTL [1SM): B
of
one code
wil clock frst). code to
be generateto design
synthesized cycle
width. sequence a
one
for minute
the detector
following: pulse
for that
a detccts a
digital Each
clock question
Mealy
of
trequency overlapping
carries
256
Hz.
marks 3
SIL|C 0 N
module hardvare synth (input [7:0Ja, input [2:0] amt, output reg [7:0] y );
always (@*
begin
case(am)
3'd0: y= a,
3'di: y= (a[0],a[7:1];;
3'd2: y = {a[ l:0],a[7:2]};
3'd3: y = (a[2:0],a[7:3];;
3'd4: y = (a[3:0],a{7:4|};
3'dS: y= (a[4:0],a[7:5]};
3'd6: y ={a[5:0],a<7:6]} ;
default :y= (a[6:0], a[7]}:
endcase
end
endmodule
4) Display the precise batch mode output for the following:
module strobe;
reg a ;
initial
begin
Smonitor( Stime, "Value of a monitored - od",a);
$strobe($time,"Value of a strobed= %d",a):
a = 0;
a <= 1:
Sdisplay(Stime,"Valuc of adisplayed = %d",a);
#1;
a = 1'bx;
end
endmodule
& explain why?
5) Find out which of the code mentioned below is a good portable code
a) always(@s b) always@(s or r)
begin begin
if(s)
if(s) q<= 1;
q <= 1;
end
else if(r)
q<= 0:
end
always@r
begin
if(r)
q<=0;
cnd
