Digital Blocks
Semiconductor IP
DB8279 Programmable Keyboard / Display Interface
General Description
The Digital Blocks DB8279 Programmable Keyboard / Display Interface core is a full function equivalent to the Intel 8279 / Mitsubishi 8279 / NEC uPD8279 devices. The DB8279 simultaneously and independently interface a keyboard and display to a microprocessor. The keyboard section provides a scanned interface to a 64-contact key matrix keyboard. The display section contains a 16x8 display RAM which refreshes a numeric or alphanumeric segment display.
Features
The DB8279 contains the following features: Simultaneous and independent scanning of a keyboard and refresh of a display, significantly offloading these functions from the microprocessor. Keyboard section: o 8-character Keyboard FIFO o 2-Key Lockout or N-key Rollover with Contact Debounce o Interrupt Output on Key Entry o Programmable Keyboard Scan & Debounce rates Display Section: o Dual 8- or 16-Numeric Display o Single 16-Character Display o Right or Left Entry 16-Byte Display RAM with address autoincrement o Programmable display refresh rate Available in VHDL, Verilog, or FPGA-Specific Netlist
DB8279-DS-V1.8
2/20/2010
Digital Blocks, Inc.
DB8279 Programmable Keyboard / Display Interface
Block Diagram
CLK RESET DB_IN[7:0] DB_OUT[7:0] RDN WRN CSN A0 IRQ
Data Buffers
I/O Control
FIFO/SENSOR RAM Status
Internal Data Bus
Display Address Register
16 x 8 Display RAM
Control and Timing Registers
8x8 FIFO/SENSOR RAM
Keyboard Debounce and Control
Display Registers
Timing and Control
Scan Counter
Return
OUTA[3:0] OUTB[3:0]
Figure 1: DB8279 Programmable Keyboard / Display Block Diagram
8 SHIFT BDN SL[3:0] RL[7:0] CNTLSTB
DB8279-DS-V1.8
2/20/2010
Digital Blocks, Inc.
DB8279 Programmable Keyboard / Display Interface
Pin Description
Name CLK RESET CSN A0 RDN WRN RL[7:0] SHIFT CNTSTB DB_IN[7:0] DB_OUT[7:0] PDBTRI IRQ SL[3:0] OUTA[3:0] OUTB[3:0] BDN Type In In In In In In In In In In Out Out Out Out Out Out Out Polarity Rising High Low Low Low Low Low Description Clock Reset Chip Select Buffer Address Input/Output Read Input/Output Write Return Lines Shift Input Status Control/Strobed Input Mode Data Bus (input side) Data Bus (output side) Tri-State signal for DB_OUT Interrupt Request Scan Lines Outputs A for 16x4 display refresh registers Outputs B for 16x4 display refresh registers Blank Display
Table 1: DB8279 Programmable Keyboard / Display Interface I/O Pin Description
Verification Methods
The DB8279 Programmable Keyboard / Display Interface cores function was verified by means of a proprietary hardware modeler. The same stimulus was applied to a hardware model that contained the original Intel 8279 chip, and the results compared with the cores simulation outputs. The DB8279 has been verified in silicon via customer designs.
Deliverables
The DB8279 Programmable Keyboard / Display Interface is available in VHDL or Verilog source or an FPGA-specific netlist. The IP Core comes with a comprehensive test suite, synthesis scripts, data sheet, and user manual. The test suite includes a testbench, test vectors and expected results.
DB8279-DS-V1.8
2/20/2010
Digital Blocks, Inc.
DB8279 Programmable Keyboard / Display Interface
Ordering Information
Please contact Digital Blocks for additional technical, pricing, and support information. Digital Blocks, Inc. PO Box 192 587 Rock Rd Glen Rock, NJ 07452 USA Phone: +1-201-251-1281 eFax: +1-702-552-1905 [email protected]
Copyright Digital Blocks, Inc. 1999-2010, ALL RIGHTS RESERVED
DB8279-DS-V1.8
2/20/2010
