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Assignment Sequential Circuit 2023

The document outlines various problems related to designing sequential circuits using different types of flip-flops, including J K, D, and T flip-flops. It includes tasks such as generating 2's complement, creating binary counters, designing finite-state machines, and implementing shift registers. Each problem specifies the requirements and conditions for the circuit designs to be completed.

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Vineesh K Vinod
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14 views2 pages

Assignment Sequential Circuit 2023

The document outlines various problems related to designing sequential circuits using different types of flip-flops, including J K, D, and T flip-flops. It includes tasks such as generating 2's complement, creating binary counters, designing finite-state machines, and implementing shift registers. Each problem specifies the requirements and conditions for the circuit designs to be completed.

Uploaded by

Vineesh K Vinod
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Sequential Circuit Tutorial Problems

AV221- Digital Elelctronics and VLSI Design

1. Design a sequential circuit using J K Flip Flop for generating 2’s complement of serial data.
2. Design a binary counter that will convert a 64 Khz pulse signal into a 2KHz
square wave. Use D flip flop

3. Design a sequential circuit that generates one pulse when an input goes from low to high
and when the input goes from high to low the circuit generate two pulses as shown below.
The input signal need to be synchronized with the clock. Use T FLIP FLOP for the design. In
between the double pulse if any transition occurs in the input neglect it .

4. A finite-state machine has one input (w) and one output (z). The input ‘w’ is a
serial input synchronized to a clock The state machine is part of a
communication system that is using the following rules for transmission of
data through the input w: If a 1 occurs in the input stream, then there should
be an odd numbers of 1’s; if a 0 occurs, then there should be an even numbers
of 0’s. If it is not so then it has to report an error signal showing in the output
ie z=1.

W 111000100110000
Z 000000100001000

Design the circuit using T flip flop

5. Design sequential circuits with D Flip-Flops to implement the following state


diagram.

6. You only have D-Flip Flops with asynchronous preset and reset.
(1) Design 2-Bit shift register with synchronous parallel load using D FlipFlops.
(2). Design 2-Bit shift register with asynchronous parallel load using D FlipFlops.

7. A sequential circuit shown below has two JK Flip-Flops, one input X, and one

output Y. Derive the state table and state diagram of the circuit.
8. Design MOD 6 counter using T flipflop? If the clock frequency of the counter
is
10MHZ . Find the output frequencies generated by the flipflops.

9. Consider the Block Diagram

The shift register is used to convert the parallel data to serial data. The bit b7 is set 0 when the
parallel input is given. Before transmitting the signal b0 to b7 a parity bit (odd) is added in the bit
position b7. A FSM need to be designed to generate the parity bit and augment with the serial
output w. A 3 bit counter is used to count from 0 to 7 and when it reaches 7 the Sel line becomes
high to transmit the generated parity bit. Design the FSM using JK flip flop

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