Y.V.
SANTHOSH MS-2011 VEDAIIT
PREPARATION TILL NOW
Efficient timing closure with a transistor level
design flow
At physical design level the evolution of automation was remained at the standard cell approach, where the layout of the cells are designed and included in a cell library. So, the design of the cell layout is not really automated. A cell library is also limited to small number of logic combinations. This limitation doesn't allow reaching an optimization of the circuit at the physical design level.
Efficient Physical Design Methodology for Reducing Test Power Dissipation of Scan-Based Designs
Scan-based test methodology is used to resolve the sequential-test problem but suffers from high power dissipation. In this paper, we propose a scheme to prevent transitions of scan chain from reflecting into the circuit line. It not only can save 23% power consumption without performance loss,but also can be easily implemented with popular industrial design tools.