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Physical Design

The document discusses two topics. The first discusses improving physical design automation by designing cell layouts automatically rather than manually pre-designing cells in a library. This allows for more optimization at the physical design level. The second discusses a scheme to reduce power dissipation in scan-based circuit testing by preventing transitions in scan chains from propagating to circuit lines, saving 23% power without performance loss.

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Marri Rohit
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0% found this document useful (0 votes)
144 views4 pages

Physical Design

The document discusses two topics. The first discusses improving physical design automation by designing cell layouts automatically rather than manually pre-designing cells in a library. This allows for more optimization at the physical design level. The second discusses a scheme to reduce power dissipation in scan-based circuit testing by preventing transitions in scan chains from propagating to circuit lines, saving 23% power without performance loss.

Uploaded by

Marri Rohit
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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Y.V.

SANTHOSH MS-2011 VEDAIIT

PREPARATION TILL NOW

Efficient timing closure with a transistor level

design flow
At physical design level the evolution of automation was remained at the standard cell approach, where the layout of the cells are designed and included in a cell library. So, the design of the cell layout is not really automated. A cell library is also limited to small number of logic combinations. This limitation doesn't allow reaching an optimization of the circuit at the physical design level.

Efficient Physical Design Methodology for Reducing Test Power Dissipation of Scan-Based Designs

Scan-based test methodology is used to resolve the sequential-test problem but suffers from high power dissipation. In this paper, we propose a scheme to prevent transitions of scan chain from reflecting into the circuit line. It not only can save 23% power consumption without performance loss,but also can be easily implemented with popular industrial design tools.

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