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Adaptive Body Bias For Reducing Process Variations

This document discusses using adaptive body biasing to reduce process variations in integrated circuits. It describes how applying forward or reverse body bias can be used to increase or decrease transistor threshold voltages, allowing compensation for slow or leaky dies. An adaptive body bias circuit is proposed that uses feedback to determine the optimal body bias voltages needed to meet timing and power constraints across dies with variation. The circuit aims to maximize yield by reducing frequency variations to 1% from the original 4.1% while improving the number of dies that meet leakage constraints.

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Pardha Saradhi Damarla
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136 views24 pages

Adaptive Body Bias For Reducing Process Variations

This document discusses using adaptive body biasing to reduce process variations in integrated circuits. It describes how applying forward or reverse body bias can be used to increase or decrease transistor threshold voltages, allowing compensation for slow or leaky dies. An adaptive body bias circuit is proposed that uses feedback to determine the optimal body bias voltages needed to meet timing and power constraints across dies with variation. The circuit aims to maximize yield by reducing frequency variations to 1% from the original 4.1% while improving the number of dies that meet leakage constraints.

Uploaded by

Pardha Saradhi Damarla
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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adaptive body bias for reducing process variations

nuno alves 19 / october / 2006

background goal of processor design: achieve maximum operating frequency meet power density constraint process variations create differences: across a single die across multiple wafers and lots

differences in transistors ? so?

some dies cannot be accepted because:


low frequency high power consumption

dies
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solving leakage problem leakage can be controlled to some extent using body bias. remember: non-zero body-to-source bias can modulate the threshold voltage of a transistors

reverse body bias (rbb) we can use rbb to reduce leakage power in standby mode by: raising the voltage of the pMOS n-wells with respect to vdd or lowering the voltage of substrate relative to gnd

forward body bias (fbb)


use fbb to increase operating frequency in active mode

the good Vt by the lowering the source-body potential barrier

the bad
increase in sub-threshold and substrate-to-source leakage

lower Vt = higher on current

slows down the discharge of nodes

hence higher performance

ideally Vt should be lowered for slow dies raised for leaky dies accomplished by an adaptive body bias

testchip
21 subsites

each subsite contains: an abb generator control circuit

how it works? pt 1
slows things down compare critical path with target clock period the desired operating frequency is applied externally

how it works? pt 2

output of first ff is sampled by second ff

this allows sufficient time for the body bias to stabilize

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how it works? pt 3

PD used to clock a counter

counter whose value represents the body bias to apply

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how it works? pt 4

converting digital code to an analogical body voltage

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how it works? pt 5

the output voltage, which biases the the pMOS transistors is a function of VREF VCCA

output voltage

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how it works? pt 6

setting the bias by modifying: VREF VCCA and

setting a counter control bit

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operation pt 1
initially frequency is lower than the target one

body voltage reduces, forward biasing the pMOS transistor & increasing frequency
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operation pt 2
frequency has been matched

phase detector changes to a permanent 1

the counter is disabled, maintaining the body voltage


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operation pt 3
once optimal voltages are determined, they can be programmed in the chip or supplies externally

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simple adaptive body bias pt 1


optimum bias voltages are determined through measurements

example: 1. a microprocessor with many circuit blocks. 2. find out the frequency of a critical path 3. a central body bias determines the body bias to apply to achieve a desired frequency. 4. apply this bias everywhere 2% total die area overhead

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simple adaptive body bias pt 2


optimum bias is determined by applying a target clock frequency

highest possible operating frequency for the die under the given power constraint.

maximum clock frequency for this maximum frequency nMOS body bias is applied from outside pMOS body bias comes from on-chip control circuitry
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simple adaptive body bias pt 3

pick target frequency

manually adjust nMOS body bias pMOS body bias automatically adjusts

repeat until we find the best combination of lowest leakage with target frequency

determine leakage power

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effects of simple body bias pt1


NBB = no body bias

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effects of simple body bias pt2

conclusion 1: when no body bias, only 50% dies are acceptable

mostly in the low frequency bin

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effects of simple body bias pt3

conclusion 2: frequency variation was reduced to 1% from 4.1% more accepted dies (specially in the high frequency range)

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effects of simple body bias pt4


conclusion 3: many dies fail to meet the leakage constraint due to the fact that a single circuit block is used to determine the body bias for all circuit and there are always intra-die variations.

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