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Faults in Vlsi

- Integrated circuits often contain defects when manufactured, resulting in low die yields of 20-50% for complex chips - ICs must be rigorously tested to screen out faulty parts before use, but exhaustively testing all input combinations quickly becomes infeasible due to the extremely large number of combinations, so tests cover only about 25% of combinations - The VLSI design process involves determining requirements, designing the chip, verifying the design works as intended through simulation, developing tests, manufacturing, and testing produced chips before sending to customers

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200 views

Faults in Vlsi

- Integrated circuits often contain defects when manufactured, resulting in low die yields of 20-50% for complex chips - ICs must be rigorously tested to screen out faulty parts before use, but exhaustively testing all input combinations quickly becomes infeasible due to the extremely large number of combinations, so tests cover only about 25% of combinations - The VLSI design process involves determining requirements, designing the chip, verifying the design works as intended through simulation, developing tests, manufacturing, and testing produced chips before sending to customers

Uploaded by

AmarPreet Nagra
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Introduction

Many integrated circuits (ICs) contain fabrication defects upon manufacture Die yields may only be 20-50% for high end circuits ICs must be carefully tested to screen out faulty parts before integration in systems

Example
Need 23 = 8 inputs to exhaustively test a 3 input AND gate. Need 2N inputs to exhaustively test an N-input circuit Many ICs have > 100pins 2100 = 1.27 X 1030 Applying 1030 tests in 109 tests per Sec (1GHz !) will require 1021 Sec i.e. 400 billion centuries Only a few input combinations can be applied in practice 25% approx

VLSI Realization Process


Customers need Determine requirements Write specifications Design synthesis and Verification Test development Fabrication

Manufacturing test
Chips to customer

Verification vs Test
Verification
Verifies correctness of design. Performed by simulation, hardware emulation, or formal methods.

Test
Verifies correctness of manufactured hardware. Two-part process: 1. Test generation: software process executed once during design 2. Test application: electrical tests applied to hardware Test application performed on every manufactured device. Responsible for quality of devices.

Performed once prior to manufacturing. Responsible for quality of design.

Faults, Errors and Failures


Fault(Defect): A physical defect within a circuit or a system
May or may not cause a system failure

Error: Manifestation of a fault that results in incorrect circuit (system) outputs or states
Caused by faults

Failure: Deviation of a circuit or system from its specified behavior


Fails to do what it should do Caused by an error
Defect ---> Error ---> Failure

Faults: Electrical Effects:


Shorts Opens Transistor Stuck-On/Open Resistive Shorts and Opens Change in Threshold Voltages

Logic Effects:
Logic Stuck-At-0/1 Slower Transition (Delay Faults) AND-Bridging, OR-Bridging

Three properties define a single stuck-at fault


Only one line is faulty The faulty line is permanently set to 0 or 1 The fault can be at an input or output of a gate

Single Stuck-at Fault

Test Generation

0 0

0/1
s-a-1 D

Cannot detect the fault

1
F

B 1

0/1 1 0E Fault detected

1
C

Controllability for a digital circuit is defined as the difficulty or efforts of setting a particular logic signal to a 0 or a 1. Observability for a digital circuit is defined as the difficulty or efforts of observing the state of a logic signal. These measures are important for circuit testing, because while there are methods of observing the internal signals of a circuit, they are prohibitively expensive.

Sandia Controllability/Observability Analysis Program, Called as SCOAP consists of six numerical measures for each signal (l) in the circuit:

Line = l

The three combinational measures are related to the number of signals that may be manipulated to control or observe l. The three sequential measures are related to the number of time-frames (or clock cycles) needed to control or observe.
The controllability range between 1 and infinity. The observability lie between 0 and infinity.

Find Output Controllability of the following circuits


A D B

G1

F Y
G4

A
G2

H
G5

B Z C
G3

Assume that controllability of all inputs and observability of all outputs is 1

G1

F Y
G4

A
G2

H
G5

B Z

Controllabilities CC1(F)=CC1(A)+CC1(B)+CC1( C)+1=4 CC0(F)=min{CC0(A),CC0(B),CC0( C)}+1=2 CC1(H)=min{CC0(A),CC0(B)}+1=2 CC0(H)=CC1(A)+CC1(B)+1=3 CC1(G)=CC0( C)+1=2 CC0(G)=CC1( C)+1=2 CC1(Y)=min{CC1(F),CC1(H)}+1=3 CC0(Y)=CC0(F)+CC0(H)+1=6 CC1(Z)=min{CC0(H),CC0(G)}+1=3 CC0(Z)=CC1(H)+CC1(G)+1=5

G3

Comb. Controllability
Circled numbers give level number. (CC0, CC1)

Controllability Through Level 2

Final Combinational Controllability

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