Very High-Speed Integrated Circuits
Hardware Description Language
( VHDL )
VHDL Syntax 1
Outline
What is VHDL
VHDL Syntax
VHDL Program Structure
Entity
Architecture
Concurrent and Sequential Statements
VHDL Design Examples
2-to-1 MUX
3-to-8-line Decoder
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What is VHDL
VHDL: Very High Speed Integrated Circuits
Hardware Description Language
Originally developed as a standard mean to document complex
circuits
Later for ASIC design to Printed Circuit Board (PCB) system
Become IEEE-Standard in mid-1986 and a
new standard in 1993
Similar syntax, keywords to C-language
But VHDL IS NOT a programming language
What is VHDL
VHDL allows design re-use by taking deviceindependent VHDL codes as component
High portability:
Same code can be implemented on different logic devices
General VHDL Syntax
Statements termination: ;
List delimiter: ,
Signal assignment: <=
Signal comparsion:
= to compare if they are equal
/= to compare if they are different
Single line comments: --
General VHDL Syntax
User defined names:
Letters, numbers, underscores(_)
MUST start with a letter
Case insensitive, but please follow naming
convention:
VHDL keywords are written in lower case letters
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User defined identifiers are written in upper case letters
VHDL Program Structure
VHDL program structure can be divided into 3 parts:
Library: Collection of complied design units
You should always include IEEE.std_logic.1164.all
Entity: Interface (I/O ports list)
Architecture: Concurrent description, sequential description
Entity
Entity
Entity is the I/O port specification of a module
I/O directions include:
IN, OUT, INOUT (not preferred)
Data types:
std_logic, std_logic_vector, bit, integer
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Entity Port Modes
Port
modes
IN signals that are only read in the architecture
OUT signals that are generated by the architecture
INOUT bidirectional ports
Architecture
Architecture
The behaviour and function of an entity
Many different ways to describe the same design
For example:
Concurrent / dataflow
Sequential
Structural (Will be covered in next tutorial)
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Architecture Example 1
A dataflow description:
Concurrent
statement
Concurrent statements:
Order of the statements is not important
All statements have effects simultaneously
Example:
Boolean equations
With-select-when statements
When-else statements
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Architecture Example 2
A sequential description:
Concurrent
statement
The set of statements that make up a process
constitutes a concurrent statement
Remember:
Electronic systems are concurrent!
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Example of Combinational Digital
Design
2 examples of synthesizable VHDL code will
be discussed:
2-to-1 MUX
3-to-8-line Decoder
For each example:
Observe different styles to describe the behaviours of the device
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2-to-1 MUX
When S = 0
Y=A
When S = 1
Y=B
All input A & B, output Y are 8-bit wide
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2-to-1 MUX
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2-to-1 MUX
LIBRARY statement is used to reference a group of
previously defined VHDL design units or packages
USE statement specifies what entities or packages to
use in this libray
STD_LOGIC_1164 package defines a multi-valued
logic system which will be used as data types for the
signals
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2-to-1 MUX
Signal types:
Std_logic (single bit), std_logic_vector (buses)
std_logic_vector(7 downto 0) descending range
std_logic_vector(0 to 7) ascending range
Difference between ascending and descending range:
Ascending: y(0) [MSB] . y(7) [LSB]
Descending: y(7) [MSB] . y(0) [LSB]
If y <= 11110000
For ascending y(0) = 1, for descending y(7) = 1
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2-to-1 MUX
Single bit assignment:
Y(0) <= 1, use single quotes
Bus assignment:
Y <= 11110000, use double quotes
AVOID declaring buses with different direction in the
same entity
The when else statement is a conditional signal
assignment statement (concurrent)
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Sequential Statement
The process block itself is considered as a single
concurrent statement
Only sequential VHDL statements are allowed within
a process block
Sequential statements:
if else
case
Sensitivity list:
The list of signals after the process block
Any event / change of these signals will cause the process block to be
evaluated
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2-to-1 MUX
Another Architecture Using Process
When using process, common error is forget to
assign a default value to output
If the output is not assigned any value
Synthesizer will assume output must retain current value
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3-to-8-line Decoder
Input:
Binary number D2D1D0
Output:
The output bit corresponds to the input binary number
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3-to-8-line Decoder
Entity:
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3-to-8-line Decoder
Architecture 1
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3-to-8-line Decoder
Architecture 2
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Summary
3 parts of VHDL program:
library, entity, architecture
Concurrent statements
Signal / bus assignment: Z <= A and B;
When else
Sequential statements (only used in process):
Signal / bus assignment: Z <= A and B;
if then else
case when
Single bits and buses
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VHDL Model Template
library library_name;
use library_name.package_name.all;
entity model_name is
port
(
list of inputs and outputs
);
end model_name;
architecture architecture_name of model_name is
begin
...
VHDL concurrent statments
...
end architecture_name;
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Reference
Useful links:
www.gmvhdl.com/VHDL.html
www.vhdl-online.de/tutorial/
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