UNIT - I

The 8085 Microprocessor

Prepared By,
Mr.R-THANDAIAH PRABU M.E.,
Lecturer - ECE
[email protected]

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The 8085 and Its Busses

The 8085 is an 8-bit general purpose microprocessor that can

address 216 =64K Byte of memory.
It has 40 pins and uses +5V for power. It can run at a maximum
frequency of 3 MHz.
The pins on the chip can be grouped into 6 groups:
Address Bus.
Data Bus.
Control and Status Signals.
Power supply and frequency.
Externally Initiated Signals.
Serial I/O ports.
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Intel 8085 Pin Configuration

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Functional Blocks

Registers
ALU
Instruction Decoder
Address Buffer
Address/Data Buffer

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Increment/ Decrement
Address Latch
Interrupt Control
Serial I/O Control
Timing and control
circuitry

Registers
General purpose
Registers
Temporary Registers
Special Purpose
Register
16 Bit Registers

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The Flags register

AC

CY

There is also the flags register whose bits are affected by the arithmetic & logic
operations.
S-sign flag
The sign flag is set if bit D7 of the accumulator is set after an arithmetic or
logic operation.
0- + Ve
1- -Ve
Z-zero flag
Set if the result of the ALU operation is 0. Otherwise is reset. This flag is
affected by operations on the accumulator as well as other registers. (DCR B).
AC-Auxiliary Carry
This flag is set when a carry is generated from bit D3 and passed to D4 . This
flag is used only internally for BCD operations.
P-Parity flag
After an ALU operation if the result has an even no of 1s the p-flag is set.
Otherwise it is cleared. So, the flag can be used to indicate even parity.
CY-carry flag
CY = carry is set when result generates a carry. Also a borrow flag.

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PROGRAM COUNTER (PC) AND STACK

POINTER (SP)
These are two 16-bit registers used to hold memory
addresses.
PC:
The function of the PC is to point to the memory address from
which the next byte is to be fetched.
When a byte (machine code) is being fetched, the program counter
is incremented by one to point to the next memory location.

SP:
It points to a memory location in R/W memory, called the stack.
The beginning of the stack is defined by loading a 16-bit address in
the stack pointer.
The PC will automatically update when calling to /returning from
Subroutines.

The ALU
In addition to the arithmetic & logic circuits, the ALU
includes the accumulator, which is part of every
arithmetic & logic operation.
Also, the ALU includes a temporary register used for
holding data temporarily during the execution of the
operation. This temporary register is not accessible by
the programmer.

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The Address and Data Busses

The address bus has 8 signal lines A8 A15 which are

unidirectional.
The other 8 address bits are multiplexed (time shared) with the 8
data bits.
So, the bits AD0 AD7 are bi-directional and serve as A0
A7 and D0 D7 at the same time.
During the execution of the instruction, these lines carry
the address bits during the early part, then during the
late parts of the execution, they carry the 8 data bits.
In order to separate the address from the data, we can use a
latch to save the value before the function of the bits
changes.
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INCREMENT/ DECREMENT ADDRESS LATCH

Interrupt Control:
Fetch, Decode & execute
RST 5.5, RST 6.5, RST 7.5, TRAP, & INTR
Serial I/O Control
SOD & SID
Timing and Control Circuitry
Its control fetching, decoding, execution

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Frequency Control Signals

There are 3 important pins in the frequency control group.

X0 and X1 are the inputs from the crystal or clock generating
circuit.
The frequency is internally divided by 2.
So, to run the microprocessor at 3 MHz, a clock
running at 6 MHz should be connected to the X0 and
X1 pins.
CLK (OUT): An output clock pin to drive the clock of the rest
of the system.

We will discuss the rest of the control signals as we get to them.

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The Control and Status Signals

There are 4 main control and status signals. These are:
ALE: Address Latch Enable. This signal is a pulse that
become 1 when the AD0 AD7 lines have an address on
them. It becomes 0 after that. This signal can be used to
enable a latch to save the address bits from the AD lines.
RD: Read. Active low indicates that the data must be read
from the selected memory location or I/O port via data bus.
WR: Write. Active low indicates that the data must be written
into the selected memory location or I/O port via data bus..
IO/M: This signal specifies whether the operation is a memory
operation (IO/M=0) or an I/O operation (IO/M=1).
S1 and S0 : Status signals to specify the kind of operation
being performed .Usually un-used in small systems.

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ADDRESSING MODES
IMMEDIATE
MVI A,05(H)
LXI H,0050(H)
DIRECT
LDA 0208(H)
REGISTER
MOV B,C ADD B
REGISTER INDIRECT
LDAX B
INHERENT
HLT
STC(SET CARRY FLAG)

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NOTATIONS

MEANING

Memory location pointed by HL reg pair

8- bit register

rp

16-bit register

rs

Source register

rd

Destination register

addr

16-bit address

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Data Transfer Group

MVI r, data (8- Bit)

MVI M, data (8- Bit)
MOV rd, rs
MOV M, rs
MOV rd, M
LXI rp, data (16 bit)
STA addr
LDA addr
SHLD addr
LHLD addr
STAX addr
LDAX rp
XCHG

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MOV Rd,Rs
MVI R,8bit
LXI Rp,16bit
MOV R,M
MOV M,R
LDA 16 bit
STA 16 bit
LDAx Rp
STAX Rp

MOV B,C
MVI A,05H
LXI B,2050
MOV D,M
MOV M,E
LDA 8005H
STA 8006H
LDAx B
STAX D
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ARITHEMATIC GROUP

ADD r
ADD M
ADI data (8)
ADC r
ADC M
ACI data (8)
DAD rp

SUB r
SUB M
SUI data
SBB r
SBB M
SBI data
DAA
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INR r
INR M
INX rp
DCR r
DCR M
DCX rp

ADD R
ADI 8bit
SUB R
SUI 8bit
INR R
DCR R
INR M
DCR M
INX Rp
DCX Rp

ADD B
ADI 59H
SUB C
SUI 37H
INR D
DCR B
INR M
DCRB M
INX B
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LOGIC GROUP

ANA r
ANA M
ANI data
XRA r
XRA M
XRI data
ORA r
ORA M
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ORI data
CMP r
CMP M
CPI data
STC
CMC
CMA

ANA R/M
ANI 8bit
ORA R/M
ORI 8bit
XRA R/M
XRI 8bit
RLC
RAL
RRC
RAR
CMP R/M

ANA D
ORA C
XRA D

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BRANCH GROUP
JUMP
INSTRUCTION
CALL and
RETURN
INSTRUCTION
RESTART
INSTRUCTION

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JMP 16bit Address

JZ 16bit Address
JNZ 16bit Address
JC 16bit Address
JNC 16bit Address

HLT
NOP

Stop processing and wait

Dont perform anything - delay

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STACK OPERATION I/O &

CONTROL GROUP
PUSH
POP
RESTART
RST n

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INSTRUCTION FORMATS
1 BYTE INSTRUCTION

MOV A,B --- 78H

2 BYTE INSTRUCTION

MVI B, 02 --- 06H 02

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3 BYTE INSTRUCTION

JMP 6200H --C3H 00 62

INSTRUCTION SET

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INSTUCTION SET

MOVEMENT
INSTUCTIONS

GROUP-0
DATA
TRANSFER

MVI,INR,DCR,LDA,
STA,RAR,CMC,
CMA,STC,DAA,
DAD,LDAX,SHLD,
INX,RIM ETC.,

GROUP 1
DATA
TRANSFER

MOV

MODIFICATION
INSTUCTIONS

GROUP 2
ARITHEMATIC
& LOGIC

AND,ADD,
OR,XOR
etc.,

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CONTROL
INSTRUCTIONS

GROUP -3A
BRANCH

JNZ,JNC,JC,
JZ etc.,
PROGRAM
CONTROL

GROUP 3B I/O &

MACHINE
CONTROL

HLT,ENABLE,
DISABLE,
INTR
PROCESS
CONTROL

BYTE ORGANIZATION
GROUP - 0
0

I0

I0

I0

B0

B0

B0

GROUP - 1
0

GROUP - 2
1

A1

A1

A1

GROUP - 3
1

Cb

Cb
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Cb

CODE FOR RECEIVING AND SENDING

REGISTERS/PAIRS
RESSISTERS

AADDRESS CODE

RESSISTERS

ADDRESS CODE

000

BC

00

001

010

DE

01

011

100

HL

10

101

110

SP

11

111

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INFORMATION OPERATIONS (I0 I0 I0)

ADDRESS

OPERATION

I0

I0

I0

NOT USED

IMMETIATE OPERATION REGISTER PAIR

LOAD / STORE

INCREMENT/ DECREMENT REGISTER PAIR

INCREMENT SINGLE REGISTER

DECREMENT SINGLE REGISTER

IMMETIATE OPERATION ON SINGLE REGISTER

REGISTER SHIFTING

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ARITHEMATIC AND LOGICAL OPERATIONS (A1 A1 A1)

ADDRESS

OPERATION

A1

A1

A1

ADD

ADD WITH CARRY (ADC)

SUBTRACT (SUB)

SUBTRACT WITH BORROW (SBB)

LOGICAL AND

EXCLUSIVE OR (X-OR)

LOGICAL OR (OR)

COMPARE

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CONDITIONS OF BRANCH ( Cb Cb Cb)

ADDRESS

OPERATION

Cb

Cb

Cb

IF NOT ZERO (JNZ)

IF ZERO (JZ)

IF NO CARRY(JNC)

IF CARRY (JC)

IF ODD PARITY (JPO)

IF EVEN PARITY (JPE)

WAS IT POSITIVE (JP)

WAS IT NEGATIVE (JM)

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BRANCH OPERATIONS (B0 B0 B0)

ADDRESS

OPERATION

B0

B0

B0

CONDITIONAL RETURN

SIMPLE RETURN

CONDITIONAL JUMP

UNCONDITIONAL JUMP

CONDITIONAL CALL

SIMPLE CALL

SPECIAL A/L OPERATIONS

SPECIAL UNCONDITIONAL JUMPS

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MVI B, BYTE
0

0
0

R
0

I0

I0

I0

MOV B,C
0

ADD B
1

A1

A1

A1

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Static RAM

Dynamic RAM

Static RAM contains less memory cells Dynamic RAM contains more memory
per unit area
cells as compare to static RAM per unit
area
It has less access time, hence faster
memories

Its access time is greater than static

RAMs

Static RAM consists of number of flipflops. Each flip-flop stores one bit

Dynamic RAM stores the data as a

charge on the capacitor. It consists of
MOSFET and the capacitor for each
cell

Refreshing circuitry is not required

Refreshing circuitry is required to

maintain the charge on the capacitor
after every few milliseconds

Cost is more

Cost is less

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MACHINE CYCLES AND THEIR

TIMING OF 8085:
Timing Diagram is a graphical representation. It represents the execution time taken
by each instruction in a graphical format. The execution time is represented in Tstates.
Instruction Cycle:
The time required to execute an instruction is called instruction cycle.
Machine Cycle:
The time required to access the memory or input/output devices is called machine
cycle.
T-State:
The machine cycle and instruction cycle takes multiple clock periods.
A portion of an operation carried out in one system clock period is called as T-state.

 Clock Signal
The 8085 divides the clock frequency provided at x1 and x2 inputs
by 2 which is called operating frequency.
Rise time and fall time

T-State
1 Clock cycle

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 Single Signal
Single signal status is represented by a line. It may have status either
logic 0 or logic 1 or tri-state

Logic 1
Logic 0

Tri state

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 Group of signals
Group of signals is also called a bus.
Eg: Address bus, data bus

Valid state
State changes

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Tri state

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Instruction cycle

Machine cycle1

Machine cycle 2

T State 1 T State 2 T State 3

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Machine cycle 5

T State 6

The 8085 microprocessor has 5 basic machine

cycles. They are

1.Opcode fetch cycle (4T)

2.Memory write cycle (3 T)
3.I/O read cycle (3 T)
4.Memory read cycle (3 T)
5.I/O write cycle (3 T)

 Each instruction of the 8085 processor consists of one to five

machine cycles, i.e., when the 8085 processor executes an
instruction, it will execute some of the machine cycles in a
specific order.
The processor takes a definite time to execute the machine cycles.
The time taken by the processor to execute a machine cycle is
expressed in T-states.
One T-state is equal to the time period of the internal clock signal
of the processor.
The T-state starts at the falling edge of a clock.
In this time, the first, 3 T-states are used for fetching the opcode
from memory and the remaining T-states are used for internal
operations by the processor.

Opcode Fetch Machine Cycle

The first step of executing any instruction is the Opcode fetch cycle.
In this cycle, the microprocessor brings in the instructions
Opcode from memory.
To differentiate this machine cycle from the very similar
memory read cycle, the control & status signals are set as
follows:
IO/M=0, s0 and s1 are both 1.
This machine cycle has four T-states.
The 8085 uses the first 3 T-states to fetch the opcode.
T4 is used to decode and execute it.
It is also possible for an instruction to have 6 T-states in an
opcode fetch machine cycle.

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Timing Diagram for Opcode Fetch Machine Cycle

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Memory Read Machine Cycle of 8085:

The memory read machine cycle is executed by the
processor to read a data byte from memory.
The processor takes 3T states to execute this cycle.
The instructions which have more than one byte word
size will use the machine cycle after the opcode fetch
machine cycle.

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Memory Read Machine Cycle

The memory read machine cycle is
exactly the same as the opcode fetch
except:
It only has 3 T-states
The s0 signal is set to 0 instead.

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The Memory Read Machine Cycle

To understand the memory read machine cycle, lets study the
execution of the following instruction:
MVI A, 32
In memory, this instruction looks like:
The first byte 3EH represents the opcode for loading a byte
into the accumulator (MVI A), the second byte is the data to
be loaded.
The 8085 needs to read these two bytes from memory before it
can execute the instruction. Therefore, it will need at least two
machine cycles.
The first machine cycle is the opcode fetch discussed
earlier.
The second machine cycle is the Memory Read Cycle.

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2000H

3E

2001H

32

Timing Diagram for Memory Read Machine Cycle

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Memory Write Machine Cycle of 8085:

The memory write machine cycle is executed by the
processor to write a data byte in a memory location.
The processor takes, 3T states to execute this machine
cycle.

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The Memory Write Operation

In a memory write operation:
The 8085 places the address (2065H) on the
address bus
Identifies the operation as a memory write
(IO/M=0, s1=0, s0=1).
Places the contents of the accumulator on the
data bus and asserts the signal WR.
During the last T-state, the contents of the data
bus are saved into the memory location.

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Timing Diagram for Memory Write Machine Cycle

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INTERFACING I/O AND PERIPHERAL

DEVICES:
1. For data transfer from input device to processor
the following operations are performed.

The input device will load the data to the port.

When the port receives a data, it sends message to

the processor to read the data.

The processor will read the data from the port.

After a data have been read by the processor the

input device will load the next data into the port.

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2. For data transfer from processor to output device the following

operations are performed.
The processor will load the data to the port.
The port will send a message to the output device to read the data.
The output device will read the data from the port.
After the data have been read by the output device the processor can load
the next data to the port.
The various INTEL 110 port devices are 8212, 8155/8156, 8255, 8355
and 8755.
8212
The 8212 is a 24 pin IC.
It consists of eight number of D-type latches.
It has 8-input lines DI1 to DI8 and 8-output lines DO1 to DO8
The 8212 can be used as an input or output device
It has two selecting device DS1 (low) and DS2.
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Dimensions of Memory
Memory is usually measured by two numbers: its length and
its width (Length X Width).
The length is the total number of locations.
The width is the number of bits in each location.

The length (total number of locations) is a function of

the number of address lines.
# of memory locations = 2( # of address lines)
So, a memory chip with 10 address lines would have

210 = 1024 locations (1K)

Looking at it from the other side, a memory chip with 4K
locations would need

Log2 4096=12 address lines

The 8085 and Memory

The 8085 has 16 address lines. That means it
can address
216 = 64K memory locations.
Then it will need 1 memory chip with 64 k
locations, or 2 chips with 32 K in each, or 4 with
16 K each or 16 of the 4 K chips, etc.

how would we use these address lines to

control the multiple chips?

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To communicate with other devices two interfacing

devices are used
Memory Interfacing
I/o Interfacing

MEMORY INTERFACING
Require:
Select a chip
Identify the register
Enable the appropriate buffer

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Memory interfacing techniques

Techniques
Absolute Decoding / Full Decoding
Linear Decoding / Partial Decoding

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Absolute Decoding / Full Decoding

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I/O Intefacing
I/O devices can be interfaced to an 8085
I/O Mapped I/O
Memory Mapped I/O

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I/O Mapped I/O

IN addr8
the content of port is moved to A- Register
OUT addr8
The content of A register is moved to port

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Memory Mapped I/O

Mov r,m
LHLD addr
XRA M
STA addr

LDA addr
ADD M
MOV m,r

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Comparison of memory mapped I/O and Peripheral I/O

Characteristics

Memory Mapped

I/O Mapped

Device address

16 bit

8 bit

Control signals for I/O

MEMW MEMR

IOR

Instruction available

STA, LDA, LDAX,

STAX etc.,

IN & OUT

Data Transfer

between any register

and I/O

Between I/O and

accumulator

Maximum no of I/O

64k

Independent

Execution speed

13T for STA &LDA

10T

Hardware

More hardware require

Less hardware

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IOW