Software architecture of

the INTEL 8086

Memory segmentation and
addressing
Block diagram of 8086
Address space & Data organization
Data Types
Registers
Stack
I/O space
RCET

Microprocessor &
Microcontroller

Hardware Architecture of
INTEL 8086
Pin Diagram and Pin Details
min/max mode
Coprocessor and Multiprocessor
configuration
Hardware organization of address space
Control signals
I/O interfaces
RCET

Microprocessor &
Microcontroller

8086 programming and

program development.
Assembly Language
Programming.
Instruction Set.
Assembler Directives.
Programming Exercises.

RCET

Microprocessor &
Microcontroller

Software
Architecture of
INTEL 8086
RCET

Microprocessor & Microcontroller

Software architecture of
the INTEL 8086
Memory segmentation and
addressing
Block diagram of 8086
Address space & Data organization
Data Types
Registers
Stack
I/O space
RCET

Microprocessor &
Microcontroller

Memory segmentation and

addressing
Von Newman architecture & Harvard
architecture
Program Memory & Data Memory
Need for Segmentation

RCET

To implement Harvard architecture

Easy to debug
Same Interfacing ICs can be used
To avoid overlap of stack with normal memory
Compatible with 8085
Microprocessor &
Microcontroller

Von- neuman &Harvard

architecture

RCET

Microprocessor &
Microcontroller

Segmented Memory

RCET

Microprocessor &
Microcontroller

Memory Address
Generation
The BIU has a dedicated adder for
determining physical memory addresses.
Offset Value (16 bits)

Segment Register (16 bits)

0000

Adder

Physical Address (20 Bits)

RCET

Microprocessor &
Microcontroller

Segment : Offset
Address
Logical Address is specified as segment:offset
Physical address is obtained by shifting the
segment address 4 bits to the left and adding
the offset address.
Thus the physical address of the logical address
A4FB:4872 is:
A4FB0
+ 4872
A9822
RCET

Microprocessor &
Microcontroller

10

Segments, Segment
Registers & Offset
Registers

Segment Size = 64KB

Maximum number of segments possible = 4

Logical Address 16 bits
Physical Address 20 bits
2 Logical Addresses for each Segments.
Base Address (16 bits)
Offset Address (16 bits)
Segment registers are used to store the Base
address of the segment.
RCET

Microprocessor &
Microcontroller

11

Segments, Segment
Registers & Offset
Registers

4 Segments in 8086
Code Segment (CS)

Data Segment (DS)SEGMENT

Stack Segment (SS)
Extra Segment (ES)

Code

SEGMEN
T
REGISTE
R

Instruction
Pointer (IP)

DSR

Source Index
(SI)

ESR

Destination
Index (DI)

SSR

Stack Pointer
(SP) / Base
12

Segment
Extra
Segment
Stack
RCET

Microprocessor &
Segment
Microcontroller

REGISTER

CSR

Segment
Data

OFFSET

Block diagram of 8086

RCET

Microprocessor &
Microcontroller

13

Block diagram of 8086

RCET

Microprocessor &
Microcontroller

14

Pipelined architecture of
the 8086 microprocessors

RCET

Microprocessor &
Microcontroller

15

Execution and bus

interface units

RCET

Microprocessor &
Microcontroller

16

8086 Registers
General Purpose
AH

Index
AL

AX

BP
SP

BH

BL

BX

SI
CH

CL

DH

DL

CX

DI

Segment

DX

CS

RCET

Status and Control

SS

Flags

DS

IP

ES

Microprocessor &
Microcontroller

17

General Purpose
Registers
AX - the
Accumulator
BX - the Base
Register
CX - the Count
Register
DX - the Data
Register

Normally used for storing temporary results

Each of the registers is 16 bits wide (AX, BX, CX, DX)
Can be accessed as either 16 or 8 bits AX, AH, AL

RCET

Microprocessor &
Microcontroller

18

General Purpose
Registers
AX
Accumulator Register
Preferred register to use in arithmetic, logic
and data transfer instructions because it
generates the shortest Machine Language
Code
Must be used in multiplication and division
operations
Must also be used in I/O operations

BX
Base Register
Also serves as an address register
RCET

Microprocessor &
Microcontroller

19

General Purpose
Registers
CX
Count register
Used as a loop counter
Used in shift and rotate operations

DX
Data register
Used in multiplication and division
Also used in I/O operations
RCET

Microprocessor &
Microcontroller

20

Pointer and Index

Registers

All 16 bits wide, L/H bytes are not accessible

Used as memory pointers
Example: MOV AH, [SI]
Move the byte stored in memory location whose address is
contained in register SI to register AH

IP is not under direct control of the programmer

RCET

Microprocessor &
Microcontroller

21

Flag Register

Overflow

Carry

Direction

Parity

Interrupt enable

Auxiliary Carry

Trap Zero
Sign
RCET

Microprocessor &
Microcontroller

6 are status fla

3 are control fla
22

8086 Programmers
Model
ES
CS
SS
DS
IP

BIU registers
(20 bit adder)

EU registers

AX
BX
CX
DX

AH
BH
CH
DH

Extra Segment
Code Segment
Stack Segment
Data Segment
Instruction Pointer

AL
BL
CL
DL
SP
BP
SI
DI
FLAGS

RCET

Microprocessor &
Microcontroller

Accumulator
Base Register
Count Register
Data Register
Stack Pointer
Base Pointer
Source Index Register
Destination Index Registe

23

The Stack
The stack is used for temporary storage of
information such as data or addresses.
When a CALL is executed, the 8086 automatically
PUSHes the current value of CS and IP onto the
stack.
Other registers can also be pushed
Before return from the subroutine, POP
instructions can be used to pop values back from
the stack into the corresponding registers.
RCET

Microprocessor &
Microcontroller

24

The Stack

RCET

Microprocessor &
Microcontroller

25

Hardware
Architecture of
INTEL 8086
RCET

Microprocessor & Microcontroller

26

Hardware Architecture of
INTEL 8086
Pin Diagram and Pin Details
min/max mode
Hardware organization of address space
Control signals
Coprocessor and Multiprocessor
configuration
I/O interfaces
RCET

Microprocessor &
Microcontroller

27

INTEL 8086 - Pin Diagram

RCET

Microprocessor &
Microcontroller

28

INTEL 8086 - Pin Details

Power
Supply
5V 10%

Grou
nd

Reset
Registers,
seg regs,
flags
CS: FFFFH,
IP: 0000H
If high for
minimum 4
clks

Clock
Duty cycle:
33%
RCET

Microprocessor &
Microcontroller

29

INTEL 8086 - Pin Details

Address/Data
Bus:

Address Latch
Enable:

Contains
address bits A15A0 when ALE is 1
& data bits D15
D0 when ALE is
0.

RCET

When high,
multiplexed
address/data bus
contains address
information.

Microprocessor &
Microcontroller

30

INTEL 8086 - Pin Details

INTERRU
PT

Non maskable
interrupt

Interrupt
request
RCET

Interrupt
acknowled
ge
Microprocessor &
Microcontroller

31

INTEL 8086 - Pin Details

Direct
Memory
Access
Hold

Hold
acknowledg
e
RCET

Microprocessor &
Microcontroller

32

INTEL 8086 - Pin Details

Address/Statu
s Bus
Address bits A19
A16 & Status
bits S6 S3

RCET

Microprocessor &
Microcontroller

33

INTEL 8086 - Pin Details

BHE#, A0:

Bus High
Enable/S7

0,0: Whole word

(16-bits)

Enables most
significant data
bits D15 D8
during read or
write operation.

0,1: High byte

to/from odd
address
1,0: Low byte
to/from even
address

S7: Always 1.

1,1: No selection

RCET

Microprocessor &
Microcontroller

34

INTEL 8086 - Pin Details

Min/Max
mode
Minimum Mode:
+5V
Maximum Mode:
0V Mode
Minimum

Pins
Maximum
Mode Pins

RCET

Microprocessor &
Microcontroller

35

Minimum Mode- Pin

Details

RCET

Microprocessor &
Microcontroller

36

Maximum Mode - Pin

Details
S2 S1 S0
000: INTA
001: read I/O
port
010: write I/O
port
011: halt
100: code access
101: read
memory
110: write
memory
111: none
-passive
RCET

Status
Signal
Inputs to 8288 to
generate
eliminated signals
due to max mode.
Microprocessor &
Microcontroller

37

Maximum Mode - Pin

Details
Lock
Output
Used
to
lock
peripherals off the
system

DMA
Request/Gr
ant

Activated by using
the LOCK: prefix on
any instruction

Lock Output

RCET

Microprocessor &
Microcontroller

38

Maximum Mode - Pin

Details

QS1 QS0
00: Queue is idle
01: First byte of
opcode
10: Queue is empty
11: Subsequent byte
of opcode

RCET

Queue
Status
Microprocessor &
Microcontroller

Used by numeric
coprocessor
(8087) 39

Minimum Mode 8086

System

RCET

Microprocessor &
Microcontroller

40

Minimum Mode 8086

System

RCET

Microprocessor &
Microcontroller

41

Read Cycle timing

Diagram for Minimum Mode

RCET

Microprocessor &
Microcontroller

42

Write Cycle timing

Diagram for Minimum Mode

RCET

Microprocessor &
Microcontroller

43

Maximum Mode 8086

System

RCET

Microprocessor &
Microcontroller

44

Maximum Mode 8086

System

RCET

Microprocessor &
Microcontroller

45

Maximum Mode 8086

System
Here, either a numeric coprocessor of the type 8087 or
another processor is interfaced with 8086.

The Memory, Address Bus, Data Buses are shared

resources between the two processors.
The control signals for Maximum mode of operation are
generated by the Bus Controller chip 8788.
The three status outputs S0*, S1*, S2* from the
processor are input to 8788.
The outputs of the bus controller are the Control Signals,
namely DEN, DT/R*, IORC*, IOWTC*, MWTC*, MRDC*, ALE
etc.
RCET

Microprocessor &
Microcontroller

46

Memory Read timing in

Maximum Mode

RCET

Microprocessor &
Microcontroller

47

Memory Write timing in

Maximum Mode

RCET

Microprocessor &
Microcontroller

48

Memory Banking

RCET

Microprocessor &
Microcontroller

49

Interface 8086 to 6116

Static RAM
A0, BHE*

A
____
BHE
ALE
D

20

21

Latch

A(11-1)
D(7-0)

A(19-12)
16

6116 (2K x8)

A(10-0)
D(7-0)
__
R/W
OE*
CS*

Low byte
(Even Bank)

Addr
Decoder RAMCS*

8086

__
M/IO
___
WR
___
RD

A0
MEM*

BHE*

A(11-1)
D(15-8)

A(10-0)
D(7-0)
__
R/W
OE*
CS*

High byte
(Odd Bank)

50

8086 Interrupts

RCET

Microprocessor &
Microcontroller

51

8086 Interrupts
Procedure

RCET

Microprocessor &
Microcontroller

52

8086 External Interrupts

RCET

Microprocessor &
Microcontroller

53

8086 Interrupt Vector

Table

RCET

Microprocessor &
Microcontroller

54

8086 Interrupt Vector

Table

RCET

Microprocessor &
Microcontroller

55

Total Memory and IVT

RCET

Microprocessor &
Microcontroller

56

8086 Control Signals

1.ALE
2.BHE
3.M/IO
4.DT/R
5.RD
6.WR
7.DEN
RCET

Microprocessor &
Microcontroller

57

Coprocessor and
Multiprocessor
configuration
Multiprocessor Systems refer to the

use of
multiple processors that executes instructions
simultaneously and communicate with each
other using mail boxes and Semaphores.

Maximum mode of 8086 is designed to

implement
3
basic
multiprocessor
configurations:
1. Coprocessor (8087)
2. Closely coupled (8089)
3. Loosely coupled (Multibus)
RCET

Microprocessor &
Microcontroller

58

Coprocessor and
Multiprocessor
configuration
Coprocessors
and
Closely
coupled
configurations are similar in that both the
8086 and the external processor shares the:
- Memory
- I/O system
- Bus & bus control logic
- Clock generator

RCET

Microprocessor &
Microcontroller

59

Coprocessor / Closely
Coupled Configuration

RCET

Microprocessor &
Microcontroller

60

TEST pin of 8086

Used in conjunction with the WAIT instruction
in multiprocessing environments.
This is input from the 8087 coprocessor.
During execution of a wait instruction, the CPU
checks this signal.
If it is low, execution of the signal will continue;
if not, it will stop executing.
RCET

Microprocessor &
Microcontroller

61

Coprocessor Execution
Example

Coprocessor cannot take control of the bus, it does everything through the CPU

RCET

Microprocessor &
Microcontroller

62

Closely Coupled Execution

Example

Closely Coupled
processor may
take control of the
bus independently.
Two 8086s cannot
be closely coupled.

RCET

Microprocessor &
Microcontroller

63

Loosely Coupled
Configuration
has shared system bus, system memory, and
system I/O.
each processor has its own clock as well as its
own memory (in addition to access to the system
resources).
Used for
systems.

medium

to

large

multiprocessor

Each module is capable of being the bus master.

Any module could be a processor capable of being
a bus master, a coprocessor configuration or a
closely coupled configuration.
RCET

Microprocessor &
Microcontroller

64

Loosely Coupled
Configuration
No direct connections between the modules.
Each share the system bus and communicate
through shared resources.
Processor in their separate modules can
simultaneously access their private subsystems
through their local busses, and perform their local
data
references
and
instruction
fetches
independently. This results in improved degree
of concurrent processing.
Excellent for real time applications, as separate
modules can be assigned specialized tasks
RCET

Microprocessor &
Microcontroller

65

Advantages of
Multiprocessor
Configuration

1. High system throughput can be achieved by

having more than one CPU.
2. The system can be expanded in modular form.
Each bus master module is an independent unit and
normally resides on a separate PC board. One can be
added or removed without affecting the others in the
system.

3. A failure in one module normally does not affect

the breakdown of the entire system and the faulty
module can be easily detected and replaced
4. Each bus master has its own local bus to access
dedicated memory or IO devices. So a greater
degree of parallel processing can be achieved.
RCET

Microprocessor &
Microcontroller

66

WAIT State

A wait state (Tw) is an extra clocking period,

inserted between T2 and T3, to lengthen the bus
cycle,
allowing
slower
memory
and
I/O
components to respond.
The READY input is sampled at the end of T2, and
again, if necessary in the middle of Tw. If READY
is 0 then a Tw is inserted.
RCET

Microprocessor &
Microcontroller

67

8086 System Memory

Circuitry
1. Minimum Mode System Memory
Circuitry

2. Maximum Mode System Memory

Circuitry

RCET

Microprocessor &
Microcontroller

68

Minimum Mode System

Memory Circuitry

RCET

Microprocessor &
Microcontroller

69

Maximum Mode System Memory

Circuitry

RCET

Microprocessor &
Microcontroller

70