Chapter 4
The Processor
CPU performance factors
Instruction count
Determined by CPU hardware
We will examine two MIPS implementations
Determined by ISA and compiler
CPI and Cycle time
4.1 Introduction
Introduction
A simplified version
A more realistic pipelined version
Simple subset, shows most aspects
Memory reference: lw, sw
Arithmetic/logical: add, sub, and, or, slt
Control transfer: beq, j
Chapter 4 The Processor 2
Instruction Execution
PC instruction memory, fetch instruction
Register numbers register file, read registers
Depending on instruction class
Use ALU to calculate
Arithmetic result
Memory address for load/store
Branch target address
Access data memory for load/store
PC target address or PC + 4
Chapter 4 The Processor 3
CPU Overview
Chapter 4 The Processor 4
Multiplexers
Cant just join
wires together
Use multiplexers
Chapter 4 The Processor 5
Control
Chapter 4 The Processor 6
Information encoded in binary
Combinational element
Low voltage = 0, High voltage = 1
One wire per bit
Multi-bit data encoded on multi-wire buses
4.2 Logic Design Conventions
Logic Design Basics
Operate on data
Output is a function of input
State (sequential) elements
Store information
Chapter 4 The Processor 7
Combinational Elements
AND-gate
Y = A& B
A
B
Multiplexer
A
+
Y = A+ B
Adder
Y = S ? I1 : I0
I0
I1
M
u
x
Arithmetic/Logic Unit
Y = F(A, B)
A
ALU
B
F
Chapter 4 The Processor 8
Sequential Elements
Register: stores data in a circuit
Uses a clock signal to determine when to
update the stored value
Edge-triggered: update when Clk changes
from 0 to 1
Clk
D
Clk
D
Q
Chapter 4 The Processor 9
Sequential Elements
Register with write control
Only updates on clock edge when write
control input is 1
Used when stored value is required later
Clk
D
Write
Clk
Write
D
Q
Chapter 4 The Processor 10
Clocking Methodology
Combinational logic transforms data
during clock cycles
Between clock edges
Input from state elements, output to state
element
Longest delay determines clock period
Chapter 4 The Processor 11
Datapath
Elements that process data and addresses
in the CPU
4.3 Building a Datapath
Building a Datapath
Registers, ALUs, muxs, memories,
We will build a MIPS datapath
incrementally
Refining the overview design
Chapter 4 The Processor 12
Instruction Fetch
32-bit
register
Increment by
4 for next
instruction
Chapter 4 The Processor 13
R-Format Instructions
Read two register operands
Perform arithmetic/logical operation
Write register result
Chapter 4 The Processor 14
Load/Store Instructions
Read register operands
Calculate address using 16-bit offset
Use ALU, but sign-extend offset
Load: Read memory and update register
Store: Write register value to memory
Chapter 4 The Processor 15
Branch Instructions
Read register operands
Compare operands
Use ALU, subtract and check Zero output
Calculate target address
Sign-extend displacement
Shift left 2 places (word displacement)
Add to PC + 4
Already calculated by instruction fetch
Chapter 4 The Processor 16
Branch Instructions
Just
re-routes
wires
Sign-bit wire
replicated
Chapter 4 The Processor 17
Composing the Elements
First-cut data path does an instruction in
one clock cycle
Each datapath element can only do one
function at a time
Hence, we need separate instruction and data
memories
Use multiplexers where alternate data
sources are used for different instructions
Chapter 4 The Processor 18
R-Type/Load/Store Datapath
Chapter 4 The Processor 19
Full Datapath
Chapter 4 The Processor 20
ALU used for
Load/Store: F = add
Branch: F = subtract
R-type: F depends on funct field
ALU control
Function
0000
AND
0001
OR
0010
add
0110
subtract
0111
set-on-less-than
1100
NOR
4.4 A Simple Implementation Scheme
ALU Control
Chapter 4 The Processor 21
ALU Control
Assume 2-bit ALUOp derived from opcode
Combinational logic derives ALU control
opcode
ALUOp
Operation
funct
ALU function
ALU control
lw
00
load word
XXXXXX
add
0010
sw
00
store word
XXXXXX
add
0010
beq
01
branch equal
XXXXXX
subtract
0110
R-type
10
add
100000
add
0010
subtract
100010
subtract
0110
AND
100100
AND
0000
OR
100101
OR
0001
set-on-less-than
101010
set-on-less-than
0111
Chapter 4 The Processor 22
The Main Control Unit
Control signals derived from instruction
R-type
Load/
Store
Branch
rs
rt
rd
shamt
funct
31:26
25:21
20:16
15:11
10:6
5:0
35 or 43
rs
rt
address
31:26
25:21
20:16
15:0
rs
rt
address
31:26
25:21
20:16
15:0
opcode
always
read
read,
except
for load
write for
R-type
and load
sign-extend
and add
Chapter 4 The Processor 23
Datapath With Control
Chapter 4 The Processor 24
R-Type Instruction
Chapter 4 The Processor 25
Load Instruction
Chapter 4 The Processor 26
Branch-on-Equal Instruction
Chapter 4 The Processor 27
Implementing Jumps
Jump
address
31:26
25:0
Jump uses word address
Update PC with concatenation of
Top 4 bits of old PC
26-bit jump address
00
Need an extra control signal decoded from
opcode
Chapter 4 The Processor 28
Datapath With Jumps Added
Chapter 4 The Processor 29
Performance Issues
Longest delay determines clock period
Not feasible to vary period for different
instructions
Violates design principle
Critical path: load instruction
Instruction memory register file ALU
data memory register file
Making the common case fast
We will improve performance by pipelining
Chapter 4 The Processor 30
Pipelined laundry: overlapping execution
Parallelism improves performance
Four loads:
4.5 An Overview of Pipelining
Pipelining Analogy
Speedup
= 8/3.5 = 2.3
Non-stop:
Speedup
= 2n/0.5n + 1.5 4
= number of stages
Chapter 4 The Processor 31
MIPS Pipeline
Five stages, one step per stage
1.
2.
3.
4.
5.
IF: Instruction fetch from memory
ID: Instruction decode & register read
EX: Execute operation or calculate address
MEM: Access memory operand
WB: Write result back to register
Chapter 4 The Processor 32
Pipeline Performance
Assume time for stages is
100ps for register read or write
200ps for other stages
Compare pipelined datapath with single-cycle
datapath
Instr
Instr fetch Register
read
ALU op
Memory
access
Register
write
Total time
lw
200ps
100 ps
200ps
200ps
100 ps
800ps
sw
200ps
100 ps
200ps
200ps
R-format
200ps
100 ps
200ps
beq
200ps
100 ps
200ps
700ps
100 ps
600ps
500ps
Chapter 4 The Processor 33
Pipeline Performance
Single-cycle (Tc= 800ps)
Pipelined (Tc= 200ps)
Chapter 4 The Processor 34
Pipeline Speedup
If all stages are balanced
i.e., all take the same time
Time between instructionspipelined
= Time between instructionsnonpipelined
Number of stages
If not balanced, speedup is less
Speedup due to increased throughput
Latency (time for each instruction) does not
decrease
Chapter 4 The Processor 35
Pipelining and ISA Design
MIPS ISA designed for pipelining
All instructions are 32-bits
Few and regular instruction formats
Can decode and read registers in one step
Load/store addressing
Easier to fetch and decode in one cycle
c.f. x86: 1- to 17-byte instructions
Can calculate address in 3rd stage, access memory
in 4th stage
Alignment of memory operands
Memory access takes only one cycle
Chapter 4 The Processor 36
Hazards
Situations that prevent starting the next
instruction in the next cycle
Structure hazards
Data hazard
A required resource is busy
Need to wait for previous instruction to
complete its data read/write
Control hazard
Deciding on control action depends on
previous instruction
Chapter 4 The Processor 37
Structure Hazards
Conflict for use of a resource
In MIPS pipeline with a single memory
Load/store requires data access
Instruction fetch would have to stall for that
cycle
Would cause a pipeline bubble
Hence, pipelined datapaths require
separate instruction/data memories
Or separate instruction/data caches
Chapter 4 The Processor 38
Data Hazards
An instruction depends on completion of
data access by a previous instruction
add
sub
$s0, $t0, $t1
$t2, $s0, $t3
Chapter 4 The Processor 39
Forwarding (aka Bypassing)
Use result when it is computed
Dont wait for it to be stored in a register
Requires extra connections in the datapath
Chapter 4 The Processor 40
Load-Use Data Hazard
Cant always avoid stalls by forwarding
If value not computed when needed
Cant forward backward in time!
Chapter 4 The Processor 41
Code Scheduling to Avoid Stalls
Reorder code to avoid use of load result in
the next instruction
C code for A = B + E; C = B + F;
stall
stall
lw
lw
add
sw
lw
add
sw
$t1,
$t2,
$t3,
$t3,
$t4,
$t5,
$t5,
0($t0)
4($t0)
$t1, $t2
12($t0)
8($t0)
$t1, $t4
16($t0)
13 cycles
lw
lw
lw
add
sw
add
sw
$t1,
$t2,
$t4,
$t3,
$t3,
$t5,
$t5,
0($t0)
4($t0)
8($t0)
$t1, $t2
12($t0)
$t1, $t4
16($t0)
11 cycles
Chapter 4 The Processor 42
Control Hazards
Branch determines flow of control
Fetching next instruction depends on branch
outcome
Pipeline cant always fetch correct instruction
Still working on ID stage of branch
In MIPS pipeline
Need to compare registers and compute
target early in the pipeline
Add hardware to do it in ID stage
Chapter 4 The Processor 43
Stall on Branch
Wait until branch outcome determined
before fetching next instruction
Chapter 4 The Processor 44
Branch Prediction
Longer pipelines cant readily determine
branch outcome early
Predict outcome of branch
Stall penalty becomes unacceptable
Only stall if prediction is wrong
In MIPS pipeline
Can predict branches not taken
Fetch instruction after branch, with no delay
Chapter 4 The Processor 45
MIPS with Predict Not Taken
Prediction
correct
Prediction
incorrect
Chapter 4 The Processor 46
More-Realistic Branch Prediction
Static branch prediction
Based on typical branch behavior
Example: loop and if-statement branches
Predict backward branches taken
Predict forward branches not taken
Dynamic branch prediction
Hardware measures actual branch behavior
e.g., record recent history of each branch
Assume future behavior will continue the trend
When wrong, stall while re-fetching, and update history
Chapter 4 The Processor 47
Pipeline Summary
The BIG Picture
Pipelining improves performance by
increasing instruction throughput
Subject to hazards
Executes multiple instructions in parallel
Each instruction has the same latency
Structure, data, control
Instruction set design affects complexity of
pipeline implementation
Chapter 4 The Processor 48
4.6 Pipelined Datapath and Control
MIPS Pipelined Datapath
MEM
Right-to-left
flow leads to
hazards
WB
Chapter 4 The Processor 49
Pipeline registers
Need registers between stages
To hold information produced in previous cycle
Chapter 4 The Processor 50
Pipeline Operation
Cycle-by-cycle flow of instructions through
the pipelined datapath
Single-clock-cycle pipeline diagram
c.f. multi-clock-cycle diagram
Shows pipeline usage in a single cycle
Highlight resources used
Graph of operation over time
Well look at single-clock-cycle diagrams
for load & store
Chapter 4 The Processor 51
IF for Load, Store,
Chapter 4 The Processor 52
ID for Load, Store,
Chapter 4 The Processor 53
EX for Load
Chapter 4 The Processor 54
MEM for Load
Chapter 4 The Processor 55
WB for Load
Wrong
register
number
Chapter 4 The Processor 56
Corrected Datapath for Load
Chapter 4 The Processor 57
EX for Store
Chapter 4 The Processor 58
MEM for Store
Chapter 4 The Processor 59
WB for Store
Chapter 4 The Processor 60
Multi-Cycle Pipeline Diagram
Form showing resource usage
Chapter 4 The Processor 61
Multi-Cycle Pipeline Diagram
Traditional form
Chapter 4 The Processor 62
Single-Cycle Pipeline Diagram
State of pipeline in a given cycle
Chapter 4 The Processor 63
Pipelined Control (Simplified)
Chapter 4 The Processor 64
Pipelined Control
Control signals derived from instruction
As in single-cycle implementation
Chapter 4 The Processor 65
Pipelined Control
Chapter 4 The Processor 66
Consider this sequence:
sub
and
or
add
sw
$2, $1,$3
$12,$2,$5
$13,$6,$2
$14,$2,$2
$15,100($2)
We can resolve hazards with forwarding
4.7 Data Hazards: Forwarding vs. Stalling
Data Hazards in ALU Instructions
How do we detect when to forward?
Chapter 4 The Processor 67
Dependencies & Forwarding
Chapter 4 The Processor 68
Detecting the Need to Forward
Pass register numbers along pipeline
ALU operand register numbers in EX stage
are given by
e.g., ID/EX.RegisterRs = register number for Rs
sitting in ID/EX pipeline register
ID/EX.RegisterRs, ID/EX.RegisterRt
Data hazards when
1a. EX/MEM.RegisterRd = ID/EX.RegisterRs
1b. EX/MEM.RegisterRd = ID/EX.RegisterRt
2a. MEM/WB.RegisterRd = ID/EX.RegisterRs
2b. MEM/WB.RegisterRd = ID/EX.RegisterRt
Fwd from
EX/MEM
pipeline reg
Fwd from
MEM/WB
pipeline reg
Chapter 4 The Processor 69
Detecting the Need to Forward
But only if forwarding instruction will write
to a register!
EX/MEM.RegWrite, MEM/WB.RegWrite
And only if Rd for that instruction is not
$zero
EX/MEM.RegisterRd 0,
MEM/WB.RegisterRd 0
Chapter 4 The Processor 70
Forwarding Paths
Chapter 4 The Processor 71
Forwarding Conditions
EX hazard
if (EX/MEM.RegWrite and (EX/MEM.RegisterRd 0)
and (EX/MEM.RegisterRd = ID/EX.RegisterRs))
ForwardA = 10
if (EX/MEM.RegWrite and (EX/MEM.RegisterRd 0)
and (EX/MEM.RegisterRd = ID/EX.RegisterRt))
ForwardB = 10
MEM hazard
if (MEM/WB.RegWrite and (MEM/WB.RegisterRd 0)
and (MEM/WB.RegisterRd = ID/EX.RegisterRs))
ForwardA = 01
if (MEM/WB.RegWrite and (MEM/WB.RegisterRd 0)
and (MEM/WB.RegisterRd = ID/EX.RegisterRt))
ForwardB = 01
Chapter 4 The Processor 72
Double Data Hazard
Consider the sequence:
add $1,$1,$2
add $1,$1,$3
add $1,$1,$4
Both hazards occur
Want to use the most recent
Revise MEM hazard condition
Only fwd if EX hazard condition isnt true
Chapter 4 The Processor 73
Revised Forwarding Condition
MEM hazard
if (MEM/WB.RegWrite and (MEM/WB.RegisterRd 0)
and not (EX/MEM.RegWrite and (EX/MEM.RegisterRd 0)
and (EX/MEM.RegisterRd = ID/EX.RegisterRs))
and (MEM/WB.RegisterRd = ID/EX.RegisterRs))
ForwardA = 01
if (MEM/WB.RegWrite and (MEM/WB.RegisterRd 0)
and not (EX/MEM.RegWrite and (EX/MEM.RegisterRd 0)
and (EX/MEM.RegisterRd = ID/EX.RegisterRt))
and (MEM/WB.RegisterRd = ID/EX.RegisterRt))
ForwardB = 01
Chapter 4 The Processor 74
Datapath with Forwarding
Chapter 4 The Processor 75
Load-Use Data Hazard
Need to stall
for one cycle
Chapter 4 The Processor 76
Load-Use Hazard Detection
Check when using instruction is decoded
in ID stage
ALU operand register numbers in ID stage
are given by
Load-use hazard when
IF/ID.RegisterRs, IF/ID.RegisterRt
ID/EX.MemRead and
((ID/EX.RegisterRt = IF/ID.RegisterRs) or
(ID/EX.RegisterRt = IF/ID.RegisterRt))
If detected, stall and insert bubble
Chapter 4 The Processor 77
How to Stall the Pipeline
Force control values in ID/EX register
to 0
EX, MEM and WB do nop (no-operation)
Prevent update of PC and IF/ID register
Using instruction is decoded again
Following instruction is fetched again
1-cycle stall allows MEM to read data for lw
Can subsequently forward to EX stage
Chapter 4 The Processor 78
Stall/Bubble in the Pipeline
Stall inserted
here
Chapter 4 The Processor 79
Stall/Bubble in the Pipeline
Or, more
accurately
Chapter 4 The Processor 80
Datapath with Hazard Detection
Chapter 4 The Processor 81
Stalls and Performance
The BIG Picture
Stalls reduce performance
But are required to get correct results
Compiler can arrange code to avoid
hazards and stalls
Requires knowledge of the pipeline structure
Chapter 4 The Processor 82
If branch outcome determined in MEM
4.8 Control Hazards
Branch Hazards
Flush these
instructions
(Set control
values to 0)
PC
Chapter 4 The Processor 83
Reducing Branch Delay
Move hardware to determine outcome to ID
stage
Target address adder
Register comparator
Example: branch taken
36:
40:
44:
48:
52:
56:
72:
sub
beq
and
or
add
slt
...
lw
$10,
$1,
$12,
$13,
$14,
$15,
$4,
$3,
$2,
$2,
$4,
$6,
$8
7
$5
$6
$2
$7
$4, 50($7)
Chapter 4 The Processor 84
Example: Branch Taken
Chapter 4 The Processor 85
Example: Branch Taken
Chapter 4 The Processor 86
Data Hazards for Branches
If a comparison register is a destination of
2nd or 3rd preceding ALU instruction
add $1, $2, $3
IF
add $4, $5, $6
beq $1, $4, target
ID
EX
MEM
WB
IF
ID
EX
MEM
WB
IF
ID
EX
MEM
WB
IF
ID
EX
MEM
WB
Can resolve using forwarding
Chapter 4 The Processor 87
Data Hazards for Branches
If a comparison register is a destination of
preceding ALU instruction or 2nd preceding
load instruction
lw
Need 1 stall cycle
$1, addr
IF
add $4, $5, $6
beq stalled
beq $1, $4, target
ID
EX
MEM
WB
IF
ID
EX
MEM
WB
IF
ID
ID
EX
MEM
WB
Chapter 4 The Processor 88
Data Hazards for Branches
If a comparison register is a destination of
immediately preceding load instruction
lw
Need 2 stall cycles
$1, addr
IF
beq stalled
beq stalled
beq $1, $0, target
ID
EX
IF
ID
MEM
WB
ID
ID
EX
MEM
WB
Chapter 4 The Processor 89
Dynamic Branch Prediction
In deeper and superscalar pipelines, branch
penalty is more significant
Use dynamic prediction
Branch prediction buffer (aka branch history table)
Indexed by recent branch instruction addresses
Stores outcome (taken/not taken)
To execute a branch
Check table, expect the same outcome
Start fetching from fall-through or target
If wrong, flush pipeline and flip prediction
Chapter 4 The Processor 90
1-Bit Predictor: Shortcoming
Inner loop branches mispredicted twice!
outer:
inner:
beq , , inner
beq , , outer
Mispredict as taken on last iteration of inner
loop
Then mispredict as not taken on first
iteration of inner loop next time around
Chapter 4 The Processor 91
2-Bit Predictor
Only change prediction on two successive
mispredictions
Chapter 4 The Processor 92
Calculating the Branch Target
Even with predictor, still need to calculate
the target address
1-cycle penalty for a taken branch
Branch target buffer
Cache of target addresses
Indexed by PC when instruction fetched
If hit and instruction is branch predicted taken, can
fetch target immediately
Chapter 4 The Processor 93
Unexpected events requiring change
in flow of control
Different ISAs use the terms differently
Exception
Arises within the CPU
e.g., undefined opcode, overflow, syscall,
Interrupt
4.9 Exceptions
Exceptions and Interrupts
From an external I/O controller
Dealing with them without sacrificing
performance is hard
Chapter 4 The Processor 94
Handling Exceptions
In MIPS, exceptions managed by a System
Control Coprocessor (CP0)
Save PC of offending (or interrupted) instruction
In MIPS: Exception Program Counter (EPC)
Save indication of the problem
In MIPS: Cause register
Well assume 1-bit
0 for undefined opcode, 1 for overflow
Jump to handler at 8000 00180
Chapter 4 The Processor 95
An Alternate Mechanism
Vectored Interrupts
Example:
Handler address determined by the cause
Undefined opcode:
Overflow:
:
C000 0000
C000 0020
C000 0040
Instructions either
Deal with the interrupt, or
Jump to real handler
Chapter 4 The Processor 96
Handler Actions
Read cause, and transfer to relevant
handler
Determine action required
If restartable
Take corrective action
use EPC to return to program
Otherwise
Terminate program
Report error using EPC, cause,
Chapter 4 The Processor 97
Exceptions in a Pipeline
Another form of control hazard
Consider overflow on add in EX stage
add $1, $2, $1
Prevent $1 from being clobbered
Complete previous instructions
Flush add and subsequent instructions
Set Cause and EPC register values
Transfer control to handler
Similar to mispredicted branch
Use much of the same hardware
Chapter 4 The Processor 98
Pipeline with Exceptions
Chapter 4 The Processor 99
Exception Properties
Restartable exceptions
Pipeline can flush the instruction
Handler executes, then returns to the
instruction
Refetched and executed from scratch
PC saved in EPC register
Identifies causing instruction
Actually PC + 4 is saved
Handler must adjust
Chapter 4 The Processor 100
Exception Example
Exception on add in
40
44
48
4C
50
54
sub
and
or
add
slt
lw
$11,
$12,
$13,
$1,
$15,
$16,
$2, $4
$2, $5
$2, $6
$2, $1
$6, $7
50($7)
sw
sw
$25, 1000($0)
$26, 1004($0)
Handler
80000180
80000184
Chapter 4 The Processor 101
Exception Example
Chapter 4 The Processor 102
Exception Example
Chapter 4 The Processor 103
Multiple Exceptions
Pipelining overlaps multiple instructions
Simple approach: deal with exception from
earliest instruction
Could have multiple exceptions at once
Flush subsequent instructions
Precise exceptions
In complex pipelines
Multiple instructions issued per cycle
Out-of-order completion
Maintaining precise exceptions is difficult!
Chapter 4 The Processor 104
Imprecise Exceptions
Just stop pipeline and save state
Including exception cause(s)
Let the handler work out
Which instruction(s) had exceptions
Which to complete or flush
May require manual completion
Simplifies hardware, but more complex handler
software
Not feasible for complex multiple-issue
out-of-order pipelines
Chapter 4 The Processor 105
Pipelining: executing multiple instructions in
parallel
To increase ILP
Deeper pipeline
Less work per stage shorter clock cycle
Multiple issue
Replicate pipeline stages multiple pipelines
Start multiple instructions per clock cycle
CPI < 1, so use Instructions Per Cycle (IPC)
E.g., 4GHz 4-way multiple-issue
16 BIPS, peak CPI = 0.25, peak IPC = 4
But dependencies reduce this in practice
4.10 Parallelism and Advanced Instruction Level Parallelism
Instruction-Level Parallelism (ILP)
Chapter 4 The Processor 106
Multiple Issue
Static multiple issue
Compiler groups instructions to be issued together
Packages them into issue slots
Compiler detects and avoids hazards
Dynamic multiple issue
CPU examines instruction stream and chooses
instructions to issue each cycle
Compiler can help by reordering instructions
CPU resolves hazards using advanced techniques at
runtime
Chapter 4 The Processor 107
Speculation
Guess what to do with an instruction
Start operation as soon as possible
Check whether guess was right
If so, complete the operation
If not, roll-back and do the right thing
Common to static and dynamic multiple issue
Examples
Speculate on branch outcome
Roll back if path taken is different
Speculate on load
Roll back if location is updated
Chapter 4 The Processor 108
Compiler/Hardware Speculation
Compiler can reorder instructions
e.g., move load before branch
Can include fix-up instructions to recover
from incorrect guess
Hardware can look ahead for instructions
to execute
Buffer results until it determines they are
actually needed
Flush buffers on incorrect speculation
Chapter 4 The Processor 109
Speculation and Exceptions
What if exception occurs on a
speculatively executed instruction?
Static speculation
e.g., speculative load before null-pointer
check
Can add ISA support for deferring exceptions
Dynamic speculation
Can buffer exceptions until instruction
completion (which may not occur)
Chapter 4 The Processor 110
Static Multiple Issue
Compiler groups instructions into issue
packets
Group of instructions that can be issued on a
single cycle
Determined by pipeline resources required
Think of an issue packet as a very long
instruction
Specifies multiple concurrent operations
Very Long Instruction Word (VLIW)
Chapter 4 The Processor 111
Scheduling Static Multiple Issue
Compiler must remove some/all hazards
Reorder instructions into issue packets
No dependencies with a packet
Possibly some dependencies between
packets
Varies between ISAs; compiler must know!
Pad with nop if necessary
Chapter 4 The Processor 112
MIPS with Static Dual Issue
Two-issue packets
One ALU/branch instruction
One load/store instruction
64-bit aligned
ALU/branch, then load/store
Pad an unused instruction with nop
Address
Instruction type
Pipeline Stages
ALU/branch
IF
ID
EX
MEM
WB
n+4
Load/store
IF
ID
EX
MEM
WB
n+8
ALU/branch
IF
ID
EX
MEM
WB
n + 12
Load/store
IF
ID
EX
MEM
WB
n + 16
ALU/branch
IF
ID
EX
MEM
WB
n + 20
Load/store
IF
ID
EX
MEM
WB
Chapter 4 The Processor 113
MIPS with Static Dual Issue
Chapter 4 The Processor 114
Hazards in the Dual-Issue MIPS
More instructions executing in parallel
EX data hazard
Forwarding avoided stalls with single-issue
Now cant use ALU result in load/store in same packet
Load-use hazard
add $t0, $s0, $s1
load $s2, 0($t0)
Split into two packets, effectively a stall
Still one cycle use latency, but now two instructions
More aggressive scheduling required
Chapter 4 The Processor 115
Scheduling Example
Schedule this for dual-issue MIPS
Loop: lw
addu
sw
addi
bne
Loop:
$t0,
$t0,
$t0,
$s1,
$s1,
0($s1)
$t0, $s2
0($s1)
$s1,4
$zero, Loop
#
#
#
#
#
$t0=array element
add scalar in $s2
store result
decrement pointer
branch $s1!=0
ALU/branch
Load/store
cycle
nop
lw
addi $s1, $s1,4
nop
addu $t0, $t0, $s2
nop
bne
sw
$s1, $zero, Loop
$t0, 0($s1)
$t0, 4($s1)
IPC = 5/4 = 1.25 (c.f. peak IPC = 2)
Chapter 4 The Processor 116
Loop Unrolling
Replicate loop body to expose more
parallelism
Reduces loop-control overhead
Use different registers per replication
Called register renaming
Avoid loop-carried anti-dependencies
Store followed by a load of the same register
Aka name dependence
Reuse of a register name
Chapter 4 The Processor 117
Loop Unrolling Example
Loop:
ALU/branch
Load/store
cycle
addi $s1, $s1,16
lw
$t0, 0($s1)
nop
lw
$t1, 12($s1)
addu $t0, $t0, $s2
lw
$t2, 8($s1)
addu $t1, $t1, $s2
lw
$t3, 4($s1)
addu $t2, $t2, $s2
sw
$t0, 16($s1)
addu $t3, $t4, $s2
sw
$t1, 12($s1)
nop
sw
$t2, 8($s1)
sw
$t3, 4($s1)
bne
$s1, $zero, Loop
IPC = 14/8 = 1.75
Closer to 2, but at cost of registers and code size
Chapter 4 The Processor 118
Dynamic Multiple Issue
Superscalar processors
CPU decides whether to issue 0, 1, 2,
each cycle
Avoiding structural and data hazards
Avoids the need for compiler scheduling
Though it may still help
Code semantics ensured by the CPU
Chapter 4 The Processor 119
Dynamic Pipeline Scheduling
Allow the CPU to execute instructions out
of order to avoid stalls
But commit result to registers in order
Example
lw
$t0, 20($s2)
addu $t1, $t0, $t2
sub
$s4, $s4, $t3
slti $t5, $s4, 20
Can start sub while addu is waiting for lw
Chapter 4 The Processor 120
Dynamically Scheduled CPU
Preserves
dependencies
Hold pending
operands
Results also sent
to any waiting
reservation
stations
Reorders buffer for
register writes
Can supply
operands for
issued instructions
Chapter 4 The Processor 121
Register Renaming
Reservation stations and reorder buffer
effectively provide register renaming
On instruction issue to reservation station
If operand is available in register file or reorder
buffer
Copied to reservation station
No longer required in the register; can be
overwritten
If operand is not yet available
It will be provided to the reservation station by a
function unit
Register update may not be required
Chapter 4 The Processor 122
Speculation
Predict branch and continue issuing
Dont commit until branch outcome
determined
Load speculation
Avoid load and cache miss delay
Predict the effective address
Predict loaded value
Load before completing outstanding stores
Bypass stored values to load unit
Dont commit load until speculation cleared
Chapter 4 The Processor 123
Why Do Dynamic Scheduling?
Why not just let the compiler schedule
code?
Not all stalls are predicable
Cant always schedule around branches
e.g., cache misses
Branch outcome is dynamically determined
Different implementations of an ISA have
different latencies and hazards
Chapter 4 The Processor 124
Does Multiple Issue Work?
The BIG Picture
Yes, but not as much as wed like
Programs have real dependencies that limit ILP
Some dependencies are hard to eliminate
Some parallelism is hard to expose
Limited window size during instruction issue
Memory delays and limited bandwidth
e.g., pointer aliasing
Hard to keep pipelines full
Speculation can help if done well
Chapter 4 The Processor 125
Power Efficiency
Complexity of dynamic scheduling and
speculations requires power
Multiple simpler cores may be better
Microprocessor
Year
Clock Rate
Pipeline
Stages
Issue
width
Out-of-order/
Speculation
Cores
Power
i486
1989
25MHz
No
5W
Pentium
1993
66MHz
No
10W
Pentium Pro
1997
200MHz
10
Yes
29W
P4 Willamette
2001
2000MHz
22
Yes
75W
P4 Prescott
2004
3600MHz
31
Yes
103W
Core
2006
2930MHz
14
Yes
75W
UltraSparc III
2003
1950MHz
14
No
90W
UltraSparc T1
2005
1200MHz
No
70W
Chapter 4 The Processor 126
72 physical
registers
4.11 Real Stuff: The AMD Opteron X4 (Barcelona) Pipeline
The Opteron X4 Microarchitecture
Chapter 4 The Processor 127
The Opteron X4 Pipeline Flow
For integer operations
FP is 5 stages longer
Up to 106 RISC-ops in progress
Bottlenecks
Complex instructions with long dependencies
Branch mispredictions
Memory access delays
Chapter 4 The Processor 128
Pipelining is easy (!)
The basic idea is easy
The devil is in the details
e.g., detecting data hazards
4.13 Fallacies and Pitfalls
Fallacies
Pipelining is independent of technology
So why havent we always done pipelining?
More transistors make more advanced techniques
feasible
Pipeline-related ISA design needs to take account of
technology trends
e.g., predicated instructions
Chapter 4 The Processor 129
Pitfalls
Poor ISA design can make pipelining
harder
e.g., complex instruction sets (VAX, IA-32)
e.g., complex addressing modes
Significant overhead to make pipelining work
IA-32 micro-op approach
Register update side effects, memory indirection
e.g., delayed branches
Advanced pipelines have long delay slots
Chapter 4 The Processor 130
ISA influences design of datapath and control
Datapath and control influence design of ISA
Pipelining improves instruction throughput
using parallelism
4.14 Concluding Remarks
Concluding Remarks
More instructions completed per second
Latency for each instruction not reduced
Hazards: structural, data, control
Multiple issue and dynamic scheduling (ILP)
Dependencies limit achievable parallelism
Complexity leads to the power wall
Chapter 4 The Processor 131
